projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | #ifndef _IMX_REGS_H |
| 2 | #define _IMX_REGS_H | |
| 3 | /* ------------------------------------------------------------------------ | |
| 4 | * Motorola IMX system registers | |
| 5 | * ------------------------------------------------------------------------ | |
| 6 | * | |
| 7 | */ | |
| 8 | ||
| 9 | /* | |
| 10 | * Register BASEs, based on OFFSETs | |
| 11 | * | |
| 12 | */ | |
| 13 | #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) | |
| 14 | #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) | |
| 15 | #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) | |
| 16 | #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) | |
| 17 | #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) | |
| 18 | #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) | |
| 19 | #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) | |
| 20 | #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) | |
| 21 | #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) | |
| 22 | #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) | |
| 23 | #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) | |
| 24 | #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) | |
| 25 | #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) | |
| 26 | #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) | |
| 27 | #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) | |
| 28 | #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) | |
| 29 | #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) | |
| 30 | #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) | |
| 31 | #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) | |
| 32 | #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) | |
| 33 | #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) | |
| 34 | #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) | |
| 35 | #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) | |
| 36 | #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) | |
| 37 | #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) | |
| 38 | #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) | |
| 39 | #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) | |
| 40 | #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) | |
| 41 | ||
| 42 | /* PLL registers */ | |
| 43 | #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ | |
| 3c8cd0cc PP |
44 | #define CSCR_SPLL_RESTART (1<<22) |
| 45 | #define CSCR_MPLL_RESTART (1<<21) | |
| 46 | #define CSCR_SYSTEM_SEL (1<<16) | |
| 47 | #define CSCR_BCLK_DIV (0xf<<10) | |
| 48 | #define CSCR_MPU_PRESC (1<<15) | |
| 49 | #define CSCR_SPEN (1<<1) | |
| 50 | #define CSCR_MPEN (1<<0) | |
| 1da177e4 LT |
51 | |
| 52 | #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ | |
| 53 | #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ | |
| 54 | #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ | |
| 55 | #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ | |
| 56 | #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ | |
| 57 | ||
| 1da177e4 LT |
58 | /* |
| 59 | * GPIO Module and I/O Multiplexer | |
| 60 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | |
| 61 | */ | |
| 62 | #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) | |
| 63 | #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) | |
| 64 | #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) | |
| 65 | #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) | |
| 66 | #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) | |
| 67 | #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) | |
| 68 | #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) | |
| 69 | #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) | |
| 70 | #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) | |
| 71 | #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) | |
| 72 | #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) | |
| 73 | #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) | |
| 74 | #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) | |
| 75 | #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) | |
| 76 | #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) | |
| 77 | #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) | |
| 78 | #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) | |
| 79 | ||
| 80 | #define GPIO_PIN_MASK 0x1f | |
| 81 | #define GPIO_PORT_MASK (0x3 << 5) | |
| 82 | ||
| 0a5b0aa8 | 83 | #define GPIO_PORT_SHIFT 5 |
| 1da177e4 LT |
84 | #define GPIO_PORTA (0<<5) |
| 85 | #define GPIO_PORTB (1<<5) | |
| 86 | #define GPIO_PORTC (2<<5) | |
| 87 | #define GPIO_PORTD (3<<5) | |
| 88 | ||
| 89 | #define GPIO_OUT (1<<7) | |
| 90 | #define GPIO_IN (0<<7) | |
| 91 | #define GPIO_PUEN (1<<8) | |
| 92 | ||
| 93 | #define GPIO_PF (0<<9) | |
| 94 | #define GPIO_AF (1<<9) | |
| 95 | ||
| 0a5b0aa8 | 96 | #define GPIO_OCR_SHIFT 10 |
| 1da177e4 LT |
97 | #define GPIO_OCR_MASK (3<<10) |
| 98 | #define GPIO_AIN (0<<10) | |
| 99 | #define GPIO_BIN (1<<10) | |
| 100 | #define GPIO_CIN (2<<10) | |
| 0a5b0aa8 | 101 | #define GPIO_DR (3<<10) |
| 1da177e4 | 102 | |
| 0a5b0aa8 SH |
103 | #define GPIO_AOUT_SHIFT 12 |
| 104 | #define GPIO_AOUT_MASK (3<<12) | |
| 105 | #define GPIO_AOUT (0<<12) | |
| 106 | #define GPIO_AOUT_ISR (1<<12) | |
| 107 | #define GPIO_AOUT_0 (2<<12) | |
| 108 | #define GPIO_AOUT_1 (3<<12) | |
| 109 | ||
| 110 | #define GPIO_BOUT_SHIFT 14 | |
| 111 | #define GPIO_BOUT_MASK (3<<14) | |
| 112 | #define GPIO_BOUT (0<<14) | |
| 113 | #define GPIO_BOUT_ISR (1<<14) | |
| 114 | #define GPIO_BOUT_0 (2<<14) | |
| 115 | #define GPIO_BOUT_1 (3<<14) | |
| 116 | ||
| 117 | #define GPIO_GIUS (1<<16) | |
| 1da177e4 LT |
118 | |
| 119 | /* assignements for GPIO alternate/primary functions */ | |
| 120 | ||
| 121 | /* FIXME: This list is not completed. The correct directions are | |
| 122 | * missing on some (many) pins | |
| 123 | */ | |
| 0a5b0aa8 | 124 | #define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) |
| 1da177e4 | 125 | #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) |
| 0a5b0aa8 | 126 | #define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) |
| 1da177e4 LT |
127 | #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) |
| 128 | #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) | |
| 129 | #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) | |
| 130 | #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) | |
| 131 | #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) | |
| 132 | #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) | |
| 133 | #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) | |
| 134 | #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) | |
| 135 | #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) | |
| 136 | #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) | |
| 137 | #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) | |
| 138 | #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) | |
| 139 | #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) | |
| 140 | #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) | |
| 141 | #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) | |
| 142 | #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) | |
| 143 | #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) | |
| 0a5b0aa8 | 144 | #define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) |
| 1da177e4 LT |
145 | #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) |
| 146 | #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) | |
| 147 | #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) | |
| 148 | #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) | |
| 149 | #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) | |
| 150 | #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) | |
| 151 | #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) | |
| 152 | #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) | |
| 153 | #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) | |
| 154 | #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) | |
| 155 | #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) | |
| 156 | #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) | |
| 157 | #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) | |
| 158 | #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) | |
| 159 | #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) | |
| 160 | #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) | |
| 161 | #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) | |
| 162 | #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) | |
| 163 | #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) | |
| 164 | #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) | |
| 165 | #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) | |
| 166 | #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) | |
| 167 | #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) | |
| 168 | #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) | |
| 169 | #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) | |
| 170 | #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) | |
| 171 | #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) | |
| 172 | #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) | |
| 173 | #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) | |
| 174 | #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) | |
| 175 | #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) | |
| 176 | #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) | |
| 177 | #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) | |
| 178 | #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) | |
| 179 | #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) | |
| 180 | #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) | |
| 181 | #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) | |
| 182 | #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) | |
| 183 | #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) | |
| 184 | #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) | |
| 185 | #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) | |
| 186 | #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) | |
| 187 | #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) | |
| 188 | #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) | |
| 189 | #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) | |
| 190 | #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) | |
| 191 | #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) | |
| 192 | #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) | |
| 193 | #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) | |
| 194 | #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) | |
| 195 | #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) | |
| 196 | #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) | |
| 197 | #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) | |
| 198 | #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) | |
| 199 | #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) | |
| 200 | #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) | |
| 201 | #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) | |
| 202 | #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) | |
| 203 | #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) | |
| 204 | #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) | |
| 205 | #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) | |
| 206 | #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) | |
| 207 | #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) | |
| 208 | #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) | |
| 209 | #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) | |
| 210 | #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) | |
| 211 | #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) | |
| 0a5b0aa8 SH |
212 | #define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) |
| 213 | #define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) | |
| 214 | #define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) | |
| 215 | #define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) | |
| 216 | #define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) | |
| 217 | #define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) | |
| 218 | #define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) | |
| 219 | #define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) | |
| 1da177e4 LT |
220 | #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) |
| 221 | #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) | |
| 79d13b62 | 222 | #define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) |
| 0a5b0aa8 | 223 | #define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) |
| 1da177e4 LT |
224 | #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) |
| 225 | #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) | |
| 0a5b0aa8 | 226 | #define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) |
| 1da177e4 LT |
227 | #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) |
| 228 | #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) | |
| 0a5b0aa8 | 229 | #define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) |
| 1da177e4 LT |
230 | #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) |
| 231 | #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) | |
| 0a5b0aa8 | 232 | #define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) |
| 1da177e4 LT |
233 | #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) |
| 234 | #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) | |
| 235 | #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) | |
| 236 | #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) | |
| 237 | #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) | |
| 238 | #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) | |
| 239 | #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) | |
| 240 | #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) | |
| 241 | #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) | |
| 242 | #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) | |
| 243 | #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) | |
| 244 | #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) | |
| 245 | #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) | |
| 246 | #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) | |
| 247 | #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) | |
| 248 | #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) | |
| 249 | #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) | |
| 250 | #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) | |
| 251 | #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) | |
| 252 | #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) | |
| 253 | #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) | |
| 0a5b0aa8 | 254 | #define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) |
| 1da177e4 | 255 | |
| d7def6c2 SH |
256 | /* |
| 257 | * PWM controller | |
| 258 | */ | |
| 259 | #define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ | |
| 260 | #define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ | |
| 261 | #define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ | |
| 262 | #define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ | |
| 263 | ||
| 264 | #define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ | |
| 265 | #define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ | |
| 266 | #define PWMC_SWR (0x01<<16) /* Software Reset */ | |
| 267 | #define PWMC_CLKSRC (0x01<<15) /* Clock Source */ | |
| 268 | #define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ | |
| 269 | #define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ | |
| 270 | #define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ | |
| 271 | #define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ | |
| 272 | #define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ | |
| 273 | #define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ | |
| 274 | #define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ | |
| 275 | ||
| 276 | #define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ | |
| 277 | #define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ | |
| 278 | #define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ | |
| 279 | ||
| 1da177e4 LT |
280 | /* |
| 281 | * DMA Controller | |
| 282 | */ | |
| 283 | #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ | |
| 284 | #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ | |
| 285 | #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ | |
| 286 | #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ | |
| 287 | #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ | |
| 288 | #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ | |
| 289 | #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ | |
| 290 | #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ | |
| 291 | #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ | |
| 292 | #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ | |
| 293 | #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ | |
| 294 | #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ | |
| 295 | #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ | |
| 296 | #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ | |
| 297 | #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ | |
| 298 | #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ | |
| 299 | #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ |