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1da177e4 LT |
1 | #ifndef _IMX_REGS_H |
2 | #define _IMX_REGS_H | |
3 | /* ------------------------------------------------------------------------ | |
4 | * Motorola IMX system registers | |
5 | * ------------------------------------------------------------------------ | |
6 | * | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Register BASEs, based on OFFSETs | |
11 | * | |
12 | */ | |
13 | #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) | |
14 | #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) | |
15 | #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) | |
16 | #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) | |
17 | #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) | |
18 | #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) | |
19 | #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) | |
20 | #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) | |
21 | #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) | |
22 | #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) | |
23 | #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) | |
24 | #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) | |
25 | #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) | |
26 | #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) | |
27 | #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) | |
28 | #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) | |
29 | #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) | |
30 | #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) | |
31 | #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) | |
32 | #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) | |
33 | #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) | |
34 | #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) | |
35 | #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) | |
36 | #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) | |
37 | #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) | |
38 | #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) | |
39 | #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) | |
40 | #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) | |
41 | ||
42 | /* PLL registers */ | |
43 | #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ | |
3c8cd0cc PP |
44 | #define CSCR_SPLL_RESTART (1<<22) |
45 | #define CSCR_MPLL_RESTART (1<<21) | |
46 | #define CSCR_SYSTEM_SEL (1<<16) | |
47 | #define CSCR_BCLK_DIV (0xf<<10) | |
48 | #define CSCR_MPU_PRESC (1<<15) | |
49 | #define CSCR_SPEN (1<<1) | |
50 | #define CSCR_MPEN (1<<0) | |
1da177e4 LT |
51 | |
52 | #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ | |
53 | #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ | |
54 | #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ | |
55 | #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ | |
56 | #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ | |
57 | ||
1da177e4 LT |
58 | /* |
59 | * GPIO Module and I/O Multiplexer | |
60 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | |
61 | */ | |
62 | #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) | |
63 | #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) | |
64 | #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) | |
65 | #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) | |
66 | #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) | |
67 | #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) | |
68 | #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) | |
69 | #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) | |
70 | #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) | |
71 | #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) | |
72 | #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) | |
73 | #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) | |
74 | #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) | |
75 | #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) | |
76 | #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) | |
77 | #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) | |
78 | #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) | |
79 | ||
b3e6a508 PP |
80 | #define GPIO_PORT_MAX 3 |
81 | ||
1da177e4 LT |
82 | #define GPIO_PIN_MASK 0x1f |
83 | #define GPIO_PORT_MASK (0x3 << 5) | |
84 | ||
0a5b0aa8 | 85 | #define GPIO_PORT_SHIFT 5 |
1da177e4 LT |
86 | #define GPIO_PORTA (0<<5) |
87 | #define GPIO_PORTB (1<<5) | |
88 | #define GPIO_PORTC (2<<5) | |
89 | #define GPIO_PORTD (3<<5) | |
90 | ||
91 | #define GPIO_OUT (1<<7) | |
92 | #define GPIO_IN (0<<7) | |
93 | #define GPIO_PUEN (1<<8) | |
94 | ||
95 | #define GPIO_PF (0<<9) | |
96 | #define GPIO_AF (1<<9) | |
97 | ||
0a5b0aa8 | 98 | #define GPIO_OCR_SHIFT 10 |
1da177e4 LT |
99 | #define GPIO_OCR_MASK (3<<10) |
100 | #define GPIO_AIN (0<<10) | |
101 | #define GPIO_BIN (1<<10) | |
102 | #define GPIO_CIN (2<<10) | |
0a5b0aa8 | 103 | #define GPIO_DR (3<<10) |
1da177e4 | 104 | |
0a5b0aa8 SH |
105 | #define GPIO_AOUT_SHIFT 12 |
106 | #define GPIO_AOUT_MASK (3<<12) | |
107 | #define GPIO_AOUT (0<<12) | |
108 | #define GPIO_AOUT_ISR (1<<12) | |
109 | #define GPIO_AOUT_0 (2<<12) | |
110 | #define GPIO_AOUT_1 (3<<12) | |
111 | ||
112 | #define GPIO_BOUT_SHIFT 14 | |
113 | #define GPIO_BOUT_MASK (3<<14) | |
114 | #define GPIO_BOUT (0<<14) | |
115 | #define GPIO_BOUT_ISR (1<<14) | |
116 | #define GPIO_BOUT_0 (2<<14) | |
117 | #define GPIO_BOUT_1 (3<<14) | |
118 | ||
119 | #define GPIO_GIUS (1<<16) | |
1da177e4 LT |
120 | |
121 | /* assignements for GPIO alternate/primary functions */ | |
122 | ||
123 | /* FIXME: This list is not completed. The correct directions are | |
124 | * missing on some (many) pins | |
125 | */ | |
0a5b0aa8 | 126 | #define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) |
1da177e4 | 127 | #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) |
0a5b0aa8 | 128 | #define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) |
1da177e4 LT |
129 | #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) |
130 | #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) | |
131 | #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) | |
132 | #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) | |
133 | #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) | |
134 | #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) | |
135 | #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) | |
136 | #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) | |
137 | #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) | |
138 | #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) | |
139 | #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) | |
140 | #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) | |
141 | #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) | |
142 | #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) | |
143 | #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) | |
144 | #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) | |
145 | #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) | |
0a5b0aa8 | 146 | #define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) |
1da177e4 LT |
147 | #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) |
148 | #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) | |
149 | #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) | |
150 | #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) | |
151 | #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) | |
152 | #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) | |
153 | #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) | |
154 | #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) | |
155 | #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) | |
156 | #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) | |
157 | #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) | |
158 | #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) | |
159 | #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) | |
160 | #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) | |
161 | #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) | |
162 | #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) | |
163 | #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) | |
164 | #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) | |
165 | #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) | |
166 | #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) | |
167 | #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) | |
168 | #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) | |
169 | #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) | |
170 | #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) | |
171 | #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) | |
172 | #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) | |
173 | #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) | |
174 | #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) | |
175 | #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) | |
176 | #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) | |
177 | #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) | |
178 | #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) | |
179 | #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) | |
180 | #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) | |
181 | #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) | |
182 | #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) | |
183 | #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) | |
184 | #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) | |
185 | #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) | |
186 | #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) | |
187 | #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) | |
188 | #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) | |
189 | #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) | |
190 | #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) | |
191 | #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) | |
192 | #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) | |
193 | #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) | |
194 | #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) | |
195 | #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) | |
196 | #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) | |
197 | #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) | |
198 | #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) | |
199 | #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) | |
200 | #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) | |
201 | #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) | |
202 | #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) | |
203 | #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) | |
204 | #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) | |
205 | #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) | |
206 | #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) | |
207 | #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) | |
208 | #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) | |
209 | #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) | |
210 | #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) | |
211 | #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) | |
212 | #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) | |
213 | #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) | |
0a5b0aa8 SH |
214 | #define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) |
215 | #define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) | |
216 | #define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) | |
217 | #define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) | |
218 | #define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) | |
219 | #define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) | |
220 | #define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) | |
221 | #define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) | |
1da177e4 LT |
222 | #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) |
223 | #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) | |
79d13b62 | 224 | #define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) |
0a5b0aa8 | 225 | #define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) |
1da177e4 LT |
226 | #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) |
227 | #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) | |
0a5b0aa8 | 228 | #define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) |
1da177e4 LT |
229 | #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) |
230 | #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) | |
0a5b0aa8 | 231 | #define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) |
1da177e4 LT |
232 | #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) |
233 | #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) | |
0a5b0aa8 | 234 | #define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) |
1da177e4 LT |
235 | #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) |
236 | #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) | |
237 | #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) | |
238 | #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) | |
239 | #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) | |
240 | #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) | |
241 | #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) | |
242 | #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) | |
243 | #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) | |
244 | #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) | |
245 | #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) | |
246 | #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) | |
247 | #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) | |
248 | #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) | |
249 | #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) | |
250 | #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) | |
251 | #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) | |
252 | #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) | |
253 | #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) | |
254 | #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) | |
255 | #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) | |
0a5b0aa8 | 256 | #define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) |
1da177e4 | 257 | |
d7def6c2 SH |
258 | /* |
259 | * PWM controller | |
260 | */ | |
261 | #define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ | |
262 | #define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ | |
263 | #define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ | |
264 | #define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ | |
265 | ||
266 | #define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ | |
267 | #define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ | |
268 | #define PWMC_SWR (0x01<<16) /* Software Reset */ | |
269 | #define PWMC_CLKSRC (0x01<<15) /* Clock Source */ | |
270 | #define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ | |
271 | #define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ | |
272 | #define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ | |
273 | #define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ | |
274 | #define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ | |
275 | #define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ | |
276 | #define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ | |
277 | ||
278 | #define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ | |
279 | #define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ | |
280 | #define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ | |
281 | ||
1da177e4 LT |
282 | /* |
283 | * DMA Controller | |
284 | */ | |
285 | #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ | |
286 | #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ | |
287 | #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ | |
288 | #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ | |
289 | #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ | |
290 | #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ | |
291 | #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ | |
292 | #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ | |
293 | #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ | |
294 | #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ | |
295 | #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ | |
296 | #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ | |
297 | #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ | |
298 | #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ | |
299 | #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ | |
300 | #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ | |
301 | #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ | |
121e70b6 | 302 | #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ |
1da177e4 LT |
303 | #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ |
304 | #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ | |
305 | #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ | |
306 | #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ | |
307 | ||
308 | #define DCR_DRST (1<<1) | |
309 | #define DCR_DEN (1<<0) | |
310 | #define DBTOCR_EN (1<<15) | |
311 | #define DBTOCR_CNT(x) ((x) & 0x7fff ) | |
312 | #define CNTR_CNT(x) ((x) & 0xffffff ) | |
313 | #define CCR_DMOD_LINEAR ( 0x0 << 12 ) | |
314 | #define CCR_DMOD_2D ( 0x1 << 12 ) | |
315 | #define CCR_DMOD_FIFO ( 0x2 << 12 ) | |
316 | #define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) | |
317 | #define CCR_SMOD_LINEAR ( 0x0 << 10 ) | |
318 | #define CCR_SMOD_2D ( 0x1 << 10 ) | |
319 | #define CCR_SMOD_FIFO ( 0x2 << 10 ) | |
320 | #define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) | |
321 | #define CCR_MDIR_DEC (1<<9) | |
322 | #define CCR_MSEL_B (1<<8) | |
323 | #define CCR_DSIZ_32 ( 0x0 << 6 ) | |
324 | #define CCR_DSIZ_8 ( 0x1 << 6 ) | |
325 | #define CCR_DSIZ_16 ( 0x2 << 6 ) | |
326 | #define CCR_SSIZ_32 ( 0x0 << 4 ) | |
327 | #define CCR_SSIZ_8 ( 0x1 << 4 ) | |
328 | #define CCR_SSIZ_16 ( 0x2 << 4 ) | |
329 | #define CCR_REN (1<<3) | |
330 | #define CCR_RPT (1<<2) | |
331 | #define CCR_FRC (1<<1) | |
332 | #define CCR_CEN (1<<0) | |
333 | #define RTOR_EN (1<<15) | |
334 | #define RTOR_CLK (1<<14) | |
335 | #define RTOR_PSC (1<<13) | |
336 | ||
337 | /* | |
338 | * Interrupt controller | |
339 | */ | |
340 | ||
341 | #define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00) | |
342 | #define INTCNTL_FIAD (1<<19) | |
343 | #define INTCNTL_NIAD (1<<20) | |
344 | ||
345 | #define IMX_NIMASK __REG(IMX_AITC_BASE+0x04) | |
346 | #define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08) | |
347 | #define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c) | |
348 | #define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10) | |
349 | #define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14) | |
350 | ||
351 | /* | |
352 | * General purpose timers | |
353 | */ | |
354 | #define IMX_TCTL(x) __REG( 0x00 + (x)) | |
355 | #define TCTL_SWR (1<<15) | |
356 | #define TCTL_FRR (1<<8) | |
357 | #define TCTL_CAP_RIS (1<<6) | |
358 | #define TCTL_CAP_FAL (2<<6) | |
359 | #define TCTL_CAP_RIS_FAL (3<<6) | |
360 | #define TCTL_OM (1<<5) | |
361 | #define TCTL_IRQEN (1<<4) | |
362 | #define TCTL_CLK_PCLK1 (1<<1) | |
363 | #define TCTL_CLK_PCLK1_16 (2<<1) | |
364 | #define TCTL_CLK_TIN (3<<1) | |
365 | #define TCTL_CLK_32 (4<<1) | |
366 | #define TCTL_TEN (1<<0) | |
367 | ||
368 | #define IMX_TPRER(x) __REG( 0x04 + (x)) | |
369 | #define IMX_TCMP(x) __REG( 0x08 + (x)) | |
370 | #define IMX_TCR(x) __REG( 0x0C + (x)) | |
371 | #define IMX_TCN(x) __REG( 0x10 + (x)) | |
372 | #define IMX_TSTAT(x) __REG( 0x14 + (x)) | |
373 | #define TSTAT_CAPT (1<<1) | |
374 | #define TSTAT_COMP (1<<0) | |
375 | ||
376 | /* | |
377 | * LCD Controller | |
378 | */ | |
379 | ||
380 | #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) | |
381 | ||
382 | #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) | |
383 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) | |
384 | #define SIZE_YMAX(y) ( (y) & 0x1ff ) | |
385 | ||
386 | #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) | |
387 | #define VPW_VPW(x) ( (x) & 0x3ff ) | |
388 | ||
389 | #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) | |
390 | #define CPOS_CC1 (1<<31) | |
391 | #define CPOS_CC0 (1<<30) | |
392 | #define CPOS_OP (1<<28) | |
393 | #define CPOS_CXP(x) (((x) & 3ff) << 16) | |
394 | #define CPOS_CYP(y) ((y) & 0x1ff) | |
395 | ||
396 | #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) | |
397 | #define LCWHB_BK_EN (1<<31) | |
398 | #define LCWHB_CW(w) (((w) & 0x1f) << 24) | |
399 | #define LCWHB_CH(h) (((h) & 0x1f) << 16) | |
400 | #define LCWHB_BD(x) ((x) & 0xff) | |
401 | ||
402 | #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) | |
403 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) | |
404 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) | |
405 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) | |
406 | ||
407 | #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) | |
408 | #define PCR_TFT (1<<31) | |
409 | #define PCR_COLOR (1<<30) | |
410 | #define PCR_PBSIZ_1 (0<<28) | |
411 | #define PCR_PBSIZ_2 (1<<28) | |
412 | #define PCR_PBSIZ_4 (2<<28) | |
413 | #define PCR_PBSIZ_8 (3<<28) | |
414 | #define PCR_BPIX_1 (0<<25) | |
415 | #define PCR_BPIX_2 (1<<25) | |
416 | #define PCR_BPIX_4 (2<<25) | |
417 | #define PCR_BPIX_8 (3<<25) | |
418 | #define PCR_BPIX_12 (4<<25) | |
419 | #define PCR_BPIX_16 (4<<25) | |
420 | #define PCR_PIXPOL (1<<24) | |
421 | #define PCR_FLMPOL (1<<23) | |
422 | #define PCR_LPPOL (1<<22) | |
423 | #define PCR_CLKPOL (1<<21) | |
424 | #define PCR_OEPOL (1<<20) | |
425 | #define PCR_SCLKIDLE (1<<19) | |
426 | #define PCR_END_SEL (1<<18) | |
427 | #define PCR_END_BYTE_SWAP (1<<17) | |
428 | #define PCR_REV_VS (1<<16) | |
429 | #define PCR_ACD_SEL (1<<15) | |
430 | #define PCR_ACD(x) (((x) & 0x7f) << 8) | |
431 | #define PCR_SCLK_SEL (1<<7) | |
432 | #define PCR_SHARP (1<<6) | |
433 | #define PCR_PCD(x) ((x) & 0x3f) | |
434 | ||
435 | #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) | |
436 | #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) | |
437 | #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) | |
438 | #define HCR_H_WAIT_2(x) ((x) & 0xff) | |
439 | ||
440 | #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) | |
441 | #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) | |
442 | #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) | |
443 | #define VCR_V_WAIT_2(x) ((x) & 0xff) | |
444 | ||
445 | #define LCDC_POS __REG(IMX_LCDC_BASE+0x24) | |
446 | #define POS_POS(x) ((x) & 1f) | |
447 | ||
448 | #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) | |
449 | #define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) | |
450 | #define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) | |
451 | #define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) | |
452 | #define LSCR1_GRAY2(x) (((x) & 0xf) << 4) | |
453 | #define LSCR1_GRAY1(x) (((x) & 0xf)) | |
454 | ||
455 | #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) | |
456 | #define PWMR_CLS(x) (((x) & 0x1ff) << 16) | |
457 | #define PWMR_LDMSK (1<<15) | |
458 | #define PWMR_SCR1 (1<<10) | |
459 | #define PWMR_SCR0 (1<<9) | |
460 | #define PWMR_CC_EN (1<<8) | |
461 | #define PWMR_PW(x) ((x) & 0xff) | |
462 | ||
463 | #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) | |
464 | #define DMACR_BURST (1<<31) | |
465 | #define DMACR_HM(x) (((x) & 0xf) << 16) | |
466 | #define DMACR_TM(x) ((x) &0xf) | |
467 | ||
468 | #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) | |
469 | #define RMCR_LCDC_EN (1<<1) | |
470 | #define RMCR_SELF_REF (1<<0) | |
471 | ||
472 | #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) | |
473 | #define LCDICR_INT_SYN (1<<2) | |
474 | #define LCDICR_INT_CON (1) | |
475 | ||
476 | #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) | |
477 | #define LCDISR_UDR_ERR (1<<3) | |
478 | #define LCDISR_ERR_RES (1<<2) | |
479 | #define LCDISR_EOF (1<<1) | |
480 | #define LCDISR_BOF (1<<0) | |
481 | ||
1da177e4 | 482 | #endif // _IMX_REGS_H |