[deliverable/linux.git] / include / asm-arm / arch-ixp2000 / io.h

/*
 * linux/include/asm-arm/arch-ixp2000/io.h
 *
 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright (C) 2002  Intel Corp.
 * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H

#include <asm/hardware.h>

#define IO_SPACE_LIMIT		0xffffffff
#define __mem_pci(a)		(a)

/*
 * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
 * transactions the other way round (MEM transactions don't have this
 * issue), so if we want to support those models, we need to override
 * the standard I/O functions.
 *
 * B0 and later have a bit that can be set to 1 to get the proper
 * behavior for I/O transactions, which then allows us to use the
 * standard I/O functions.  This is what we do if the user does not
 * explicitly ask for support for pre-B0.
 */
#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
#define ___io(p)		((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))

#define alignb(addr)		(void __iomem *)((unsigned long)(addr) ^ 3)
#define alignw(addr)		(void __iomem *)((unsigned long)(addr) ^ 2)

#define outb(v,p)		__raw_writeb((v),alignb(___io(p)))
#define outw(v,p)		__raw_writew((v),alignw(___io(p)))
#define outl(v,p)		__raw_writel((v),___io(p))

#define inb(p)		({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
#define inw(p)		\
	({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
#define inl(p)		\
	({ unsigned int __v = (__raw_readl(___io(p))); __v; })

#define outsb(p,d,l)		__raw_writesb(alignb(___io(p)),d,l)
#define outsw(p,d,l)		__raw_writesw(alignw(___io(p)),d,l)
#define outsl(p,d,l)		__raw_writesl(___io(p),d,l)

#define insb(p,d,l)		__raw_readsb(alignb(___io(p)),d,l)
#define insw(p,d,l)		__raw_readsw(alignw(___io(p)),d,l)
#define insl(p,d,l)		__raw_readsl(___io(p),d,l)

#define __is_io_address(p)	((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)

#define ioread8(p)						\
	({							\
		unsigned int __v;				\
								\
		if (__is_io_address(p)) {			\
			__v = __raw_readb(alignb(p));		\
		} else {					\
			__v = __raw_readb(p);			\
		}						\
								\
		__v;						\
	})							\

#define ioread16(p)						\
	({							\
		unsigned int __v;				\
								\
		if (__is_io_address(p)) {			\
			__v = __raw_readw(alignw(p));		\
		} else {					\
			__v = le16_to_cpu(__raw_readw(p));	\
		}						\
								\
		__v;						\
	})

#define ioread32(p)						\
	({							\
		unsigned int __v;				\
								\
		if (__is_io_address(p)) {			\
			__v = __raw_readl(p);			\
		} else {					\
			__v = le32_to_cpu(__raw_readl(p));	\
		}						\
								\
		 __v;						\
	})

#define iowrite8(v,p)						\
	({							\
		if (__is_io_address(p)) {			\
			__raw_writeb((v), alignb(p));		\
		} else {					\
			__raw_writeb((v), p);			\
		}						\
	})

#define iowrite16(v,p)						\
	({							\
		if (__is_io_address(p)) {			\
			__raw_writew((v), alignw(p));		\
		} else {					\
			__raw_writew(cpu_to_le16(v), p);	\
		}						\
	})

#define iowrite32(v,p)						\
	({							\
		if (__is_io_address(p)) {			\
			__raw_writel((v), p);			\
		} else {					\
			__raw_writel(cpu_to_le32(v), p);	\
		}						\
	})

#define ioport_map(port, nr)	___io(port)

#define ioport_unmap(addr)
#else
#define __io(p)			((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
#endif


#ifdef CONFIG_ARCH_IXDP2X01
/*
 * This is an ugly hack but the CS8900 on the 2x01's does not sit in any sort
 * of "I/O space" and is just direct mapped into a 32-bit-only addressable
 * bus. The address space for this bus is such that we can't really easily
 * make it contiguous to the PCI I/O address range, and it also does not
 * need swapping like PCI addresses do (IXDP2x01 is a BE platform).
 * B/C of this we can't use the standard in/out functions and need to
 * runtime check if the incoming address is a PCI address or for
 * the CS89x0.
 */
#undef inw
#undef outw
#undef insw
#undef outsw

#include <asm/mach-types.h>

static inline void insw(u32 ptr, void *buf, int length)
{
	register volatile u32 *port = (volatile u32 *)ptr;

	/*
	 * Is this cycle meant for the CS8900?
	 */
	if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
		(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
		 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
		u8 *buf8 = (u8*)buf;
		register u32 tmp32;

		do {
			tmp32 = *port;
			*buf8++ = (u8)tmp32;
			*buf8++ = (u8)(tmp32 >> 8);
		} while(--length);

		return;
	}

	__raw_readsw(alignw(___io(ptr)),buf,length);
}

static inline void outsw(u32 ptr, void *buf, int length)
{
	register volatile u32 *port = (volatile u32 *)ptr;

	/*
	 * Is this cycle meant for the CS8900?
	 */
	if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
		(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
		 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
		register u32 tmp32;
		u8 *buf8 = (u8*)buf;
		do {
			tmp32 = *buf8++;
			tmp32 |= (*buf8++) << 8;
			*port = tmp32;
		} while(--length);
		return;
	}

	__raw_writesw(alignw(___io(ptr)),buf,length);
}


static inline u16 inw(u32 ptr)
{
	register volatile u32 *port = (volatile u32 *)ptr;

	/*
	 * Is this cycle meant for the CS8900?
	 */
	if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
		(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
		 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
		return (u16)(*port);  
	}

	return __raw_readw(alignw(___io(ptr)));
}

static inline void outw(u16 value, u32 ptr)
{
	register volatile u32 *port = (volatile u32 *)ptr;

	if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
		(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
		 ((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
		*port = value;  
		return;
	}

	__raw_writew((value),alignw(___io(ptr)));
}
#endif	/* IXDP2x01 */

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-arm/arch-ixp2000/io.h
	3	*
	4	* Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
	5	* Maintainer: Deepak Saxena <dsaxena@plexity.net>
	6	*
	7	* Copyright (C) 2002 Intel Corp.
	8	* Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#ifndef __ASM_ARM_ARCH_IO_H
	16	#define __ASM_ARM_ARCH_IO_H
	17
7fca0aa4 RK	18	#include <asm/hardware.h>
7fca0aa4 RK	19
1da177e4 LT	20	#define IO_SPACE_LIMIT 0xffffffff
1da177e4 LT	21	#define __mem_pci(a) (a)
1da177e4 LT	22
1da177e4 LT	23	/*
321ab6a5	24	* The A? revisions of the IXP2000s assert byte lanes for PCI I/O
1da177e4	25	* transactions the other way round (MEM transactions don't have this
321ab6a5 LB	26	* issue), so if we want to support those models, we need to override
	27	* the standard I/O functions.
	28	*
	29	* B0 and later have a bit that can be set to 1 to get the proper
	30	* behavior for I/O transactions, which then allows us to use the
	31	* standard I/O functions. This is what we do if the user does not
	32	* explicitly ask for support for pre-B0.
1da177e4	33	*/
321ab6a5 LB	34	#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
	35	#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
	36
c6b56949 LB	37	#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
c6b56949 LB	38	#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
1da177e4 LT	39
	40	#define outb(v,p) __raw_writeb((v),alignb(___io(p)))
	41	#define outw(v,p) __raw_writew((v),alignw(___io(p)))
	42	#define outl(v,p) __raw_writel((v),___io(p))
	43
	44	#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
	45	#define inw(p) \
	46	({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
	47	#define inl(p) \
	48	({ unsigned int __v = (__raw_readl(___io(p))); __v; })
	49
	50	#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
	51	#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
	52	#define outsl(p,d,l) __raw_writesl(___io(p),d,l)
	53
	54	#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
	55	#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
	56	#define insl(p,d,l) __raw_readsl(___io(p),d,l)
	57
2966207c LB	58	#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
	59
	60	#define ioread8(p) \
	61	({ \
	62	unsigned int __v; \
	63	\
	64	if (__is_io_address(p)) { \
	65	__v = __raw_readb(alignb(p)); \
	66	} else { \
	67	__v = __raw_readb(p); \
	68	} \
	69	\
	70	__v; \
	71	}) \
	72
	73	#define ioread16(p) \
	74	({ \
	75	unsigned int __v; \
	76	\
	77	if (__is_io_address(p)) { \
	78	__v = __raw_readw(alignw(p)); \
	79	} else { \
	80	__v = le16_to_cpu(__raw_readw(p)); \
	81	} \
	82	\
	83	__v; \
	84	})
	85
	86	#define ioread32(p) \
	87	({ \
	88	unsigned int __v; \
	89	\
	90	if (__is_io_address(p)) { \
	91	__v = __raw_readl(p); \
	92	} else { \
	93	__v = le32_to_cpu(__raw_readl(p)); \
	94	} \
	95	\
	96	__v; \
	97	})
	98
	99	#define iowrite8(v,p) \
	100	({ \
	101	if (__is_io_address(p)) { \
	102	__raw_writeb((v), alignb(p)); \
	103	} else { \
	104	__raw_writeb((v), p); \
	105	} \
	106	})
	107
	108	#define iowrite16(v,p) \
	109	({ \
	110	if (__is_io_address(p)) { \
	111	__raw_writew((v), alignw(p)); \
	112	} else { \
	113	__raw_writew(cpu_to_le16(v), p); \
	114	} \
	115	})
	116
	117	#define iowrite32(v,p) \
	118	({ \
	119	if (__is_io_address(p)) { \
	120	__raw_writel((v), p); \
	121	} else { \
122	__raw_writel(cpu_to_le32(v), p); \
123	} \
124	})
125
126	#define ioport_map(port, nr) ___io(port)
127
128	#define ioport_unmap(addr)
321ab6a5 LB	129	#else
	130	#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
	131	#endif
2966207c	132
1da177e4 LT	133
	134	#ifdef CONFIG_ARCH_IXDP2X01
	135	/*
	136	* This is an ugly hack but the CS8900 on the 2x01's does not sit in any sort
	137	* of "I/O space" and is just direct mapped into a 32-bit-only addressable
	138	* bus. The address space for this bus is such that we can't really easily
	139	* make it contiguous to the PCI I/O address range, and it also does not
	140	* need swapping like PCI addresses do (IXDP2x01 is a BE platform).
	141	* B/C of this we can't use the standard in/out functions and need to
	142	* runtime check if the incoming address is a PCI address or for
	143	* the CS89x0.
	144	*/
	145	#undef inw
	146	#undef outw
	147	#undef insw
	148	#undef outsw
	149
	150	#include <asm/mach-types.h>
	151
	152	static inline void insw(u32 ptr, void *buf, int length)
	153	{
	154	register volatile u32 port = (volatile u32 )ptr;
	155
	156	/*
	157	* Is this cycle meant for the CS8900?
	158	*/
	159	if ((machine_is_ixdp2401() \|\| machine_is_ixdp2801()) &&
4ab5c01c DS	160	(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
4ab5c01c DS	161	((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
1da177e4 LT	162	u8 buf8 = (u8)buf;
	163	register u32 tmp32;
	164
	165	do {
	166	tmp32 = *port;
	167	*buf8++ = (u8)tmp32;
	168	*buf8++ = (u8)(tmp32 >> 8);
	169	} while(--length);
	170
	171	return;
	172	}
	173
	174	__raw_readsw(alignw(___io(ptr)),buf,length);
	175	}
	176
	177	static inline void outsw(u32 ptr, void *buf, int length)
	178	{
	179	register volatile u32 port = (volatile u32 )ptr;
	180
	181	/*
	182	* Is this cycle meant for the CS8900?
	183	*/
	184	if ((machine_is_ixdp2401() \|\| machine_is_ixdp2801()) &&
4ab5c01c DS	185	(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
4ab5c01c DS	186	((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
1da177e4 LT	187	register u32 tmp32;
	188	u8 buf8 = (u8)buf;
	189	do {
	190	tmp32 = *buf8++;
	191	tmp32 \|= (*buf8++) << 8;
	192	*port = tmp32;
	193	} while(--length);
	194	return;
	195	}
	196
	197	__raw_writesw(alignw(___io(ptr)),buf,length);
	198	}
	199
	200
	201	static inline u16 inw(u32 ptr)
	202	{
	203	register volatile u32 port = (volatile u32 )ptr;
	204
	205	/*
	206	* Is this cycle meant for the CS8900?
	207	*/
	208	if ((machine_is_ixdp2401() \|\| machine_is_ixdp2801()) &&
4ab5c01c DS	209	(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
4ab5c01c DS	210	((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
1da177e4 LT	211	return (u16)(*port);
	212	}
	213
	214	return __raw_readw(alignw(___io(ptr)));
	215	}
	216
	217	static inline void outw(u16 value, u32 ptr)
	218	{
	219	register volatile u32 port = (volatile u32 )ptr;
	220
	221	if ((machine_is_ixdp2401() \|\| machine_is_ixdp2801()) &&
4ab5c01c DS	222	(((u32)port >= (u32)IXDP2X01_CS8900_VIRT_BASE) &&
4ab5c01c DS	223	((u32)port <= (u32)IXDP2X01_CS8900_VIRT_END))) {
1da177e4 LT	224	*port = value;
	225	return;
	226	}
	227
	228	__raw_writew((value),alignw(___io(ptr)));
	229	}
	230	#endif /* IXDP2x01 */
	231
	232	#endif