Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | |
3 | * | |
4 | * Register definitions for IXP4xx chipset. This file contains | |
5 | * register location and bit definitions only. Platform specific | |
6 | * definitions and helper function declarations are in platform.h | |
7 | * and machine-name.h. | |
8 | * | |
9 | * Copyright (C) 2002 Intel Corporation. | |
10 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #ifndef __ASM_ARCH_HARDWARE_H__ | |
19 | #error "Do not include this directly, instead #include <asm/hardware.h>" | |
20 | #endif | |
21 | ||
22 | #ifndef _ASM_ARM_IXP4XX_H_ | |
23 | #define _ASM_ARM_IXP4XX_H_ | |
24 | ||
25 | /* | |
26 | * IXP4xx Linux Memory Map: | |
27 | * | |
28 | * Phy Size Virt Description | |
29 | * ========================================================================= | |
30 | * | |
31 | * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM | |
32 | * | |
33 | * 0x48000000 0x04000000 ioremap'd PCI Memory Space | |
34 | * | |
35 | * 0x50000000 0x10000000 ioremap'd EXP BUS | |
36 | * | |
37 | * 0x6000000 0x00004000 ioremap'd QMgr | |
38 | * | |
39 | * 0xC0000000 0x00001000 0xffbfe000 PCI CFG | |
40 | * | |
41 | * 0xC4000000 0x00001000 0xffbfd000 EXP CFG | |
42 | * | |
43 | * 0xC8000000 0x0000C000 0xffbf2000 On-Chip Peripherals | |
44 | */ | |
45 | ||
46 | /* | |
47 | * Queue Manager | |
48 | */ | |
49 | #define IXP4XX_QMGR_BASE_PHYS (0x60000000) | |
50 | ||
51 | /* | |
52 | * Expansion BUS Configuration registers | |
53 | */ | |
54 | #define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000) | |
55 | #define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFD000) | |
56 | #define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000) | |
57 | ||
58 | /* | |
59 | * PCI Config registers | |
60 | */ | |
61 | #define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000) | |
62 | #define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFE000) | |
63 | #define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000) | |
64 | ||
65 | /* | |
66 | * Peripheral space | |
67 | */ | |
68 | #define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000) | |
69 | #define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000) | |
70 | #define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000) | |
71 | ||
5932ae3f DS |
72 | /* |
73 | * Debug UART | |
74 | * | |
75 | * This is basically a remap of UART1 into a region that is section | |
76 | * aligned so that it * can be used with the low-level debug code. | |
77 | */ | |
78 | #define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000) | |
79 | #define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000) | |
80 | #define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000) | |
81 | ||
1da177e4 LT |
82 | #define IXP4XX_EXP_CS0_OFFSET 0x00 |
83 | #define IXP4XX_EXP_CS1_OFFSET 0x04 | |
84 | #define IXP4XX_EXP_CS2_OFFSET 0x08 | |
85 | #define IXP4XX_EXP_CS3_OFFSET 0x0C | |
86 | #define IXP4XX_EXP_CS4_OFFSET 0x10 | |
87 | #define IXP4XX_EXP_CS5_OFFSET 0x14 | |
88 | #define IXP4XX_EXP_CS6_OFFSET 0x18 | |
89 | #define IXP4XX_EXP_CS7_OFFSET 0x1C | |
90 | #define IXP4XX_EXP_CFG0_OFFSET 0x20 | |
91 | #define IXP4XX_EXP_CFG1_OFFSET 0x24 | |
92 | #define IXP4XX_EXP_CFG2_OFFSET 0x28 | |
93 | #define IXP4XX_EXP_CFG3_OFFSET 0x2C | |
94 | ||
95 | /* | |
96 | * Expansion Bus Controller registers. | |
97 | */ | |
98 | #define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) | |
99 | ||
100 | #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) | |
101 | #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) | |
102 | #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) | |
103 | #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) | |
104 | #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) | |
105 | #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) | |
106 | #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) | |
107 | #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) | |
108 | ||
109 | #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) | |
110 | #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) | |
111 | #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) | |
112 | #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) | |
113 | ||
114 | ||
115 | /* | |
116 | * Peripheral Space Register Region Base Addresses | |
117 | */ | |
118 | #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) | |
119 | #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) | |
120 | #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) | |
121 | #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) | |
122 | #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) | |
123 | #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) | |
124 | #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) | |
125 | #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) | |
126 | #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) | |
127 | ||
128 | #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) | |
129 | #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) | |
130 | #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) | |
131 | #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) | |
132 | #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) | |
133 | #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) | |
134 | #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) | |
135 | #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) | |
136 | #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) | |
137 | ||
138 | /* | |
139 | * Constants to make it easy to access Interrupt Controller registers | |
140 | */ | |
141 | #define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */ | |
142 | #define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */ | |
143 | #define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ | |
144 | #define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */ | |
145 | #define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */ | |
146 | #define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */ | |
147 | #define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ | |
148 | #define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ | |
149 | ||
150 | /* | |
151 | * IXP465-only | |
152 | */ | |
153 | #define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */ | |
154 | #define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */ | |
155 | #define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */ | |
156 | #define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */ | |
157 | #define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */ | |
158 | #define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */ | |
159 | ||
160 | ||
161 | /* | |
162 | * Interrupt Controller Register Definitions. | |
163 | */ | |
164 | ||
165 | #define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x))) | |
166 | ||
167 | #define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET) | |
168 | #define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET) | |
169 | #define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET) | |
170 | #define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET) | |
171 | #define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET) | |
172 | #define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET) | |
173 | #define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) | |
174 | #define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET) | |
175 | #define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET) | |
176 | #define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET) | |
177 | #define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET) | |
178 | #define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET) | |
179 | #define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET) | |
180 | #define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET) | |
181 | ||
182 | /* | |
183 | * Constants to make it easy to access GPIO registers | |
184 | */ | |
185 | #define IXP4XX_GPIO_GPOUTR_OFFSET 0x00 | |
186 | #define IXP4XX_GPIO_GPOER_OFFSET 0x04 | |
187 | #define IXP4XX_GPIO_GPINR_OFFSET 0x08 | |
188 | #define IXP4XX_GPIO_GPISR_OFFSET 0x0C | |
189 | #define IXP4XX_GPIO_GPIT1R_OFFSET 0x10 | |
190 | #define IXP4XX_GPIO_GPIT2R_OFFSET 0x14 | |
191 | #define IXP4XX_GPIO_GPCLKR_OFFSET 0x18 | |
192 | #define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C | |
193 | ||
194 | /* | |
195 | * GPIO Register Definitions. | |
196 | * [Only perform 32bit reads/writes] | |
197 | */ | |
198 | #define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x))) | |
199 | ||
200 | #define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET) | |
201 | #define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET) | |
202 | #define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET) | |
203 | #define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET) | |
204 | #define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET) | |
205 | #define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET) | |
206 | #define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET) | |
207 | #define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET) | |
208 | ||
209 | /* | |
210 | * GPIO register bit definitions | |
211 | */ | |
212 | ||
213 | /* Interrupt styles | |
214 | */ | |
215 | #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0 | |
216 | #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1 | |
217 | #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2 | |
218 | #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3 | |
219 | #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4 | |
220 | ||
221 | /* | |
222 | * Mask used to clear interrupt styles | |
223 | */ | |
224 | #define IXP4XX_GPIO_STYLE_CLEAR 0x7 | |
225 | #define IXP4XX_GPIO_STYLE_SIZE 3 | |
226 | ||
227 | /* | |
228 | * Constants to make it easy to access Timer Control/Status registers | |
229 | */ | |
230 | #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ | |
231 | #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ | |
232 | #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ | |
233 | #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ | |
234 | #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ | |
235 | #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ | |
236 | #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ | |
237 | #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ | |
238 | #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ | |
239 | ||
240 | /* | |
241 | * Operating System Timer Register Definitions. | |
242 | */ | |
243 | ||
244 | #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) | |
245 | ||
246 | #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) | |
247 | #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) | |
248 | #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) | |
249 | #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) | |
250 | #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) | |
251 | #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) | |
252 | #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) | |
253 | #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) | |
254 | #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) | |
255 | ||
256 | /* | |
257 | * Timer register values and bit definitions | |
258 | */ | |
259 | #define IXP4XX_OST_ENABLE 0x00000001 | |
260 | #define IXP4XX_OST_ONE_SHOT 0x00000002 | |
261 | /* Low order bits of reload value ignored */ | |
262 | #define IXP4XX_OST_RELOAD_MASK 0x00000003 | |
263 | #define IXP4XX_OST_DISABLED 0x00000000 | |
264 | #define IXP4XX_OSST_TIMER_1_PEND 0x00000001 | |
265 | #define IXP4XX_OSST_TIMER_2_PEND 0x00000002 | |
266 | #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 | |
267 | #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 | |
268 | #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 | |
269 | ||
270 | #define IXP4XX_WDT_KEY 0x0000482E | |
271 | ||
272 | #define IXP4XX_WDT_RESET_ENABLE 0x00000001 | |
273 | #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 | |
274 | #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 | |
275 | ||
276 | ||
277 | /* | |
278 | * Constants to make it easy to access PCI Control/Status registers | |
279 | */ | |
280 | #define PCI_NP_AD_OFFSET 0x00 | |
281 | #define PCI_NP_CBE_OFFSET 0x04 | |
282 | #define PCI_NP_WDATA_OFFSET 0x08 | |
283 | #define PCI_NP_RDATA_OFFSET 0x0c | |
284 | #define PCI_CRP_AD_CBE_OFFSET 0x10 | |
285 | #define PCI_CRP_WDATA_OFFSET 0x14 | |
286 | #define PCI_CRP_RDATA_OFFSET 0x18 | |
287 | #define PCI_CSR_OFFSET 0x1c | |
288 | #define PCI_ISR_OFFSET 0x20 | |
289 | #define PCI_INTEN_OFFSET 0x24 | |
290 | #define PCI_DMACTRL_OFFSET 0x28 | |
291 | #define PCI_AHBMEMBASE_OFFSET 0x2c | |
292 | #define PCI_AHBIOBASE_OFFSET 0x30 | |
293 | #define PCI_PCIMEMBASE_OFFSET 0x34 | |
294 | #define PCI_AHBDOORBELL_OFFSET 0x38 | |
295 | #define PCI_PCIDOORBELL_OFFSET 0x3C | |
296 | #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 | |
297 | #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 | |
298 | #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 | |
299 | #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C | |
300 | #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 | |
301 | #define PCI_ATPDMA1_LENADDR_OFFSET 0x54 | |
302 | ||
303 | /* | |
304 | * PCI Control/Status Registers | |
305 | */ | |
306 | #define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) | |
307 | ||
308 | #define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) | |
309 | #define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) | |
310 | #define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) | |
311 | #define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) | |
312 | #define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) | |
313 | #define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) | |
314 | #define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) | |
315 | #define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET) | |
316 | #define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET) | |
317 | #define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) | |
318 | #define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) | |
319 | #define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) | |
320 | #define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) | |
321 | #define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) | |
322 | #define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) | |
323 | #define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) | |
324 | #define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) | |
325 | #define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) | |
326 | #define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) | |
327 | #define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) | |
328 | #define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) | |
329 | #define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) | |
330 | ||
331 | /* | |
332 | * PCI register values and bit definitions | |
333 | */ | |
334 | ||
335 | /* CSR bit definitions */ | |
336 | #define PCI_CSR_HOST 0x00000001 | |
337 | #define PCI_CSR_ARBEN 0x00000002 | |
338 | #define PCI_CSR_ADS 0x00000004 | |
339 | #define PCI_CSR_PDS 0x00000008 | |
340 | #define PCI_CSR_ABE 0x00000010 | |
341 | #define PCI_CSR_DBT 0x00000020 | |
342 | #define PCI_CSR_ASE 0x00000100 | |
343 | #define PCI_CSR_IC 0x00008000 | |
344 | ||
345 | /* ISR (Interrupt status) Register bit definitions */ | |
346 | #define PCI_ISR_PSE 0x00000001 | |
347 | #define PCI_ISR_PFE 0x00000002 | |
348 | #define PCI_ISR_PPE 0x00000004 | |
349 | #define PCI_ISR_AHBE 0x00000008 | |
350 | #define PCI_ISR_APDC 0x00000010 | |
351 | #define PCI_ISR_PADC 0x00000020 | |
352 | #define PCI_ISR_ADB 0x00000040 | |
353 | #define PCI_ISR_PDB 0x00000080 | |
354 | ||
355 | /* INTEN (Interrupt Enable) Register bit definitions */ | |
356 | #define PCI_INTEN_PSE 0x00000001 | |
357 | #define PCI_INTEN_PFE 0x00000002 | |
358 | #define PCI_INTEN_PPE 0x00000004 | |
359 | #define PCI_INTEN_AHBE 0x00000008 | |
360 | #define PCI_INTEN_APDC 0x00000010 | |
361 | #define PCI_INTEN_PADC 0x00000020 | |
362 | #define PCI_INTEN_ADB 0x00000040 | |
363 | #define PCI_INTEN_PDB 0x00000080 | |
364 | ||
365 | /* | |
366 | * Shift value for byte enable on NP cmd/byte enable register | |
367 | */ | |
368 | #define IXP4XX_PCI_NP_CBE_BESL 4 | |
369 | ||
370 | /* | |
371 | * PCI commands supported by NP access unit | |
372 | */ | |
373 | #define NP_CMD_IOREAD 0x2 | |
374 | #define NP_CMD_IOWRITE 0x3 | |
375 | #define NP_CMD_CONFIGREAD 0xa | |
376 | #define NP_CMD_CONFIGWRITE 0xb | |
377 | #define NP_CMD_MEMREAD 0x6 | |
378 | #define NP_CMD_MEMWRITE 0x7 | |
379 | ||
380 | /* | |
381 | * Constants for CRP access into local config space | |
382 | */ | |
383 | #define CRP_AD_CBE_BESL 20 | |
384 | #define CRP_AD_CBE_WRITE 0x00010000 | |
385 | ||
386 | ||
387 | /* | |
388 | * USB Device Controller | |
389 | * | |
390 | * These are used by the USB gadget driver, so they don't follow the | |
391 | * IXP4XX_ naming convetions. | |
392 | * | |
393 | */ | |
394 | # define IXP4XX_USB_REG(x) (*((volatile u32 *)(x))) | |
395 | ||
396 | /* UDC Undocumented - Reserved1 */ | |
397 | #define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004) | |
398 | /* UDC Undocumented - Reserved2 */ | |
399 | #define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008) | |
400 | /* UDC Undocumented - Reserved3 */ | |
401 | #define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C) | |
402 | /* UDC Control Register */ | |
403 | #define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000) | |
404 | /* UDC Endpoint 0 Control/Status Register */ | |
405 | #define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010) | |
406 | /* UDC Endpoint 1 (IN) Control/Status Register */ | |
407 | #define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014) | |
408 | /* UDC Endpoint 2 (OUT) Control/Status Register */ | |
409 | #define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018) | |
410 | /* UDC Endpoint 3 (IN) Control/Status Register */ | |
411 | #define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C) | |
412 | /* UDC Endpoint 4 (OUT) Control/Status Register */ | |
413 | #define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020) | |
414 | /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | |
415 | #define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024) | |
416 | /* UDC Endpoint 6 (IN) Control/Status Register */ | |
417 | #define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028) | |
418 | /* UDC Endpoint 7 (OUT) Control/Status Register */ | |
419 | #define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C) | |
420 | /* UDC Endpoint 8 (IN) Control/Status Register */ | |
421 | #define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030) | |
422 | /* UDC Endpoint 9 (OUT) Control/Status Register */ | |
423 | #define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034) | |
424 | /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | |
425 | #define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038) | |
426 | /* UDC Endpoint 11 (IN) Control/Status Register */ | |
427 | #define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C) | |
428 | /* UDC Endpoint 12 (OUT) Control/Status Register */ | |
429 | #define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040) | |
430 | /* UDC Endpoint 13 (IN) Control/Status Register */ | |
431 | #define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044) | |
432 | /* UDC Endpoint 14 (OUT) Control/Status Register */ | |
433 | #define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048) | |
434 | /* UDC Endpoint 15 (Interrupt) Control/Status Register */ | |
435 | #define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C) | |
436 | /* UDC Frame Number Register High */ | |
437 | #define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060) | |
438 | /* UDC Frame Number Register Low */ | |
439 | #define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064) | |
440 | /* UDC Byte Count Reg 2 */ | |
441 | #define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068) | |
442 | /* UDC Byte Count Reg 4 */ | |
443 | #define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c) | |
444 | /* UDC Byte Count Reg 7 */ | |
445 | #define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070) | |
446 | /* UDC Byte Count Reg 9 */ | |
447 | #define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074) | |
448 | /* UDC Byte Count Reg 12 */ | |
449 | #define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078) | |
450 | /* UDC Byte Count Reg 14 */ | |
451 | #define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c) | |
452 | /* UDC Endpoint 0 Data Register */ | |
453 | #define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080) | |
454 | /* UDC Endpoint 1 Data Register */ | |
455 | #define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100) | |
456 | /* UDC Endpoint 2 Data Register */ | |
457 | #define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180) | |
458 | /* UDC Endpoint 3 Data Register */ | |
459 | #define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200) | |
460 | /* UDC Endpoint 4 Data Register */ | |
461 | #define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400) | |
462 | /* UDC Endpoint 5 Data Register */ | |
463 | #define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0) | |
464 | /* UDC Endpoint 6 Data Register */ | |
465 | #define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600) | |
466 | /* UDC Endpoint 7 Data Register */ | |
467 | #define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680) | |
468 | /* UDC Endpoint 8 Data Register */ | |
469 | #define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700) | |
470 | /* UDC Endpoint 9 Data Register */ | |
471 | #define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900) | |
472 | /* UDC Endpoint 10 Data Register */ | |
473 | #define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0) | |
474 | /* UDC Endpoint 11 Data Register */ | |
475 | #define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00) | |
476 | /* UDC Endpoint 12 Data Register */ | |
477 | #define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80) | |
478 | /* UDC Endpoint 13 Data Register */ | |
479 | #define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00) | |
480 | /* UDC Endpoint 14 Data Register */ | |
481 | #define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00) | |
482 | /* UDC Endpoint 15 Data Register */ | |
483 | #define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0) | |
484 | /* UDC Interrupt Control Register 0 */ | |
485 | #define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050) | |
486 | /* UDC Interrupt Control Register 1 */ | |
487 | #define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054) | |
488 | /* UDC Status Interrupt Register 0 */ | |
489 | #define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058) | |
490 | /* UDC Status Interrupt Register 1 */ | |
491 | #define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C) | |
492 | ||
493 | #define UDCCR_UDE (1 << 0) /* UDC enable */ | |
494 | #define UDCCR_UDA (1 << 1) /* UDC active */ | |
495 | #define UDCCR_RSM (1 << 2) /* Device resume */ | |
496 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ | |
497 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ | |
498 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ | |
499 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ | |
500 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ | |
501 | ||
502 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ | |
503 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ | |
504 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ | |
505 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ | |
506 | #define UDCCS0_SST (1 << 4) /* Sent stall */ | |
507 | #define UDCCS0_FST (1 << 5) /* Force stall */ | |
508 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ | |
509 | #define UDCCS0_SA (1 << 7) /* Setup active */ | |
510 | ||
511 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ | |
512 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ | |
513 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ | |
514 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ | |
515 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ | |
516 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ | |
517 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ | |
518 | ||
519 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ | |
520 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ | |
521 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ | |
522 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ | |
523 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ | |
524 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ | |
525 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ | |
526 | ||
527 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ | |
528 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ | |
529 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ | |
530 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ | |
531 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ | |
532 | ||
533 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | |
534 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | |
535 | #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ | |
536 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ | |
537 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | |
538 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | |
539 | ||
540 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ | |
541 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ | |
542 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ | |
543 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ | |
544 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ | |
545 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ | |
546 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ | |
547 | ||
548 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ | |
549 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ | |
550 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ | |
551 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ | |
552 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ | |
553 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ | |
554 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ | |
555 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ | |
556 | ||
557 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ | |
558 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ | |
559 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ | |
560 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ | |
561 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ | |
562 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ | |
563 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | |
564 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | |
565 | ||
566 | #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ | |
567 | #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ | |
568 | #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ | |
569 | #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ | |
570 | #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ | |
571 | #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ | |
572 | #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ | |
573 | #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ | |
574 | ||
575 | #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ | |
576 | #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ | |
577 | #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ | |
578 | #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ | |
579 | #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ | |
580 | #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ | |
581 | #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ | |
582 | #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ | |
583 | ||
584 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | |
585 | ||
586 | #ifndef __ASSEMBLY__ | |
587 | static inline int cpu_is_ixp46x(void) | |
588 | { | |
589 | #ifdef CONFIG_CPU_IXP46X | |
590 | unsigned int processor_id; | |
591 | ||
592 | asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :); | |
593 | ||
594 | if ((processor_id & 0xffffff00) == 0x69054200) | |
595 | return 1; | |
596 | #endif | |
597 | return 0; | |
598 | } | |
599 | #endif | |
600 | ||
601 | #endif |