[deliverable/linux.git] / include / asm-arm / arch-omap / dma.h

/*
 *  linux/include/asm-arm/arch-omap/dma.h
 *
 *  Copyright (C) 2003 Nokia Corporation
 *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H

/* Hardware registers for omap1 */
#define OMAP_DMA_BASE			(0xfffed800)
#define OMAP_DMA_GCR			(OMAP_DMA_BASE + 0x400)
#define OMAP_DMA_GSCR			(OMAP_DMA_BASE + 0x404)
#define OMAP_DMA_GRST			(OMAP_DMA_BASE + 0x408)
#define OMAP_DMA_HW_ID			(OMAP_DMA_BASE + 0x442)
#define OMAP_DMA_PCH2_ID		(OMAP_DMA_BASE + 0x444)
#define OMAP_DMA_PCH0_ID		(OMAP_DMA_BASE + 0x446)
#define OMAP_DMA_PCH1_ID		(OMAP_DMA_BASE + 0x448)
#define OMAP_DMA_PCHG_ID		(OMAP_DMA_BASE + 0x44a)
#define OMAP_DMA_PCHD_ID		(OMAP_DMA_BASE + 0x44c)
#define OMAP_DMA_CAPS_0_U		(OMAP_DMA_BASE + 0x44e)
#define OMAP_DMA_CAPS_0_L		(OMAP_DMA_BASE + 0x450)
#define OMAP_DMA_CAPS_1_U		(OMAP_DMA_BASE + 0x452)
#define OMAP_DMA_CAPS_1_L		(OMAP_DMA_BASE + 0x454)
#define OMAP_DMA_CAPS_2			(OMAP_DMA_BASE + 0x456)
#define OMAP_DMA_CAPS_3			(OMAP_DMA_BASE + 0x458)
#define OMAP_DMA_CAPS_4			(OMAP_DMA_BASE + 0x45a)
#define OMAP_DMA_PCH2_SR		(OMAP_DMA_BASE + 0x460)
#define OMAP_DMA_PCH0_SR		(OMAP_DMA_BASE + 0x480)
#define OMAP_DMA_PCH1_SR		(OMAP_DMA_BASE + 0x482)
#define OMAP_DMA_PCHD_SR		(OMAP_DMA_BASE + 0x4c0)

/* Hardware registers for omap2 */
#define OMAP24XX_DMA_BASE		(L4_24XX_BASE + 0x56000)
#define OMAP_DMA4_REVISION		(OMAP24XX_DMA_BASE + 0x00)
#define OMAP_DMA4_GCR_REG		(OMAP24XX_DMA_BASE + 0x78)
#define OMAP_DMA4_IRQSTATUS_L0		(OMAP24XX_DMA_BASE + 0x08)
#define OMAP_DMA4_IRQSTATUS_L1		(OMAP24XX_DMA_BASE + 0x0c)
#define OMAP_DMA4_IRQSTATUS_L2		(OMAP24XX_DMA_BASE + 0x10)
#define OMAP_DMA4_IRQSTATUS_L3		(OMAP24XX_DMA_BASE + 0x14)
#define OMAP_DMA4_IRQENABLE_L0		(OMAP24XX_DMA_BASE + 0x18)
#define OMAP_DMA4_IRQENABLE_L1		(OMAP24XX_DMA_BASE + 0x1c)
#define OMAP_DMA4_IRQENABLE_L2		(OMAP24XX_DMA_BASE + 0x20)
#define OMAP_DMA4_IRQENABLE_L3		(OMAP24XX_DMA_BASE + 0x24)
#define OMAP_DMA4_SYSSTATUS		(OMAP24XX_DMA_BASE + 0x28)
#define OMAP_DMA4_CAPS_0		(OMAP24XX_DMA_BASE + 0x64)
#define OMAP_DMA4_CAPS_2		(OMAP24XX_DMA_BASE + 0x6c)
#define OMAP_DMA4_CAPS_3		(OMAP24XX_DMA_BASE + 0x70)
#define OMAP_DMA4_CAPS_4		(OMAP24XX_DMA_BASE + 0x74)

#ifdef CONFIG_ARCH_OMAP1

#define OMAP_LOGICAL_DMA_CH_COUNT	17

/* Common channel specific registers for omap1 */
#define OMAP_DMA_CSDP_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
#define OMAP_DMA_CCR_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
#define OMAP_DMA_CICR_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
#define OMAP_DMA_CSR_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
#define OMAP_DMA_CEN_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
#define OMAP_DMA_CFN_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
#define OMAP_DMA_CSFI_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
#define OMAP_DMA_CSEI_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
#define OMAP_DMA_CSAC_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
#define OMAP_DMA_CDAC_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
#define OMAP_DMA_CDEI_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
#define OMAP_DMA_CDFI_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
#define OMAP_DMA_CLNK_CTRL_REG(n)	__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)

#else

#define OMAP_LOGICAL_DMA_CH_COUNT	32	/* REVISIT: Is this 32 + 2? */

/* Common channel specific registers for omap2 */
#define OMAP_DMA_CCR_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
#define OMAP_DMA_CLNK_CTRL_REG(n)	__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
#define OMAP_DMA_CICR_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
#define OMAP_DMA_CSR_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
#define OMAP_DMA_CSDP_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
#define OMAP_DMA_CEN_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
#define OMAP_DMA_CFN_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
#define OMAP_DMA_CSEI_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
#define OMAP_DMA_CSFI_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
#define OMAP_DMA_CDEI_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
#define OMAP_DMA_CDFI_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
#define OMAP_DMA_CSAC_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
#define OMAP_DMA_CDAC_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)

#endif

/* Channel specific registers only on omap1 */
#define OMAP1_DMA_CSSA_L_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
#define OMAP1_DMA_CSSA_U_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
#define OMAP1_DMA_CDSA_L_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
#define OMAP1_DMA_CDSA_U_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
#define OMAP1_DMA_COLOR_L_REG(n)	__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
#define OMAP1_DMA_CCR2_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
#define OMAP1_DMA_COLOR_U_REG(n)	__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
#define OMAP1_DMA_LCH_CTRL_REG(n)	__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)

/* Channel specific registers only on omap2 */
#define OMAP2_DMA_CSSA_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
#define OMAP2_DMA_CDSA_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
#define OMAP2_DMA_CCEN_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
#define OMAP2_DMA_CCFN_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
#define OMAP2_DMA_COLOR_REG(n)		__REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)

/*----------------------------------------------------------------------------*/

/* DMA channels for omap1 */
#define OMAP_DMA_NO_DEVICE		0
#define OMAP_DMA_MCSI1_TX		1
#define OMAP_DMA_MCSI1_RX		2
#define OMAP_DMA_I2C_RX			3
#define OMAP_DMA_I2C_TX			4
#define OMAP_DMA_EXT_NDMA_REQ		5
#define OMAP_DMA_EXT_NDMA_REQ2		6
#define OMAP_DMA_UWIRE_TX		7
#define OMAP_DMA_MCBSP1_TX		8
#define OMAP_DMA_MCBSP1_RX		9
#define OMAP_DMA_MCBSP3_TX		10
#define OMAP_DMA_MCBSP3_RX		11
#define OMAP_DMA_UART1_TX		12
#define OMAP_DMA_UART1_RX		13
#define OMAP_DMA_UART2_TX		14
#define OMAP_DMA_UART2_RX		15
#define OMAP_DMA_MCBSP2_TX		16
#define OMAP_DMA_MCBSP2_RX		17
#define OMAP_DMA_UART3_TX		18
#define OMAP_DMA_UART3_RX		19
#define OMAP_DMA_CAMERA_IF_RX		20
#define OMAP_DMA_MMC_TX			21
#define OMAP_DMA_MMC_RX			22
#define OMAP_DMA_NAND			23
#define OMAP_DMA_IRQ_LCD_LINE		24
#define OMAP_DMA_MEMORY_STICK		25
#define OMAP_DMA_USB_W2FC_RX0		26
#define OMAP_DMA_USB_W2FC_RX1		27
#define OMAP_DMA_USB_W2FC_RX2		28
#define OMAP_DMA_USB_W2FC_TX0		29
#define OMAP_DMA_USB_W2FC_TX1		30
#define OMAP_DMA_USB_W2FC_TX2		31

/* These are only for 1610 */
#define OMAP_DMA_CRYPTO_DES_IN		32
#define OMAP_DMA_SPI_TX			33
#define OMAP_DMA_SPI_RX			34
#define OMAP_DMA_CRYPTO_HASH		35
#define OMAP_DMA_CCP_ATTN		36
#define OMAP_DMA_CCP_FIFO_NOT_EMPTY	37
#define OMAP_DMA_CMT_APE_TX_CHAN_0	38
#define OMAP_DMA_CMT_APE_RV_CHAN_0	39
#define OMAP_DMA_CMT_APE_TX_CHAN_1	40
#define OMAP_DMA_CMT_APE_RV_CHAN_1	41
#define OMAP_DMA_CMT_APE_TX_CHAN_2	42
#define OMAP_DMA_CMT_APE_RV_CHAN_2	43
#define OMAP_DMA_CMT_APE_TX_CHAN_3	44
#define OMAP_DMA_CMT_APE_RV_CHAN_3	45
#define OMAP_DMA_CMT_APE_TX_CHAN_4	46
#define OMAP_DMA_CMT_APE_RV_CHAN_4	47
#define OMAP_DMA_CMT_APE_TX_CHAN_5	48
#define OMAP_DMA_CMT_APE_RV_CHAN_5	49
#define OMAP_DMA_CMT_APE_TX_CHAN_6	50
#define OMAP_DMA_CMT_APE_RV_CHAN_6	51
#define OMAP_DMA_CMT_APE_TX_CHAN_7	52
#define OMAP_DMA_CMT_APE_RV_CHAN_7	53
#define OMAP_DMA_MMC2_TX		54
#define OMAP_DMA_MMC2_RX		55
#define OMAP_DMA_CRYPTO_DES_OUT		56

/* DMA channels for 24xx */
#define OMAP24XX_DMA_NO_DEVICE		0
#define OMAP24XX_DMA_XTI_DMA		1	/* S_DMA_0 */
#define OMAP24XX_DMA_EXT_DMAREQ0	2	/* S_DMA_1 */
#define OMAP24XX_DMA_EXT_DMAREQ1	3	/* S_DMA_2 */
#define OMAP24XX_DMA_GPMC		4	/* S_DMA_3 */
#define OMAP24XX_DMA_GFX		5	/* S_DMA_4 */
#define OMAP24XX_DMA_DSS		6	/* S_DMA_5 */
#define OMAP24XX_DMA_VLYNQ_TX		7	/* S_DMA_6 */
#define OMAP24XX_DMA_CWT		8	/* S_DMA_7 */
#define OMAP24XX_DMA_AES_TX		9	/* S_DMA_8 */
#define OMAP24XX_DMA_AES_RX		10	/* S_DMA_9 */
#define OMAP24XX_DMA_DES_TX		11	/* S_DMA_10 */
#define OMAP24XX_DMA_DES_RX		12	/* S_DMA_11 */
#define OMAP24XX_DMA_SHA1MD5_RX		13	/* S_DMA_12 */
#define OMAP24XX_DMA_EXT_DMAREQ2	14	/* S_DMA_13 */
#define OMAP24XX_DMA_EXT_DMAREQ3	15	/* S_DMA_14 */
#define OMAP24XX_DMA_EXT_DMAREQ4	16	/* S_DMA_15 */
#define OMAP24XX_DMA_EAC_AC_RD		17	/* S_DMA_16 */
#define OMAP24XX_DMA_EAC_AC_WR		18	/* S_DMA_17 */
#define OMAP24XX_DMA_EAC_MD_UL_RD	19	/* S_DMA_18 */
#define OMAP24XX_DMA_EAC_MD_UL_WR	20	/* S_DMA_19 */
#define OMAP24XX_DMA_EAC_MD_DL_RD	21	/* S_DMA_20 */
#define OMAP24XX_DMA_EAC_MD_DL_WR	22	/* S_DMA_21 */
#define OMAP24XX_DMA_EAC_BT_UL_RD	23	/* S_DMA_22 */
#define OMAP24XX_DMA_EAC_BT_UL_WR	24	/* S_DMA_23 */
#define OMAP24XX_DMA_EAC_BT_DL_RD	25	/* S_DMA_24 */
#define OMAP24XX_DMA_EAC_BT_DL_WR	26	/* S_DMA_25 */
#define OMAP24XX_DMA_I2C1_TX		27	/* S_DMA_26 */
#define OMAP24XX_DMA_I2C1_RX		28	/* S_DMA_27 */
#define OMAP24XX_DMA_I2C2_TX		29	/* S_DMA_28 */
#define OMAP24XX_DMA_I2C2_RX		30	/* S_DMA_29 */
#define OMAP24XX_DMA_MCBSP1_TX		31	/* SDMA_30 */
#define OMAP24XX_DMA_MCBSP1_RX		32	/* SDMA_31 */
#define OMAP24XX_DMA_MCBSP2_TX		33	/* SDMA_32 */
#define OMAP24XX_DMA_MCBSP2_RX		34	/* SDMA_33 */
#define OMAP24XX_DMA_SPI1_TX0		35	/* SDMA_34 */
#define OMAP24XX_DMA_SPI1_RX0		36	/* SDMA_35 */
#define OMAP24XX_DMA_SPI1_TX1		37	/* SDMA_36 */
#define OMAP24XX_DMA_SPI1_RX1		38	/* SDMA_37 */
#define OMAP24XX_DMA_SPI1_TX2		39	/* SDMA_38 */
#define OMAP24XX_DMA_SPI1_RX2		40	/* SDMA_39 */
#define OMAP24XX_DMA_SPI1_TX3		41	/* SDMA_40 */
#define OMAP24XX_DMA_SPI1_RX3		42	/* SDMA_41 */
#define OMAP24XX_DMA_SPI2_TX0		43	/* SDMA_42 */
#define OMAP24XX_DMA_SPI2_RX0		44	/* SDMA_43 */
#define OMAP24XX_DMA_SPI2_TX1		45	/* SDMA_44 */
#define OMAP24XX_DMA_SPI2_RX1		46	/* SDMA_45 */

#define OMAP24XX_DMA_UART1_TX		49	/* SDMA_48 */
#define OMAP24XX_DMA_UART1_RX		50	/* SDMA_49 */
#define OMAP24XX_DMA_UART2_TX		51	/* SDMA_50 */
#define OMAP24XX_DMA_UART2_RX		52	/* SDMA_51 */
#define OMAP24XX_DMA_UART3_TX		53	/* SDMA_52 */
#define OMAP24XX_DMA_UART3_RX		54	/* SDMA_53 */
#define OMAP24XX_DMA_USB_W2FC_TX0	55	/* SDMA_54 */
#define OMAP24XX_DMA_USB_W2FC_RX0	56	/* SDMA_55 */
#define OMAP24XX_DMA_USB_W2FC_TX1	57	/* SDMA_56 */
#define OMAP24XX_DMA_USB_W2FC_RX1	58	/* SDMA_57 */
#define OMAP24XX_DMA_USB_W2FC_TX2	59	/* SDMA_58 */
#define OMAP24XX_DMA_USB_W2FC_RX2	60	/* SDMA_59 */
#define OMAP24XX_DMA_MMC1_TX		61	/* SDMA_60 */
#define OMAP24XX_DMA_MMC1_RX		62	/* SDMA_61 */
#define OMAP24XX_DMA_MS			63	/* SDMA_62 */
#define OMAP24XX_DMA_EXT_DMAREQ5	64	/* S_DMA_63 */

/*----------------------------------------------------------------------------*/

/* Hardware registers for LCD DMA */
#define OMAP1510_DMA_LCD_BASE		(0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL		(OMAP1510_DMA_LCD_BASE + 0x00)
#define OMAP1510_DMA_LCD_TOP_F1_L	(OMAP1510_DMA_LCD_BASE + 0x02)
#define OMAP1510_DMA_LCD_TOP_F1_U	(OMAP1510_DMA_LCD_BASE + 0x04)
#define OMAP1510_DMA_LCD_BOT_F1_L	(OMAP1510_DMA_LCD_BASE + 0x06)
#define OMAP1510_DMA_LCD_BOT_F1_U	(OMAP1510_DMA_LCD_BASE + 0x08)

#define OMAP1610_DMA_LCD_BASE		(0xfffee300)
#define OMAP1610_DMA_LCD_CSDP		(OMAP1610_DMA_LCD_BASE + 0xc0)
#define OMAP1610_DMA_LCD_CCR		(OMAP1610_DMA_LCD_BASE + 0xc2)
#define OMAP1610_DMA_LCD_CTRL		(OMAP1610_DMA_LCD_BASE + 0xc4)
#define OMAP1610_DMA_LCD_TOP_B1_L	(OMAP1610_DMA_LCD_BASE + 0xc8)
#define OMAP1610_DMA_LCD_TOP_B1_U	(OMAP1610_DMA_LCD_BASE + 0xca)
#define OMAP1610_DMA_LCD_BOT_B1_L	(OMAP1610_DMA_LCD_BASE + 0xcc)
#define OMAP1610_DMA_LCD_BOT_B1_U	(OMAP1610_DMA_LCD_BASE + 0xce)
#define OMAP1610_DMA_LCD_TOP_B2_L	(OMAP1610_DMA_LCD_BASE + 0xd0)
#define OMAP1610_DMA_LCD_TOP_B2_U	(OMAP1610_DMA_LCD_BASE + 0xd2)
#define OMAP1610_DMA_LCD_BOT_B2_L	(OMAP1610_DMA_LCD_BASE + 0xd4)
#define OMAP1610_DMA_LCD_BOT_B2_U	(OMAP1610_DMA_LCD_BASE + 0xd6)
#define OMAP1610_DMA_LCD_SRC_EI_B1	(OMAP1610_DMA_LCD_BASE + 0xd8)
#define OMAP1610_DMA_LCD_SRC_FI_B1_L	(OMAP1610_DMA_LCD_BASE + 0xda)
#define OMAP1610_DMA_LCD_SRC_EN_B1	(OMAP1610_DMA_LCD_BASE + 0xe0)
#define OMAP1610_DMA_LCD_SRC_FN_B1	(OMAP1610_DMA_LCD_BASE + 0xe4)
#define OMAP1610_DMA_LCD_LCH_CTRL	(OMAP1610_DMA_LCD_BASE + 0xea)
#define OMAP1610_DMA_LCD_SRC_FI_B1_U	(OMAP1610_DMA_LCD_BASE + 0xf4)

#define OMAP1_DMA_TOUT_IRQ		(1 << 0)
#define OMAP_DMA_DROP_IRQ		(1 << 1)
#define OMAP_DMA_HALF_IRQ		(1 << 2)
#define OMAP_DMA_FRAME_IRQ		(1 << 3)
#define OMAP_DMA_LAST_IRQ		(1 << 4)
#define OMAP_DMA_BLOCK_IRQ		(1 << 5)
#define OMAP1_DMA_SYNC_IRQ		(1 << 6)
#define OMAP2_DMA_PKT_IRQ		(1 << 7)
#define OMAP2_DMA_TRANS_ERR_IRQ		(1 << 8)
#define OMAP2_DMA_SECURE_ERR_IRQ	(1 << 9)
#define OMAP2_DMA_SUPERVISOR_ERR_IRQ	(1 << 10)
#define OMAP2_DMA_MISALIGNED_ERR_IRQ	(1 << 11)

#define OMAP_DMA_DATA_TYPE_S8		0x00
#define OMAP_DMA_DATA_TYPE_S16		0x01
#define OMAP_DMA_DATA_TYPE_S32		0x02

#define OMAP_DMA_SYNC_ELEMENT		0x00
#define OMAP_DMA_SYNC_FRAME		0x01
#define OMAP_DMA_SYNC_BLOCK		0x02

#define OMAP_DMA_PORT_EMIFF		0x00
#define OMAP_DMA_PORT_EMIFS		0x01
#define OMAP_DMA_PORT_OCP_T1		0x02
#define OMAP_DMA_PORT_TIPB		0x03
#define OMAP_DMA_PORT_OCP_T2		0x04
#define OMAP_DMA_PORT_MPUI		0x05

#define OMAP_DMA_AMODE_CONSTANT		0x00
#define OMAP_DMA_AMODE_POST_INC		0x01
#define OMAP_DMA_AMODE_SINGLE_IDX	0x02
#define OMAP_DMA_AMODE_DOUBLE_IDX	0x03

/* LCD DMA block numbers */
enum {
	OMAP_LCD_DMA_B1_TOP,
	OMAP_LCD_DMA_B1_BOTTOM,
	OMAP_LCD_DMA_B2_TOP,
	OMAP_LCD_DMA_B2_BOTTOM
};

enum omap_dma_burst_mode {
	OMAP_DMA_DATA_BURST_DIS = 0,
	OMAP_DMA_DATA_BURST_4,
	OMAP_DMA_DATA_BURST_8,
	OMAP_DMA_DATA_BURST_16,
};

enum omap_dma_color_mode {
	OMAP_DMA_COLOR_DIS = 0,
	OMAP_DMA_CONSTANT_FILL,
	OMAP_DMA_TRANSPARENT_COPY
};

enum omap_dma_write_mode {
	OMAP_DMA_WRITE_NON_POSTED = 0,
	OMAP_DMA_WRITE_POSTED,
	OMAP_DMA_WRITE_LAST_NON_POSTED
};

struct omap_dma_channel_params {
	int data_type;		/* data type 8,16,32 */
	int elem_count;		/* number of elements in a frame */
	int frame_count;	/* number of frames in a element */

	int src_port;		/* Only on OMAP1 REVISIT: Is this needed? */
	int src_amode;		/* constant , post increment, indexed , double indexed */
	unsigned long src_start;	/* source address : physical */
	int src_ei;		/* source element index */
	int src_fi;		/* source frame index */

	int dst_port;		/* Only on OMAP1 REVISIT: Is this needed? */
	int dst_amode;		/* constant , post increment, indexed , double indexed */
	unsigned long dst_start;	/* source address : physical */
	int dst_ei;		/* source element index */
	int dst_fi;		/* source frame index */

	int trigger;		/* trigger attached if the channel is synchronized */
	int sync_mode;		/* sycn on element, frame , block or packet */
	int src_or_dst_synch;	/* source synch(1) or destination synch(0) */

	int ie;			/* interrupt enabled */
};


extern void omap_set_dma_priority(int lch, int dst_port, int priority);
extern int omap_request_dma(int dev_id, const char *dev_name,
			    void (* callback)(int lch, u16 ch_status, void *data),
			    void *data, int *dma_ch);
extern void omap_enable_dma_irq(int ch, u16 irq_bits);
extern void omap_disable_dma_irq(int ch, u16 irq_bits);
extern void omap_free_dma(int ch);
extern void omap_start_dma(int lch);
extern void omap_stop_dma(int lch);
extern void omap_set_dma_transfer_params(int lch, int data_type,
					 int elem_count, int frame_count,
					 int sync_mode,
					 int dma_trigger, int src_or_dst_synch);
extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
				    u32 color);
extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);

extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
				    unsigned long src_start,
				    int src_ei, int src_fi);
extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
extern void omap_set_dma_src_data_pack(int lch, int enable);
extern void omap_set_dma_src_burst_mode(int lch,
					enum omap_dma_burst_mode burst_mode);

extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
				     unsigned long dest_start,
				     int dst_ei, int dst_fi);
extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
extern void omap_set_dma_dest_data_pack(int lch, int enable);
extern void omap_set_dma_dest_burst_mode(int lch,
					 enum omap_dma_burst_mode burst_mode);

extern void omap_set_dma_params(int lch,
				struct omap_dma_channel_params * params);

extern void omap_dma_link_lch (int lch_head, int lch_queue);
extern void omap_dma_unlink_lch (int lch_head, int lch_queue);

extern int omap_set_dma_callback(int lch,
			void (* callback)(int lch, u16 ch_status, void *data),
			void *data);
extern dma_addr_t omap_get_dma_src_pos(int lch);
extern dma_addr_t omap_get_dma_dst_pos(int lch);
extern int omap_get_dma_src_addr_counter(int lch);
extern void omap_clear_dma(int lch);
extern int omap_dma_running(void);

/* LCD DMA functions */
extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
				void *data);
extern void omap_free_lcd_dma(void);
extern void omap_setup_lcd_dma(void);
extern void omap_enable_lcd_dma(void);
extern void omap_stop_lcd_dma(void);
extern int  omap_lcd_dma_ext_running(void);
extern void omap_set_lcd_dma_ext_controller(int external);
extern void omap_set_lcd_dma_single_transfer(int single);
extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
				int data_type);
extern void omap_set_lcd_dma_b1_rotation(int rotate);
extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
extern void omap_set_lcd_dma_b1_mirror(int mirror);
extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);

#endif /* __ASM_ARCH_DMA_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-arm/arch-omap/dma.h
	3	*
	4	* Copyright (C) 2003 Nokia Corporation
121e70b6	5	* Author: Juha Yrjölä <juha.yrjola@nokia.com>
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#ifndef __ASM_ARCH_DMA_H
	22	#define __ASM_ARCH_DMA_H
	23
9ad5897c TL	24	/* Hardware registers for omap1 */
	25	#define OMAP_DMA_BASE (0xfffed800)
	26	#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
	27	#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
	28	#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
	29	#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
	30	#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
	31	#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
	32	#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
	33	#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
	34	#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
	35	#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
	36	#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
	37	#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
	38	#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
	39	#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
	40	#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
	41	#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
	42	#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
	43	#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
	44	#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
	45	#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
	46
	47	/* Hardware registers for omap2 */
	48	#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000)
	49	#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00)
	50	#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78)
	51	#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08)
	52	#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c)
	53	#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10)
	54	#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14)
	55	#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18)
	56	#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c)
	57	#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20)
	58	#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24)
	59	#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28)
	60	#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64)
	61	#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
	62	#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
	63	#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
	64
	65	#ifdef CONFIG_ARCH_OMAP1
1da177e4 LT	66
	67	#define OMAP_LOGICAL_DMA_CH_COUNT 17
	68
9ad5897c TL	69	/* Common channel specific registers for omap1 */
	70	#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
	71	#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
	72	#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
	73	#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
	74	#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
	75	#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
	76	#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
	77	#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
	78	#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
	79	#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
	80	#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
	81	#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
	82	#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
	83
	84	#else
	85
	86	#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
	87
	88	/* Common channel specific registers for omap2 */
	89	#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
	90	#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
	91	#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
	92	#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
	93	#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
	94	#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
	95	#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
	96	#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
	97	#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
	98	#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
	99	#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
	100	#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
	101	#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
	102
	103	#endif
	104
	105	/* Channel specific registers only on omap1 */
	106	#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
	107	#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
	108	#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
	109	#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
	110	#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
	111	#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
	112	#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
	113	#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
	114
	115	/* Channel specific registers only on omap2 */
	116	#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
	117	#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
	118	#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
	119	#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
	120	#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
	121
	122	/----------------------------------------------------------------------------/
	123
	124	/* DMA channels for omap1 */
1da177e4 LT	125	#define OMAP_DMA_NO_DEVICE 0
	126	#define OMAP_DMA_MCSI1_TX 1
	127	#define OMAP_DMA_MCSI1_RX 2
	128	#define OMAP_DMA_I2C_RX 3
	129	#define OMAP_DMA_I2C_TX 4
	130	#define OMAP_DMA_EXT_NDMA_REQ 5
	131	#define OMAP_DMA_EXT_NDMA_REQ2 6
	132	#define OMAP_DMA_UWIRE_TX 7
	133	#define OMAP_DMA_MCBSP1_TX 8
	134	#define OMAP_DMA_MCBSP1_RX 9
	135	#define OMAP_DMA_MCBSP3_TX 10
	136	#define OMAP_DMA_MCBSP3_RX 11
	137	#define OMAP_DMA_UART1_TX 12
	138	#define OMAP_DMA_UART1_RX 13
	139	#define OMAP_DMA_UART2_TX 14
	140	#define OMAP_DMA_UART2_RX 15
	141	#define OMAP_DMA_MCBSP2_TX 16
	142	#define OMAP_DMA_MCBSP2_RX 17
	143	#define OMAP_DMA_UART3_TX 18
	144	#define OMAP_DMA_UART3_RX 19
	145	#define OMAP_DMA_CAMERA_IF_RX 20
	146	#define OMAP_DMA_MMC_TX 21
	147	#define OMAP_DMA_MMC_RX 22
	148	#define OMAP_DMA_NAND 23
	149	#define OMAP_DMA_IRQ_LCD_LINE 24
	150	#define OMAP_DMA_MEMORY_STICK 25
	151	#define OMAP_DMA_USB_W2FC_RX0 26
	152	#define OMAP_DMA_USB_W2FC_RX1 27
	153	#define OMAP_DMA_USB_W2FC_RX2 28
	154	#define OMAP_DMA_USB_W2FC_TX0 29
	155	#define OMAP_DMA_USB_W2FC_TX1 30
	156	#define OMAP_DMA_USB_W2FC_TX2 31
	157
	158	/* These are only for 1610 */
	159	#define OMAP_DMA_CRYPTO_DES_IN 32
	160	#define OMAP_DMA_SPI_TX 33
	161	#define OMAP_DMA_SPI_RX 34
	162	#define OMAP_DMA_CRYPTO_HASH 35
	163	#define OMAP_DMA_CCP_ATTN 36
	164	#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
	165	#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
	166	#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
	167	#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
	168	#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
	169	#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
	170	#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
	171	#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
	172	#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
	173	#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
	174	#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
	175	#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
	176	#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
	177	#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
	178	#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
	179	#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
	180	#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
	181	#define OMAP_DMA_MMC2_TX 54
	182	#define OMAP_DMA_MMC2_RX 55
	183	#define OMAP_DMA_CRYPTO_DES_OUT 56
	184
9ad5897c TL	185	/* DMA channels for 24xx */
	186	#define OMAP24XX_DMA_NO_DEVICE 0
	187	#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
7ff879db TL	188	#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
7ff879db TL	189	#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
9ad5897c TL	190	#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
	191	#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
	192	#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
	193	#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */
	194	#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
	195	#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
	196	#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
	197	#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
	198	#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
	199	#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
7ff879db TL	200	#define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
	201	#define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
	202	#define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
9ad5897c TL	203	#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */
	204	#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */
	205	#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
	206	#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
	207	#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
	208	#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
	209	#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
	210	#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
	211	#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
	212	#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
	213	#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
	214	#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
	215	#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
	216	#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
	217	#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */
	218	#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */
	219	#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */
	220	#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */
	221	#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */
	222	#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */
	223	#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */
	224	#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */
	225	#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */
	226	#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */
	227	#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */
	228	#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */
	229	#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */
	230	#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */
	231	#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */
	232	#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */
1da177e4	233
9ad5897c TL	234	#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */
	235	#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */
	236	#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */
	237	#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */
	238	#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */
	239	#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */
	240	#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */
	241	#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */
	242	#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */
	243	#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */
	244	#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */
	245	#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */
	246	#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */
	247	#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */
	248	#define OMAP24XX_DMA_MS 63 /* SDMA_62 */
7ff879db	249	#define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
9ad5897c TL	250
	251	/----------------------------------------------------------------------------/
	252
	253	/* Hardware registers for LCD DMA */
1da177e4 LT	254	#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
	255	#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
	256	#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
	257	#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
	258	#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
	259	#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
	260
	261	#define OMAP1610_DMA_LCD_BASE (0xfffee300)
9ad5897c	262	#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
1da177e4 LT	263	#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
	264	#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
	265	#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
	266	#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
	267	#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
	268	#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
	269	#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
	270	#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
	271	#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
	272	#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
	273	#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
	274	#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
	275	#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
	276	#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
	277	#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
	278	#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
	279
7ff879db	280	#define OMAP1_DMA_TOUT_IRQ (1 << 0)
1da177e4 LT	281	#define OMAP_DMA_DROP_IRQ (1 << 1)
	282	#define OMAP_DMA_HALF_IRQ (1 << 2)
	283	#define OMAP_DMA_FRAME_IRQ (1 << 3)
	284	#define OMAP_DMA_LAST_IRQ (1 << 4)
	285	#define OMAP_DMA_BLOCK_IRQ (1 << 5)
9ad5897c TL	286	#define OMAP1_DMA_SYNC_IRQ (1 << 6)
	287	#define OMAP2_DMA_PKT_IRQ (1 << 7)
	288	#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
	289	#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
	290	#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
	291	#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
1da177e4 LT	292
	293	#define OMAP_DMA_DATA_TYPE_S8 0x00
	294	#define OMAP_DMA_DATA_TYPE_S16 0x01
	295	#define OMAP_DMA_DATA_TYPE_S32 0x02
	296
	297	#define OMAP_DMA_SYNC_ELEMENT 0x00
	298	#define OMAP_DMA_SYNC_FRAME 0x01
	299	#define OMAP_DMA_SYNC_BLOCK 0x02
	300
	301	#define OMAP_DMA_PORT_EMIFF 0x00
	302	#define OMAP_DMA_PORT_EMIFS 0x01
	303	#define OMAP_DMA_PORT_OCP_T1 0x02
	304	#define OMAP_DMA_PORT_TIPB 0x03
	305	#define OMAP_DMA_PORT_OCP_T2 0x04
	306	#define OMAP_DMA_PORT_MPUI 0x05
	307
	308	#define OMAP_DMA_AMODE_CONSTANT 0x00
	309	#define OMAP_DMA_AMODE_POST_INC 0x01
	310	#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
	311	#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
	312
	313	/* LCD DMA block numbers */
	314	enum {
	315	OMAP_LCD_DMA_B1_TOP,
	316	OMAP_LCD_DMA_B1_BOTTOM,
	317	OMAP_LCD_DMA_B2_TOP,
	318	OMAP_LCD_DMA_B2_BOTTOM
	319	};
	320
	321	enum omap_dma_burst_mode {
	322	OMAP_DMA_DATA_BURST_DIS = 0,
	323	OMAP_DMA_DATA_BURST_4,
6dc3c8f2 KP	324	OMAP_DMA_DATA_BURST_8,
6dc3c8f2 KP	325	OMAP_DMA_DATA_BURST_16,
1da177e4 LT	326	};
	327
	328	enum omap_dma_color_mode {
	329	OMAP_DMA_COLOR_DIS = 0,
	330	OMAP_DMA_CONSTANT_FILL,
	331	OMAP_DMA_TRANSPARENT_COPY
	332	};
	333
709eb3e5 TL	334	enum omap_dma_write_mode {
	335	OMAP_DMA_WRITE_NON_POSTED = 0,
	336	OMAP_DMA_WRITE_POSTED,
	337	OMAP_DMA_WRITE_LAST_NON_POSTED
	338	};
	339
9ad5897c TL	340	struct omap_dma_channel_params {
	341	int data_type; /* data type 8,16,32 */
	342	int elem_count; /* number of elements in a frame */
	343	int frame_count; /* number of frames in a element */
	344
	345	int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
	346	int src_amode; /* constant , post increment, indexed , double indexed */
123e9a55	347	unsigned long src_start; /* source address : physical */
9ad5897c TL	348	int src_ei; /* source element index */
	349	int src_fi; /* source frame index */
	350
	351	int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
	352	int dst_amode; /* constant , post increment, indexed , double indexed */
123e9a55	353	unsigned long dst_start; /* source address : physical */
9ad5897c TL	354	int dst_ei; /* source element index */
	355	int dst_fi; /* source frame index */
	356
	357	int trigger; /* trigger attached if the channel is synchronized */
	358	int sync_mode; /* sycn on element, frame , block or packet */
	359	int src_or_dst_synch; /* source synch(1) or destination synch(0) */
	360
	361	int ie; /* interrupt enabled */
	362	};
	363
	364
709eb3e5	365	extern void omap_set_dma_priority(int lch, int dst_port, int priority);
1da177e4 LT	366	extern int omap_request_dma(int dev_id, const char *dev_name,
	367	void (* callback)(int lch, u16 ch_status, void *data),
	368	void data, int dma_ch);
	369	extern void omap_enable_dma_irq(int ch, u16 irq_bits);
	370	extern void omap_disable_dma_irq(int ch, u16 irq_bits);
	371	extern void omap_free_dma(int ch);
	372	extern void omap_start_dma(int lch);
	373	extern void omap_stop_dma(int lch);
	374	extern void omap_set_dma_transfer_params(int lch, int data_type,
	375	int elem_count, int frame_count,
9ad5897c TL	376	int sync_mode,
9ad5897c TL	377	int dma_trigger, int src_or_dst_synch);
1da177e4 LT	378	extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
1da177e4 LT	379	u32 color);
709eb3e5	380	extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
1da177e4 LT	381
1da177e4 LT	382	extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
9ad5897c TL	383	unsigned long src_start,
9ad5897c TL	384	int src_ei, int src_fi);
1da177e4 LT	385	extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
	386	extern void omap_set_dma_src_data_pack(int lch, int enable);
	387	extern void omap_set_dma_src_burst_mode(int lch,
	388	enum omap_dma_burst_mode burst_mode);
	389
	390	extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
9ad5897c TL	391	unsigned long dest_start,
9ad5897c TL	392	int dst_ei, int dst_fi);
1da177e4 LT	393	extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
	394	extern void omap_set_dma_dest_data_pack(int lch, int enable);
	395	extern void omap_set_dma_dest_burst_mode(int lch,
	396	enum omap_dma_burst_mode burst_mode);
	397
9ad5897c TL	398	extern void omap_set_dma_params(int lch,
	399	struct omap_dma_channel_params * params);
	400
1da177e4 LT	401	extern void omap_dma_link_lch (int lch_head, int lch_queue);
	402	extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
	403
709eb3e5 TL	404	extern int omap_set_dma_callback(int lch,
	405	void (* callback)(int lch, u16 ch_status, void *data),
	406	void *data);
1da177e4 LT	407	extern dma_addr_t omap_get_dma_src_pos(int lch);
1da177e4 LT	408	extern dma_addr_t omap_get_dma_dst_pos(int lch);
9839c6b8	409	extern int omap_get_dma_src_addr_counter(int lch);
1da177e4	410	extern void omap_clear_dma(int lch);
bb13b5fd	411	extern int omap_dma_running(void);
1da177e4	412
1da177e4 LT	413	/* LCD DMA functions */
	414	extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
	415	void *data);
	416	extern void omap_free_lcd_dma(void);
	417	extern void omap_setup_lcd_dma(void);
	418	extern void omap_enable_lcd_dma(void);
	419	extern void omap_stop_lcd_dma(void);
0dc5e77c	420	extern int omap_lcd_dma_ext_running(void);
1da177e4 LT	421	extern void omap_set_lcd_dma_ext_controller(int external);
	422	extern void omap_set_lcd_dma_single_transfer(int single);
	423	extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
	424	int data_type);
	425	extern void omap_set_lcd_dma_b1_rotation(int rotate);
	426	extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
	427	extern void omap_set_lcd_dma_b1_mirror(int mirror);
	428	extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
	429
	430	#endif /* __ASM_ARCH_DMA_H */