[deliverable/linux.git] / include / asm-arm / arch-realview / board-eb.h

/*
 * include/asm-arm/arch-realview/board-eb.h
 *
 * Copyright (C) 2007 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#ifndef __ASM_ARCH_BOARD_EB_H
#define __ASM_ARCH_BOARD_EB_H

#include <asm/arch/platform.h>

/*
 * RealView EB + ARM11MPCore peripheral addresses
 */
#ifdef CONFIG_REALVIEW_MPCORE_REVB
#define REALVIEW_EB11MP_SCU_BASE	0x10100000	/* SCU registers */
#define REALVIEW_EB11MP_GIC_CPU_BASE	0x10100100	/* Generic interrupt controller CPU interface */
#define REALVIEW_EB11MP_TWD_BASE	0x10100700
#define REALVIEW_EB11MP_TWD_SIZE	0x00000100
#define REALVIEW_EB11MP_GIC_DIST_BASE	0x10101000	/* Generic interrupt controller distributor */
#define REALVIEW_EB11MP_L220_BASE	0x10102000	/* L220 registers */
#define REALVIEW_EB11MP_SYS_PLD_CTRL1	0xD8		/* Register offset for MPCore sysctl */
#else
#define REALVIEW_EB11MP_SCU_BASE	0x1F000000	/* SCU registers */
#define REALVIEW_EB11MP_GIC_CPU_BASE	0x1F000100	/* Generic interrupt controller CPU interface */
#define REALVIEW_EB11MP_TWD_BASE	0x1F000700
#define REALVIEW_EB11MP_TWD_SIZE	0x00000100
#define REALVIEW_EB11MP_GIC_DIST_BASE	0x1F001000	/* Generic interrupt controller distributor */
#define REALVIEW_EB11MP_L220_BASE	0x1F002000	/* L220 registers */
#define REALVIEW_EB11MP_SYS_PLD_CTRL1	0x74		/* Register offset for MPCore sysctl */
#endif

#define IRQ_EB_GIC_START	32

/*
 * RealView EB interrupt sources
 */
#define IRQ_EB_WDOG		(IRQ_EB_GIC_START + 0)		/* Watchdog timer */
#define IRQ_EB_SOFT		(IRQ_EB_GIC_START + 1)		/* Software interrupt */
#define IRQ_EB_COMMRx		(IRQ_EB_GIC_START + 2)		/* Debug Comm Rx interrupt */
#define IRQ_EB_COMMTx		(IRQ_EB_GIC_START + 3)		/* Debug Comm Tx interrupt */
#define IRQ_EB_TIMER0_1		(IRQ_EB_GIC_START + 4)		/* Timer 0 and 1 */
#define IRQ_EB_TIMER2_3		(IRQ_EB_GIC_START + 5)		/* Timer 2 and 3 */
#define IRQ_EB_GPIO0		(IRQ_EB_GIC_START + 6)		/* GPIO 0 */
#define IRQ_EB_GPIO1		(IRQ_EB_GIC_START + 7)		/* GPIO 1 */
#define IRQ_EB_GPIO2		(IRQ_EB_GIC_START + 8)		/* GPIO 2 */
								/* 9 reserved */
#define IRQ_EB_RTC		(IRQ_EB_GIC_START + 10)		/* Real Time Clock */
#define IRQ_EB_SSP		(IRQ_EB_GIC_START + 11)		/* Synchronous Serial Port */
#define IRQ_EB_UART0		(IRQ_EB_GIC_START + 12)		/* UART 0 on development chip */
#define IRQ_EB_UART1		(IRQ_EB_GIC_START + 13)		/* UART 1 on development chip */
#define IRQ_EB_UART2		(IRQ_EB_GIC_START + 14)		/* UART 2 on development chip */
#define IRQ_EB_UART3		(IRQ_EB_GIC_START + 15)		/* UART 3 on development chip */
#define IRQ_EB_SCI		(IRQ_EB_GIC_START + 16)		/* Smart Card Interface */
#define IRQ_EB_MMCI0A		(IRQ_EB_GIC_START + 17)		/* Multimedia Card 0A */
#define IRQ_EB_MMCI0B		(IRQ_EB_GIC_START + 18)		/* Multimedia Card 0B */
#define IRQ_EB_AACI		(IRQ_EB_GIC_START + 19)		/* Audio Codec */
#define IRQ_EB_KMI0		(IRQ_EB_GIC_START + 20)		/* Keyboard/Mouse port 0 */
#define IRQ_EB_KMI1		(IRQ_EB_GIC_START + 21)		/* Keyboard/Mouse port 1 */
#define IRQ_EB_CHARLCD		(IRQ_EB_GIC_START + 22)		/* Character LCD */
#define IRQ_EB_CLCD		(IRQ_EB_GIC_START + 23)		/* CLCD controller */
#define IRQ_EB_DMA		(IRQ_EB_GIC_START + 24)		/* DMA controller */
#define IRQ_EB_PWRFAIL		(IRQ_EB_GIC_START + 25)		/* Power failure */
#define IRQ_EB_PISMO		(IRQ_EB_GIC_START + 26)		/* PISMO interface */
#define IRQ_EB_DoC		(IRQ_EB_GIC_START + 27)		/* Disk on Chip memory controller */
#define IRQ_EB_ETH		(IRQ_EB_GIC_START + 28)		/* Ethernet controller */
#define IRQ_EB_USB		(IRQ_EB_GIC_START + 29)		/* USB controller */
#define IRQ_EB_TSPEN		(IRQ_EB_GIC_START + 30)		/* Touchscreen pen */
#define IRQ_EB_TSKPAD		(IRQ_EB_GIC_START + 31)		/* Touchscreen keypad */

/*
 * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
 */
#define IRQ_EB11MP_AACI		(IRQ_EB_GIC_START + 0)
#define IRQ_EB11MP_TIMER0_1	(IRQ_EB_GIC_START + 1)
#define IRQ_EB11MP_TIMER2_3	(IRQ_EB_GIC_START + 2)
#define IRQ_EB11MP_USB		(IRQ_EB_GIC_START + 3)
#define IRQ_EB11MP_UART0	(IRQ_EB_GIC_START + 4)
#define IRQ_EB11MP_UART1	(IRQ_EB_GIC_START + 5)
#define IRQ_EB11MP_RTC		(IRQ_EB_GIC_START + 6)
#define IRQ_EB11MP_KMI0		(IRQ_EB_GIC_START + 7)
#define IRQ_EB11MP_KMI1		(IRQ_EB_GIC_START + 8)
#define IRQ_EB11MP_ETH		(IRQ_EB_GIC_START + 9)
#define IRQ_EB11MP_EB_IRQ1	(IRQ_EB_GIC_START + 10)		/* main GIC */
#define IRQ_EB11MP_EB_IRQ2	(IRQ_EB_GIC_START + 11)		/* tile GIC */
#define IRQ_EB11MP_EB_FIQ1	(IRQ_EB_GIC_START + 12)		/* main GIC */
#define IRQ_EB11MP_EB_FIQ2	(IRQ_EB_GIC_START + 13)		/* tile GIC */
#define IRQ_EB11MP_MMCI0A	(IRQ_EB_GIC_START + 14)
#define IRQ_EB11MP_MMCI0B	(IRQ_EB_GIC_START + 15)

#define IRQ_EB11MP_PMU_CPU0	(IRQ_EB_GIC_START + 17)
#define IRQ_EB11MP_PMU_CPU1	(IRQ_EB_GIC_START + 18)
#define IRQ_EB11MP_PMU_CPU2	(IRQ_EB_GIC_START + 19)
#define IRQ_EB11MP_PMU_CPU3	(IRQ_EB_GIC_START + 20)
#define IRQ_EB11MP_PMU_SCU0	(IRQ_EB_GIC_START + 21)
#define IRQ_EB11MP_PMU_SCU1	(IRQ_EB_GIC_START + 22)
#define IRQ_EB11MP_PMU_SCU2	(IRQ_EB_GIC_START + 23)
#define IRQ_EB11MP_PMU_SCU3	(IRQ_EB_GIC_START + 24)
#define IRQ_EB11MP_PMU_SCU4	(IRQ_EB_GIC_START + 25)
#define IRQ_EB11MP_PMU_SCU5	(IRQ_EB_GIC_START + 26)
#define IRQ_EB11MP_PMU_SCU6	(IRQ_EB_GIC_START + 27)
#define IRQ_EB11MP_PMU_SCU7	(IRQ_EB_GIC_START + 28)

#define IRQ_EB11MP_L220_EVENT	(IRQ_EB_GIC_START + 29)
#define IRQ_EB11MP_L220_SLAVE	(IRQ_EB_GIC_START + 30)
#define IRQ_EB11MP_L220_DECODE	(IRQ_EB_GIC_START + 31)

#define IRQ_EB11MP_UART2	-1
#define IRQ_EB11MP_UART3	-1
#define IRQ_EB11MP_CLCD		-1
#define IRQ_EB11MP_DMA		-1
#define IRQ_EB11MP_WDOG		-1
#define IRQ_EB11MP_GPIO0	-1
#define IRQ_EB11MP_GPIO1	-1
#define IRQ_EB11MP_GPIO2	-1
#define IRQ_EB11MP_SCI		-1
#define IRQ_EB11MP_SSP		-1

#define NR_GIC_EB11MP		2

/*
 * Only define NR_IRQS if less than NR_IRQS_EB
 */
#define NR_IRQS_EB		(IRQ_EB_GIC_START + 96)

#if defined(CONFIG_MACH_REALVIEW_EB) \
	&& (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
#undef NR_IRQS
#define NR_IRQS			NR_IRQS_EB
#endif

#if defined(CONFIG_REALVIEW_MPCORE) \
	&& (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
#undef MAX_GIC_NR
#define MAX_GIC_NR		NR_GIC_EB11MP
#endif

#endif	/* __ASM_ARCH_BOARD_EB_H */
Commit	Line	Data
356cb470 CM	1	/*
	2	* include/asm-arm/arch-realview/board-eb.h
	3	*
	4	* Copyright (C) 2007 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	18	* MA 02110-1301, USA.
	19	*/
	20
	21	#ifndef __ASM_ARCH_BOARD_EB_H
	22	#define __ASM_ARCH_BOARD_EB_H
	23
	24	#include <asm/arch/platform.h>
	25
	26	/*
	27	* RealView EB + ARM11MPCore peripheral addresses
	28	*/
	29	#ifdef CONFIG_REALVIEW_MPCORE_REVB
	30	#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
	31	#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
	32	#define REALVIEW_EB11MP_TWD_BASE 0x10100700
	33	#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
	34	#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
	35	#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
	36	#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
	37	#else
	38	#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
	39	#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
	40	#define REALVIEW_EB11MP_TWD_BASE 0x1F000700
	41	#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
	42	#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
	43	#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
	44	#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
	45	#endif
	46
	47	#define IRQ_EB_GIC_START 32
	48
	49	/*
	50	* RealView EB interrupt sources
	51	*/
	52	#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
	53	#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
	54	#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
	55	#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
	56	#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
	57	#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
	58	#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
	59	#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
	60	#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
	61	/* 9 reserved */
	62	#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
	63	#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
	64	#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
65	#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
66	#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
67	#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
68	#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
69	#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
70	#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
71	#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
72	#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
73	#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
74	#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
75	#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
76	#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
77	#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
78	#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
79	#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
80	#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
81	#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
82	#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
83	#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
84
85	/*
86	* RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
87	*/
88	#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
89	#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
90	#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
91	#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
92	#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
93	#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
94	#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
95	#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
96	#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
97	#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
98	#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
99	#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
100	#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
101	#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
102	#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
103	#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
104
105	#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
106	#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
107	#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
108	#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
109	#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
110	#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
111	#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
112	#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
113	#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
114	#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
115	#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
116	#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
117
118	#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
119	#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
120	#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
121
122	#define IRQ_EB11MP_UART2 -1
123	#define IRQ_EB11MP_UART3 -1
124	#define IRQ_EB11MP_CLCD -1
125	#define IRQ_EB11MP_DMA -1
126	#define IRQ_EB11MP_WDOG -1
127	#define IRQ_EB11MP_GPIO0 -1
128	#define IRQ_EB11MP_GPIO1 -1
129	#define IRQ_EB11MP_GPIO2 -1
130	#define IRQ_EB11MP_SCI -1
131	#define IRQ_EB11MP_SSP -1
132
133	#define NR_GIC_EB11MP 2
134
135	/*
136	* Only define NR_IRQS if less than NR_IRQS_EB
137	*/
138	#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
139
140	#if defined(CONFIG_MACH_REALVIEW_EB) \
141	&& (!defined(NR_IRQS) \|\| (NR_IRQS < NR_IRQS_EB))
142	#undef NR_IRQS
143	#define NR_IRQS NR_IRQS_EB
144	#endif
145
146	#if defined(CONFIG_REALVIEW_MPCORE) \
147	&& (!defined(MAX_GIC_NR) \|\| (MAX_GIC_NR < NR_GIC_EB11MP))
148	#undef MAX_GIC_NR
149	#define MAX_GIC_NR NR_GIC_EB11MP
150	#endif
151
152	#endif /* __ASM_ARCH_BOARD_EB_H */