[deliverable/linux.git] / include / asm-arm / arch-s3c2410 / map.h

/* linux/include/asm-arm/arch-s3c2410/map.h
 *
 * Copyright (c) 2003 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 - Memory map definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H

/* we have a bit of a tight squeeze to fit all our registers from
 * 0xF00000000 upwards, since we use all of the nGCS space in some
 * capacity, and also need to fit the S3C2410 registers in as well...
 *
 * we try to ensure stuff like the IRQ registers are available for
 * an single MOVS instruction (ie, only 8 bits of set data)
 *
 * Note, we are trying to remove some of these from the implementation
 * as they are only useful to certain drivers...
 */

#ifndef __ASSEMBLY__
#define S3C2410_ADDR(x)	  ((void __iomem __force *)0xF0000000 + (x))
#else
#define S3C2410_ADDR(x)	  (0xF0000000 + (x))
#endif

#define S3C2400_ADDR(x)	  S3C2410_ADDR(x)

/* interrupt controller is the first thing we put in, to make
 * the assembly code for the irq detection easier
 */
#define S3C24XX_VA_IRQ	   S3C2410_ADDR(0x00000000)
#define S3C2400_PA_IRQ	   (0x14400000)
#define S3C2410_PA_IRQ	   (0x4A000000)
#define S3C24XX_SZ_IRQ	   SZ_1M

/* memory controller registers */
#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
#define S3C2400_PA_MEMCTRL (0x14000000)
#define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C24XX_SZ_MEMCTRL SZ_1M

/* USB host controller */
#define S3C2400_PA_USBHOST (0x14200000)
#define S3C2410_PA_USBHOST (0x49000000)
#define S3C24XX_SZ_USBHOST SZ_1M

/* DMA controller */
#define S3C2400_PA_DMA	   (0x14600000)
#define S3C2410_PA_DMA	   (0x4B000000)
#define S3C24XX_SZ_DMA	   SZ_1M

/* Clock and Power management */
#define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00200000)
#define S3C2400_PA_CLKPWR  (0x14800000)
#define S3C2410_PA_CLKPWR  (0x4C000000)
#define S3C24XX_SZ_CLKPWR  SZ_1M

/* LCD controller */
#define S3C24XX_VA_LCD	   S3C2410_ADDR(0x00300000)
#define S3C2400_PA_LCD	   (0x14A00000)
#define S3C2410_PA_LCD	   (0x4D000000)
#define S3C24XX_SZ_LCD	   SZ_1M

/* NAND flash controller */
#define S3C2410_PA_NAND	   (0x4E000000)
#define S3C24XX_SZ_NAND	   SZ_1M

/* MMC controller - available on the S3C2400 */
#define S3C2400_PA_MMC 	   (0x15A00000)
#define S3C2400_SZ_MMC 	   SZ_1M

/* UARTs */
#define S3C24XX_VA_UART	   S3C2410_ADDR(0x00400000)
#define S3C2400_PA_UART	   (0x15000000)
#define S3C2410_PA_UART	   (0x50000000)
#define S3C24XX_SZ_UART	   SZ_1M

/* Timers */
#define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00500000)
#define S3C2400_PA_TIMER   (0x15100000)
#define S3C2410_PA_TIMER   (0x51000000)
#define S3C24XX_SZ_TIMER   SZ_1M

/* USB Device port */
#define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00600000)
#define S3C2400_PA_USBDEV  (0x15200140)
#define S3C2410_PA_USBDEV  (0x52000000)
#define S3C24XX_SZ_USBDEV  SZ_1M

/* Watchdog */
#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
#define S3C2400_PA_WATCHDOG (0x15300000)
#define S3C2410_PA_WATCHDOG (0x53000000)
#define S3C24XX_SZ_WATCHDOG SZ_1M

/* IIC hardware controller */
#define S3C2400_PA_IIC	   (0x15400000)
#define S3C2410_PA_IIC	   (0x54000000)
#define S3C24XX_SZ_IIC	   SZ_1M

/* IIS controller */
#define S3C2400_PA_IIS	   (0x15508000)
#define S3C2410_PA_IIS	   (0x55000000)
#define S3C24XX_SZ_IIS	   SZ_1M

/* GPIO ports */

/* the calculation for the VA of this must ensure that
 * it is the same distance apart from the UART in the
 * phsyical address space, as the initial mapping for the IO
 * is done as a 1:1 maping. This puts it (currently) at
 * 0xF6800000, which is not in the way of any current mapping
 * by the base system.
*/

#define S3C2400_PA_GPIO	   (0x15600000)
#define S3C2410_PA_GPIO	   (0x56000000)
#define S3C24XX_VA_GPIO	   ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
#define S3C24XX_SZ_GPIO	   SZ_1M

/* RTC */
#define S3C2400_PA_RTC	   (0x15700040)
#define S3C2410_PA_RTC	   (0x57000000)
#define S3C24XX_SZ_RTC	   SZ_1M

/* ADC */
#define S3C2400_PA_ADC	   (0x15800000)
#define S3C2410_PA_ADC	   (0x58000000)
#define S3C24XX_SZ_ADC	   SZ_1M

/* SPI */
#define S3C2400_PA_SPI	   (0x15900000)
#define S3C2410_PA_SPI	   (0x59000000)
#define S3C24XX_SZ_SPI	   SZ_1M

/* SDI */
#define S3C2410_PA_SDI	   (0x5A000000)
#define S3C24XX_SZ_SDI	   SZ_1M

/* CAMIF */
#define S3C2440_PA_CAMIF   (0x4F000000)
#define S3C2440_SZ_CAMIF   SZ_1M

/* AC97 */

#define S3C2440_PA_AC97	   (0x5B000000)
#define S3C2440_SZ_AC97	   SZ_1M

/* ISA style IO, for each machine to sort out mappings for, if it
 * implements it. We reserve two 16M regions for ISA.
 */

#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)

/* physical addresses of all the chip-select areas */

#define S3C2410_CS0 (0x00000000)
#define S3C2410_CS1 (0x08000000)
#define S3C2410_CS2 (0x10000000)
#define S3C2410_CS3 (0x18000000)
#define S3C2410_CS4 (0x20000000)
#define S3C2410_CS5 (0x28000000)
#define S3C2410_CS6 (0x30000000)
#define S3C2410_CS7 (0x38000000)

#define S3C2410_SDRAM_PA    (S3C2410_CS6)

#define S3C2400_CS0 (0x00000000)
#define S3C2400_CS1 (0x02000000)
#define S3C2400_CS2 (0x04000000)
#define S3C2400_CS3 (0x06000000)
#define S3C2400_CS4 (0x08000000)
#define S3C2400_CS5 (0x0A000000)
#define S3C2400_CS6 (0x0C000000)
#define S3C2400_CS7 (0x0E000000)

#define S3C2400_SDRAM_PA    (S3C2400_CS6)

/* Use a single interface for common resources between S3C24XX cpus */

#ifdef CONFIG_CPU_S3C2400
#define S3C24XX_PA_IRQ      S3C2400_PA_IRQ
#define S3C24XX_PA_MEMCTRL  S3C2400_PA_MEMCTRL
#define S3C24XX_PA_USBHOST  S3C2400_PA_USBHOST
#define S3C24XX_PA_DMA      S3C2400_PA_DMA
#define S3C24XX_PA_CLKPWR   S3C2400_PA_CLKPWR
#define S3C24XX_PA_LCD      S3C2400_PA_LCD
#define S3C24XX_PA_UART     S3C2400_PA_UART
#define S3C24XX_PA_TIMER    S3C2400_PA_TIMER
#define S3C24XX_PA_USBDEV   S3C2400_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
#define S3C24XX_PA_IIC      S3C2400_PA_IIC
#define S3C24XX_PA_IIS      S3C2400_PA_IIS
#define S3C24XX_PA_GPIO     S3C2400_PA_GPIO
#define S3C24XX_PA_RTC      S3C2400_PA_RTC
#define S3C24XX_PA_ADC      S3C2400_PA_ADC
#define S3C24XX_PA_SPI      S3C2400_PA_SPI
#else
#define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
#define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
#define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
#define S3C24XX_PA_DMA      S3C2410_PA_DMA
#define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
#define S3C24XX_PA_LCD      S3C2410_PA_LCD
#define S3C24XX_PA_UART     S3C2410_PA_UART
#define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
#define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
#define S3C24XX_PA_IIC      S3C2410_PA_IIC
#define S3C24XX_PA_IIS      S3C2410_PA_IIS
#define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
#define S3C24XX_PA_RTC      S3C2410_PA_RTC
#define S3C24XX_PA_ADC      S3C2410_PA_ADC
#define S3C24XX_PA_SPI      S3C2410_PA_SPI
#endif

/* deal with the registers that move under the 2412/2413 */

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#ifndef __ASSEMBLY__
extern void __iomem *s3c24xx_va_gpio2;
#endif
#ifdef CONFIG_CPU_S3C2412_ONLY
#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
#else
#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
#endif
#else
#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
#endif

#endif /* __ASM_ARCH_MAP_H */
Commit	Line	Data
1da177e4 LT	1	/* linux/include/asm-arm/arch-s3c2410/map.h
1da177e4 LT	2	*
f056076e BD	3	* Copyright (c) 2003 Simtec Electronics
f056076e BD	4	* Ben Dooks <ben@simtec.co.uk>
1da177e4 LT	5	*
	6	* S3C2410 - Memory map definitions
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#ifndef __ASM_ARCH_MAP_H
	14	#define __ASM_ARCH_MAP_H
	15
	16	/* we have a bit of a tight squeeze to fit all our registers from
	17	* 0xF00000000 upwards, since we use all of the nGCS space in some
	18	* capacity, and also need to fit the S3C2410 registers in as well...
	19	*
	20	* we try to ensure stuff like the IRQ registers are available for
	21	* an single MOVS instruction (ie, only 8 bits of set data)
	22	*
	23	* Note, we are trying to remove some of these from the implementation
	24	* as they are only useful to certain drivers...
	25	*/
	26
	27	#ifndef __ASSEMBLY__
cdcb3835	28	#define S3C2410_ADDR(x) ((void __iomem __force *)0xF0000000 + (x))
1da177e4 LT	29	#else
	30	#define S3C2410_ADDR(x) (0xF0000000 + (x))
	31	#endif
	32
	33	#define S3C2400_ADDR(x) S3C2410_ADDR(x)
	34
	35	/* interrupt controller is the first thing we put in, to make
	36	* the assembly code for the irq detection easier
	37	*/
	38	#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
	39	#define S3C2400_PA_IRQ (0x14400000)
	40	#define S3C2410_PA_IRQ (0x4A000000)
	41	#define S3C24XX_SZ_IRQ SZ_1M
	42
	43	/* memory controller registers */
	44	#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
	45	#define S3C2400_PA_MEMCTRL (0x14000000)
	46	#define S3C2410_PA_MEMCTRL (0x48000000)
	47	#define S3C24XX_SZ_MEMCTRL SZ_1M
	48
	49	/* USB host controller */
1da177e4 LT	50	#define S3C2400_PA_USBHOST (0x14200000)
	51	#define S3C2410_PA_USBHOST (0x49000000)
	52	#define S3C24XX_SZ_USBHOST SZ_1M
	53
	54	/* DMA controller */
1da177e4 LT	55	#define S3C2400_PA_DMA (0x14600000)
	56	#define S3C2410_PA_DMA (0x4B000000)
	57	#define S3C24XX_SZ_DMA SZ_1M
	58
	59	/* Clock and Power management */
58d19d6e	60	#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000)
1da177e4 LT	61	#define S3C2400_PA_CLKPWR (0x14800000)
	62	#define S3C2410_PA_CLKPWR (0x4C000000)
	63	#define S3C24XX_SZ_CLKPWR SZ_1M
	64
	65	/* LCD controller */
58d19d6e	66	#define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000)
1da177e4 LT	67	#define S3C2400_PA_LCD (0x14A00000)
	68	#define S3C2410_PA_LCD (0x4D000000)
	69	#define S3C24XX_SZ_LCD SZ_1M
	70
	71	/* NAND flash controller */
1da177e4 LT	72	#define S3C2410_PA_NAND (0x4E000000)
	73	#define S3C24XX_SZ_NAND SZ_1M
	74
	75	/* MMC controller - available on the S3C2400 */
1da177e4 LT	76	#define S3C2400_PA_MMC (0x15A00000)
	77	#define S3C2400_SZ_MMC SZ_1M
	78
	79	/* UARTs */
58d19d6e	80	#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000)
1da177e4 LT	81	#define S3C2400_PA_UART (0x15000000)
	82	#define S3C2410_PA_UART (0x50000000)
	83	#define S3C24XX_SZ_UART SZ_1M
	84
	85	/* Timers */
58d19d6e	86	#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000)
1da177e4 LT	87	#define S3C2400_PA_TIMER (0x15100000)
	88	#define S3C2410_PA_TIMER (0x51000000)
	89	#define S3C24XX_SZ_TIMER SZ_1M
	90
	91	/* USB Device port */
58d19d6e	92	#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000)
1da177e4 LT	93	#define S3C2400_PA_USBDEV (0x15200140)
	94	#define S3C2410_PA_USBDEV (0x52000000)
	95	#define S3C24XX_SZ_USBDEV SZ_1M
	96
	97	/* Watchdog */
58d19d6e	98	#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
1da177e4 LT	99	#define S3C2400_PA_WATCHDOG (0x15300000)
	100	#define S3C2410_PA_WATCHDOG (0x53000000)
	101	#define S3C24XX_SZ_WATCHDOG SZ_1M
	102
	103	/* IIC hardware controller */
1da177e4 LT	104	#define S3C2400_PA_IIC (0x15400000)
	105	#define S3C2410_PA_IIC (0x54000000)
	106	#define S3C24XX_SZ_IIC SZ_1M
	107
1da177e4	108	/* IIS controller */
1da177e4 LT	109	#define S3C2400_PA_IIS (0x15508000)
	110	#define S3C2410_PA_IIS (0x55000000)
	111	#define S3C24XX_SZ_IIS SZ_1M
	112
	113	/* GPIO ports */
68d59693 BD	114
	115	/* the calculation for the VA of this must ensure that
	116	* it is the same distance apart from the UART in the
	117	* phsyical address space, as the initial mapping for the IO
	118	* is done as a 1:1 maping. This puts it (currently) at
	119	* 0xF6800000, which is not in the way of any current mapping
	120	* by the base system.
	121	*/
	122
1da177e4 LT	123	#define S3C2400_PA_GPIO (0x15600000)
1da177e4 LT	124	#define S3C2410_PA_GPIO (0x56000000)
68d59693	125	#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
1da177e4 LT	126	#define S3C24XX_SZ_GPIO SZ_1M
	127
	128	/* RTC */
1da177e4 LT	129	#define S3C2400_PA_RTC (0x15700040)
	130	#define S3C2410_PA_RTC (0x57000000)
	131	#define S3C24XX_SZ_RTC SZ_1M
	132
	133	/* ADC */
1da177e4 LT	134	#define S3C2400_PA_ADC (0x15800000)
	135	#define S3C2410_PA_ADC (0x58000000)
	136	#define S3C24XX_SZ_ADC SZ_1M
	137
	138	/* SPI */
1da177e4 LT	139	#define S3C2400_PA_SPI (0x15900000)
	140	#define S3C2410_PA_SPI (0x59000000)
	141	#define S3C24XX_SZ_SPI SZ_1M
	142
	143	/* SDI */
1da177e4 LT	144	#define S3C2410_PA_SDI (0x5A000000)
	145	#define S3C24XX_SZ_SDI SZ_1M
	146
	147	/* CAMIF */
	148	#define S3C2440_PA_CAMIF (0x4F000000)
	149	#define S3C2440_SZ_CAMIF SZ_1M
	150
fd88edd2 BD	151	/* AC97 */
	152
	153	#define S3C2440_PA_AC97 (0x5B000000)
	154	#define S3C2440_SZ_AC97 SZ_1M
	155
1da177e4 LT	156	/* ISA style IO, for each machine to sort out mappings for, if it
	157	* implements it. We reserve two 16M regions for ISA.
	158	*/
	159
	160	#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
	161	#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
	162
	163	/* physical addresses of all the chip-select areas */
	164
	165	#define S3C2410_CS0 (0x00000000)
	166	#define S3C2410_CS1 (0x08000000)
	167	#define S3C2410_CS2 (0x10000000)
	168	#define S3C2410_CS3 (0x18000000)
	169	#define S3C2410_CS4 (0x20000000)
	170	#define S3C2410_CS5 (0x28000000)
	171	#define S3C2410_CS6 (0x30000000)
	172	#define S3C2410_CS7 (0x38000000)
	173
	174	#define S3C2410_SDRAM_PA (S3C2410_CS6)
	175
	176	#define S3C2400_CS0 (0x00000000)
	177	#define S3C2400_CS1 (0x02000000)
	178	#define S3C2400_CS2 (0x04000000)
	179	#define S3C2400_CS3 (0x06000000)
	180	#define S3C2400_CS4 (0x08000000)
	181	#define S3C2400_CS5 (0x0A000000)
	182	#define S3C2400_CS6 (0x0C000000)
	183	#define S3C2400_CS7 (0x0E000000)
	184
	185	#define S3C2400_SDRAM_PA (S3C2400_CS6)
	186
0367a8d3 LCVR	187	/* Use a single interface for common resources between S3C24XX cpus */
	188
	189	#ifdef CONFIG_CPU_S3C2400
	190	#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
	191	#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
	192	#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
	193	#define S3C24XX_PA_DMA S3C2400_PA_DMA
	194	#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
	195	#define S3C24XX_PA_LCD S3C2400_PA_LCD
	196	#define S3C24XX_PA_UART S3C2400_PA_UART
	197	#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
	198	#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
	199	#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
	200	#define S3C24XX_PA_IIC S3C2400_PA_IIC
	201	#define S3C24XX_PA_IIS S3C2400_PA_IIS
	202	#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
	203	#define S3C24XX_PA_RTC S3C2400_PA_RTC
	204	#define S3C24XX_PA_ADC S3C2400_PA_ADC
	205	#define S3C24XX_PA_SPI S3C2400_PA_SPI
	206	#else
	207	#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
	208	#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
	209	#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
	210	#define S3C24XX_PA_DMA S3C2410_PA_DMA
	211	#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
	212	#define S3C24XX_PA_LCD S3C2410_PA_LCD
	213	#define S3C24XX_PA_UART S3C2410_PA_UART
	214	#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
	215	#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
	216	#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
	217	#define S3C24XX_PA_IIC S3C2410_PA_IIC
	218	#define S3C24XX_PA_IIS S3C2410_PA_IIS
	219	#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
	220	#define S3C24XX_PA_RTC S3C2410_PA_RTC
	221	#define S3C24XX_PA_ADC S3C2410_PA_ADC
	222	#define S3C24XX_PA_SPI S3C2410_PA_SPI
	223	#endif
1da177e4	224
68d9ab39 BD	225	/* deal with the registers that move under the 2412/2413 */
	226
	227	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
	228	#ifndef __ASSEMBLY__
	229	extern void __iomem *s3c24xx_va_gpio2;
	230	#endif
	231	#ifdef CONFIG_CPU_S3C2412_ONLY
	232	#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
	233	#else
	234	#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
	235	#endif
	236	#else
	237	#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
	238	#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
	239	#endif
	240
1da177e4	241	#endif /* __ASM_ARCH_MAP_H */