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1 | /* linux/include/asm/arch-s3c2410/regs-lcd.h |
2 | * | |
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | |
4 | * http://www.simtec.co.uk/products/SWLINUX/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * | |
11 | * | |
12 | * Changelog: | |
13 | * 12-06-2003 BJD Created file | |
14 | * 26-06-2003 BJD Updated LCDCON register definitions | |
15 | * 12-03-2004 BJD Updated include protection | |
16 | * 10-03-2005 LCVR Changed S3C2410_VA to S3C24XX_VA | |
17 | */ | |
18 | ||
19 | ||
20 | #ifndef ___ASM_ARCH_REGS_LCD_H | |
21 | #define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $" | |
22 | ||
23 | #define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD) | |
24 | ||
25 | /* LCD control registers */ | |
26 | #define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) | |
27 | #define S3C2410_LCDCON2 S3C2410_LCDREG(0x04) | |
28 | #define S3C2410_LCDCON3 S3C2410_LCDREG(0x08) | |
29 | #define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C) | |
30 | #define S3C2410_LCDCON5 S3C2410_LCDREG(0x10) | |
31 | ||
32 | #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) | |
33 | #define S3C2410_LCDCON1_MMODE (1<<7) | |
34 | #define S3C2410_LCDCON1_DSCAN4 (0<<5) | |
35 | #define S3C2410_LCDCON1_STN4 (1<<5) | |
36 | #define S3C2410_LCDCON1_STN8 (2<<5) | |
37 | #define S3C2410_LCDCON1_TFT (3<<5) | |
38 | ||
39 | #define S3C2410_LCDCON1_STN1BPP (0<<1) | |
40 | #define S3C2410_LCDCON1_STN2GREY (1<<1) | |
41 | #define S3C2410_LCDCON1_STN4GREY (2<<1) | |
42 | #define S3C2410_LCDCON1_STN8BPP (3<<1) | |
43 | #define S3C2410_LCDCON1_STN12BPP (4<<1) | |
44 | ||
45 | #define S3C2410_LCDCON1_TFT1BPP (8<<1) | |
46 | #define S3C2410_LCDCON1_TFT2BPP (9<<1) | |
47 | #define S3C2410_LCDCON1_TFT4BPP (10<<1) | |
48 | #define S3C2410_LCDCON1_TFT8BPP (11<<1) | |
49 | #define S3C2410_LCDCON1_TFT16BPP (12<<1) | |
50 | #define S3C2410_LCDCON1_TFT24BPP (13<<1) | |
51 | ||
52 | #define S3C2410_LCDCON1_ENVID (1) | |
53 | ||
54 | #define S3C2410_LCDCON2_VBPD(x) ((x) << 24) | |
55 | #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) | |
56 | #define S3C2410_LCDCON2_VFPD(x) ((x) << 6) | |
57 | #define S3C2410_LCDCON2_VSPW(x) ((x) << 0) | |
58 | ||
59 | #define S3C2410_LCDCON3_HBPD(x) ((x) << 19) | |
60 | #define S3C2410_LCDCON3_WDLY(x) ((x) << 19) | |
61 | #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) | |
62 | #define S3C2410_LCDCON3_HFPD(x) ((x) << 0) | |
63 | #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) | |
64 | ||
65 | #define S3C2410_LCDCON4_MVAL(x) ((x) << 8) | |
66 | #define S3C2410_LCDCON4_HSPW(x) ((x) << 0) | |
67 | #define S3C2410_LCDCON4_WLH(x) ((x) << 0) | |
68 | ||
69 | #define S3C2410_LCDCON5_BPP24BL (1<<12) | |
70 | #define S3C2410_LCDCON5_FRM565 (1<<11) | |
71 | #define S3C2410_LCDCON5_INVVCLK (1<<10) | |
72 | #define S3C2410_LCDCON5_INVVLINE (1<<9) | |
73 | #define S3C2410_LCDCON5_INVVFRAME (1<<8) | |
74 | #define S3C2410_LCDCON5_INVVD (1<<7) | |
75 | #define S3C2410_LCDCON5_INVVDEN (1<<6) | |
76 | #define S3C2410_LCDCON5_INVPWREN (1<<5) | |
77 | #define S3C2410_LCDCON5_INVLEND (1<<4) | |
78 | #define S3C2410_LCDCON5_PWREN (1<<3) | |
79 | #define S3C2410_LCDCON5_ENLEND (1<<2) | |
80 | #define S3C2410_LCDCON5_BSWP (1<<1) | |
81 | #define S3C2410_LCDCON5_HWSWP (1<<0) | |
82 | ||
83 | /* framebuffer start addressed */ | |
84 | #define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14) | |
85 | #define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18) | |
86 | #define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C) | |
87 | ||
88 | #define S3C2410_LCDBANK(x) ((x) << 21) | |
89 | #define S3C2410_LCDBASEU(x) (x) | |
90 | ||
91 | #define S3C2410_OFFSIZE(x) ((x) << 11) | |
92 | #define S3C2410_PAGEWIDTH(x) (x) | |
93 | ||
94 | /* colour lookup and miscellaneous controls */ | |
95 | ||
96 | #define S3C2410_REDLUT S3C2410_LCDREG(0x20) | |
97 | #define S3C2410_GREENLUT S3C2410_LCDREG(0x24) | |
98 | #define S3C2410_BLUELUT S3C2410_LCDREG(0x28) | |
99 | ||
100 | #define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) | |
101 | #define S3C2410_TPAL S3C2410_LCDREG(0x50) | |
102 | ||
103 | /* interrupt info */ | |
104 | #define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) | |
105 | #define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) | |
106 | #define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) | |
107 | #define S3C2410_LPCSEL S3C2410_LCDREG(0x60) | |
108 | ||
109 | #define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) | |
110 | ||
111 | #endif /* ___ASM_ARCH_REGS_LCD_H */ | |
112 | ||
113 | ||
114 |