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1 | /* linux/include/asm-arm/arch-s3c2410/system-reset.h |
2 | * | |
3 | * Copyright (c) 2008 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 - System define for arch_reset() function | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
be509729 | 13 | #include <asm/arch/hardware.h> |
3c7d9c81 BD |
14 | #include <asm/io.h> |
15 | ||
16 | #include <asm/plat-s3c/regs-watchdog.h> | |
17 | #include <asm/arch/regs-clock.h> | |
18 | ||
19 | #include <linux/clk.h> | |
20 | #include <linux/err.h> | |
21 | ||
22 | extern void (*s3c24xx_reset_hook)(void); | |
23 | ||
24 | static void | |
25 | arch_reset(char mode) | |
26 | { | |
27 | struct clk *wdtclk; | |
28 | ||
29 | if (mode == 's') { | |
30 | cpu_reset(0); | |
31 | } | |
32 | ||
33 | if (s3c24xx_reset_hook) | |
34 | s3c24xx_reset_hook(); | |
35 | ||
36 | printk("arch_reset: attempting watchdog reset\n"); | |
37 | ||
38 | __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ | |
39 | ||
40 | wdtclk = clk_get(NULL, "watchdog"); | |
41 | if (!IS_ERR(wdtclk)) { | |
42 | clk_enable(wdtclk); | |
43 | } else | |
44 | printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); | |
45 | ||
46 | /* put initial values into count and data */ | |
47 | __raw_writel(0x80, S3C2410_WTCNT); | |
48 | __raw_writel(0x80, S3C2410_WTDAT); | |
49 | ||
50 | /* set the watchdog to go and reset... */ | |
51 | __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | | |
52 | S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); | |
53 | ||
54 | /* wait for reset to assert... */ | |
55 | mdelay(500); | |
56 | ||
57 | printk(KERN_ERR "Watchdog reset failed to assert reset\n"); | |
58 | ||
59 | /* delay to allow the serial port to show the message */ | |
60 | mdelay(50); | |
61 | ||
62 | /* we'll take a jump through zero as a poor second */ | |
63 | cpu_reset(0); | |
64 | } |