[deliverable/linux.git] / include / asm-arm / cacheflush.h

/*
 *  linux/include/asm-arm/cacheflush.h
 *
 *  Copyright (C) 1999-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ASMARM_CACHEFLUSH_H
#define _ASMARM_CACHEFLUSH_H

#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/glue.h>
#include <asm/shmparam.h>

#define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)

/*
 *	Cache Model
 *	===========
 */
#undef _CACHE
#undef MULTI_CACHE

#if defined(CONFIG_CPU_CACHE_V3)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE v3
# endif
#endif

#if defined(CONFIG_CPU_CACHE_V4)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE v4
# endif
#endif

#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
    defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
# define MULTI_CACHE 1
#endif

#if defined(CONFIG_CPU_ARM926T)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE arm926
# endif
#endif

#if defined(CONFIG_CPU_ARM940T)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE arm940
# endif
#endif

#if defined(CONFIG_CPU_ARM946E)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE arm946
# endif
#endif

#if defined(CONFIG_CPU_CACHE_V4WB)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE v4wb
# endif
#endif

#if defined(CONFIG_CPU_XSCALE)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE xscale
# endif
#endif

#if defined(CONFIG_CPU_XSC3)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE xsc3
# endif
#endif

#if defined(CONFIG_CPU_FEROCEON)
# define MULTI_CACHE 1
#endif

#if defined(CONFIG_CPU_V6)
//# ifdef _CACHE
#  define MULTI_CACHE 1
//# else
//#  define _CACHE v6
//# endif
#endif

#if defined(CONFIG_CPU_V7)
//# ifdef _CACHE
#  define MULTI_CACHE 1
//# else
//#  define _CACHE v7
//# endif
#endif

#if !defined(_CACHE) && !defined(MULTI_CACHE)
#error Unknown cache maintainence model
#endif

/*
 * This flag is used to indicate that the page pointed to by a pte
 * is dirty and requires cleaning before returning it to the user.
 */
#define PG_dcache_dirty PG_arch_1

/*
 *	MM Cache Management
 *	===================
 *
 *	The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
 *	implement these methods.
 *
 *	Start addresses are inclusive and end addresses are exclusive;
 *	start addresses should be rounded down, end addresses up.
 *
 *	See Documentation/cachetlb.txt for more information.
 *	Please note that the implementation of these, and the required
 *	effects are cache-type (VIVT/VIPT/PIPT) specific.
 *
 *	flush_cache_kern_all()
 *
 *		Unconditionally clean and invalidate the entire cache.
 *
 *	flush_cache_user_mm(mm)
 *
 *		Clean and invalidate all user space cache entries
 *		before a change of page tables.
 *
 *	flush_cache_user_range(start, end, flags)
 *
 *		Clean and invalidate a range of cache entries in the
 *		specified address space before a change of page tables.
 *		- start - user start address (inclusive, page aligned)
 *		- end   - user end address   (exclusive, page aligned)
 *		- flags - vma->vm_flags field
 *
 *	coherent_kern_range(start, end)
 *
 *		Ensure coherency between the Icache and the Dcache in the
 *		region described by start, end.  If you have non-snooping
 *		Harvard caches, you need to implement this function.
 *		- start  - virtual start address
 *		- end    - virtual end address
 *
 *	DMA Cache Coherency
 *	===================
 *
 *	dma_inv_range(start, end)
 *
 *		Invalidate (discard) the specified virtual address range.
 *		May not write back any entries.  If 'start' or 'end'
 *		are not cache line aligned, those lines must be written
 *		back.
 *		- start  - virtual start address
 *		- end    - virtual end address
 *
 *	dma_clean_range(start, end)
 *
 *		Clean (write back) the specified virtual address range.
 *		- start  - virtual start address
 *		- end    - virtual end address
 *
 *	dma_flush_range(start, end)
 *
 *		Clean and invalidate the specified virtual address range.
 *		- start  - virtual start address
 *		- end    - virtual end address
 */

struct cpu_cache_fns {
	void (*flush_kern_all)(void);
	void (*flush_user_all)(void);
	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);

	void (*coherent_kern_range)(unsigned long, unsigned long);
	void (*coherent_user_range)(unsigned long, unsigned long);
	void (*flush_kern_dcache_page)(void *);

	void (*dma_inv_range)(const void *, const void *);
	void (*dma_clean_range)(const void *, const void *);
	void (*dma_flush_range)(const void *, const void *);
};

struct outer_cache_fns {
	void (*inv_range)(unsigned long, unsigned long);
	void (*clean_range)(unsigned long, unsigned long);
	void (*flush_range)(unsigned long, unsigned long);
};

/*
 * Select the calling method
 */
#ifdef MULTI_CACHE

extern struct cpu_cache_fns cpu_cache;

#define __cpuc_flush_kern_all		cpu_cache.flush_kern_all
#define __cpuc_flush_user_all		cpu_cache.flush_user_all
#define __cpuc_flush_user_range		cpu_cache.flush_user_range
#define __cpuc_coherent_kern_range	cpu_cache.coherent_kern_range
#define __cpuc_coherent_user_range	cpu_cache.coherent_user_range
#define __cpuc_flush_dcache_page	cpu_cache.flush_kern_dcache_page

/*
 * These are private to the dma-mapping API.  Do not use directly.
 * Their sole purpose is to ensure that data held in the cache
 * is visible to DMA, or data written by DMA to system memory is
 * visible to the CPU.
 */
#define dmac_inv_range			cpu_cache.dma_inv_range
#define dmac_clean_range		cpu_cache.dma_clean_range
#define dmac_flush_range		cpu_cache.dma_flush_range

#else

#define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
#define __cpuc_flush_user_all		__glue(_CACHE,_flush_user_cache_all)
#define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
#define __cpuc_coherent_kern_range	__glue(_CACHE,_coherent_kern_range)
#define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
#define __cpuc_flush_dcache_page	__glue(_CACHE,_flush_kern_dcache_page)

extern void __cpuc_flush_kern_all(void);
extern void __cpuc_flush_user_all(void);
extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
extern void __cpuc_flush_dcache_page(void *);

/*
 * These are private to the dma-mapping API.  Do not use directly.
 * Their sole purpose is to ensure that data held in the cache
 * is visible to DMA, or data written by DMA to system memory is
 * visible to the CPU.
 */
#define dmac_inv_range			__glue(_CACHE,_dma_inv_range)
#define dmac_clean_range		__glue(_CACHE,_dma_clean_range)
#define dmac_flush_range		__glue(_CACHE,_dma_flush_range)

extern void dmac_inv_range(const void *, const void *);
extern void dmac_clean_range(const void *, const void *);
extern void dmac_flush_range(const void *, const void *);

#endif

#ifdef CONFIG_OUTER_CACHE

extern struct outer_cache_fns outer_cache;

static inline void outer_inv_range(unsigned long start, unsigned long end)
{
	if (outer_cache.inv_range)
		outer_cache.inv_range(start, end);
}
static inline void outer_clean_range(unsigned long start, unsigned long end)
{
	if (outer_cache.clean_range)
		outer_cache.clean_range(start, end);
}
static inline void outer_flush_range(unsigned long start, unsigned long end)
{
	if (outer_cache.flush_range)
		outer_cache.flush_range(start, end);
}

#else

static inline void outer_inv_range(unsigned long start, unsigned long end)
{ }
static inline void outer_clean_range(unsigned long start, unsigned long end)
{ }
static inline void outer_flush_range(unsigned long start, unsigned long end)
{ }

#endif

/*
 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 * vmalloc, ioremap etc) in kernel space for pages.  Since the
 * direct-mappings of these pages may contain cached data, we need
 * to do a full cache flush to ensure that writebacks don't corrupt
 * data placed into these pages via the new mappings.
 */
#define flush_cache_vmap(start, end)		flush_cache_all()
#define flush_cache_vunmap(start, end)		flush_cache_all()

/*
 * Copy user data from/to a page which is mapped into a different
 * processes address space.  Really, we want to allow our "user
 * space" model to handle this.
 */
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
	do {							\
		memcpy(dst, src, len);				\
		flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
	} while (0)

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	do {							\
		memcpy(dst, src, len);				\
	} while (0)

/*
 * Convert calls to our calling convention.
 */
#define flush_cache_all()		__cpuc_flush_kern_all()
#ifndef CONFIG_CPU_CACHE_VIPT
static inline void flush_cache_mm(struct mm_struct *mm)
{
	if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
		__cpuc_flush_user_all();
}

static inline void
flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
{
	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
		__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
					vma->vm_flags);
}

static inline void
flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
{
	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
		unsigned long addr = user_addr & PAGE_MASK;
		__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
	}
}

static inline void
flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
			 unsigned long uaddr, void *kaddr,
			 unsigned long len, int write)
{
	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
		unsigned long addr = (unsigned long)kaddr;
		__cpuc_coherent_kern_range(addr, addr + len);
	}
}
#else
extern void flush_cache_mm(struct mm_struct *mm);
extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
				unsigned long uaddr, void *kaddr,
				unsigned long len, int write);
#endif

#define flush_cache_dup_mm(mm) flush_cache_mm(mm)

/*
 * flush_cache_user_range is used when we want to ensure that the
 * Harvard caches are synchronised for the user space address range.
 * This is used for the ARM private sys_cacheflush system call.
 */
#define flush_cache_user_range(vma,start,end) \
	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))

/*
 * Perform necessary cache operations to ensure that data previously
 * stored within this range of addresses can be executed by the CPU.
 */
#define flush_icache_range(s,e)		__cpuc_coherent_kern_range(s,e)

/*
 * Perform necessary cache operations to ensure that the TLB will
 * see data written in the specified area.
 */
#define clean_dcache_area(start,size)	cpu_dcache_clean_area(start, size)

/*
 * flush_dcache_page is used when the kernel has written to the page
 * cache page at virtual address page->virtual.
 *
 * If this page isn't mapped (ie, page_mapping == NULL), or it might
 * have userspace mappings, then we _must_ always clean + invalidate
 * the dcache entries associated with the kernel mapping.
 *
 * Otherwise we can defer the operation, and clean the cache when we are
 * about to change to user space.  This is the same method as used on SPARC64.
 * See update_mmu_cache for the user space part.
 */
extern void flush_dcache_page(struct page *);

extern void __flush_dcache_page(struct address_space *mapping, struct page *page);

static inline void __flush_icache_all(void)
{
	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
	    :
	    : "r" (0));
}

#define ARCH_HAS_FLUSH_ANON_PAGE
static inline void flush_anon_page(struct vm_area_struct *vma,
			 struct page *page, unsigned long vmaddr)
{
	extern void __flush_anon_page(struct vm_area_struct *vma,
				struct page *, unsigned long);
	if (PageAnon(page))
		__flush_anon_page(vma, page, vmaddr);
}

#define flush_dcache_mmap_lock(mapping) \
	spin_lock_irq(&(mapping)->tree_lock)
#define flush_dcache_mmap_unlock(mapping) \
	spin_unlock_irq(&(mapping)->tree_lock)

#define flush_icache_user_range(vma,page,addr,len) \
	flush_dcache_page(page)

/*
 * We don't appear to need to do anything here.  In fact, if we did, we'd
 * duplicate cache flushing elsewhere performed by flush_dcache_page().
 */
#define flush_icache_page(vma,page)	do { } while (0)

static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
	unsigned offset, size_t size)
{
	const void *start = (void __force *)virt + offset;
	dmac_inv_range(start, start + size);
}

#define __cacheid_present(val)			(val != read_cpuid(CPUID_ID))
#define __cacheid_type_v7(val)			((val & (7 << 29)) == (4 << 29))

#define __cacheid_vivt_prev7(val)		((val & (15 << 25)) != (14 << 25))
#define __cacheid_vipt_prev7(val)		((val & (15 << 25)) == (14 << 25))
#define __cacheid_vipt_nonaliasing_prev7(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))
#define __cacheid_vipt_aliasing_prev7(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))

#define __cacheid_vivt(val)			(__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
#define __cacheid_vipt(val)			(__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
#define __cacheid_vipt_nonaliasing(val)		(__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
#define __cacheid_vipt_aliasing(val)		(__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
#define __cacheid_vivt_asid_tagged_instr(val)	(__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)

#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)

#define cache_is_vivt()			1
#define cache_is_vipt()			0
#define cache_is_vipt_nonaliasing()	0
#define cache_is_vipt_aliasing()	0
#define icache_is_vivt_asid_tagged()	0

#elif defined(CONFIG_CPU_CACHE_VIPT)

#define cache_is_vivt()			0
#define cache_is_vipt()			1
#define cache_is_vipt_nonaliasing()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_vipt_nonaliasing(__val);			\
	})

#define cache_is_vipt_aliasing()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_vipt_aliasing(__val);				\
	})

#define icache_is_vivt_asid_tagged()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_vivt_asid_tagged_instr(__val);		\
	})

#else

#define cache_is_vivt()							\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		(!__cacheid_present(__val)) || __cacheid_vivt(__val);	\
	})
		
#define cache_is_vipt()							\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_present(__val) && __cacheid_vipt(__val);	\
	})

#define cache_is_vipt_nonaliasing()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_present(__val) &&				\
		 __cacheid_vipt_nonaliasing(__val);			\
	})

#define cache_is_vipt_aliasing()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_present(__val) &&				\
		 __cacheid_vipt_aliasing(__val);			\
	})

#define icache_is_vivt_asid_tagged()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_present(__val) &&				\
		 __cacheid_vivt_asid_tagged_instr(__val);		\
	})

#endif

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-arm/cacheflush.h
	3	*
	4	* Copyright (C) 1999-2002 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef _ASMARM_CACHEFLUSH_H
	11	#define _ASMARM_CACHEFLUSH_H
	12
1da177e4 LT	13	#include <linux/sched.h>
	14	#include <linux/mm.h>
	15
1da177e4	16	#include <asm/glue.h>
b8a9b66f RK	17	#include <asm/shmparam.h>
	18
	19	#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
1da177e4 LT	20
	21	/*
	22	* Cache Model
	23	* ===========
	24	*/
	25	#undef _CACHE
	26	#undef MULTI_CACHE
	27
6cc7cbef	28	#if defined(CONFIG_CPU_CACHE_V3)
1da177e4 LT	29	# ifdef _CACHE
	30	# define MULTI_CACHE 1
	31	# else
	32	# define _CACHE v3
	33	# endif
	34	#endif
	35
6cc7cbef	36	#if defined(CONFIG_CPU_CACHE_V4)
1da177e4 LT	37	# ifdef _CACHE
	38	# define MULTI_CACHE 1
	39	# else
	40	# define _CACHE v4
	41	# endif
	42	#endif
	43
	44	#if defined(CONFIG_CPU_ARM920T) \|\| defined(CONFIG_CPU_ARM922T) \|\| \
	45	defined(CONFIG_CPU_ARM925T) \|\| defined(CONFIG_CPU_ARM1020)
	46	# define MULTI_CACHE 1
	47	#endif
	48
	49	#if defined(CONFIG_CPU_ARM926T)
	50	# ifdef _CACHE
	51	# define MULTI_CACHE 1
	52	# else
	53	# define _CACHE arm926
	54	# endif
	55	#endif
	56
d60674eb HC	57	#if defined(CONFIG_CPU_ARM940T)
	58	# ifdef _CACHE
	59	# define MULTI_CACHE 1
	60	# else
	61	# define _CACHE arm940
	62	# endif
	63	#endif
	64
f37f46eb HC	65	#if defined(CONFIG_CPU_ARM946E)
	66	# ifdef _CACHE
	67	# define MULTI_CACHE 1
	68	# else
	69	# define _CACHE arm946
	70	# endif
	71	#endif
	72
6cc7cbef	73	#if defined(CONFIG_CPU_CACHE_V4WB)
1da177e4 LT	74	# ifdef _CACHE
	75	# define MULTI_CACHE 1
	76	# else
	77	# define _CACHE v4wb
	78	# endif
	79	#endif
	80
	81	#if defined(CONFIG_CPU_XSCALE)
	82	# ifdef _CACHE
	83	# define MULTI_CACHE 1
	84	# else
	85	# define _CACHE xscale
	86	# endif
	87	#endif
	88
23bdf86a LB	89	#if defined(CONFIG_CPU_XSC3)
	90	# ifdef _CACHE
	91	# define MULTI_CACHE 1
	92	# else
	93	# define _CACHE xsc3
	94	# endif
	95	#endif
	96
e50d6409	97	#if defined(CONFIG_CPU_FEROCEON)
836a8051	98	# define MULTI_CACHE 1
e50d6409 AH	99	#endif
e50d6409 AH	100
1da177e4 LT	101	#if defined(CONFIG_CPU_V6)
	102	//# ifdef _CACHE
	103	# define MULTI_CACHE 1
	104	//# else
	105	//# define _CACHE v6
	106	//# endif
	107	#endif
	108
bbe88886 CM	109	#if defined(CONFIG_CPU_V7)
	110	//# ifdef _CACHE
	111	# define MULTI_CACHE 1
	112	//# else
	113	//# define _CACHE v7
	114	//# endif
	115	#endif
	116
1da177e4 LT	117	#if !defined(_CACHE) && !defined(MULTI_CACHE)
	118	#error Unknown cache maintainence model
	119	#endif
	120
	121	/*
	122	* This flag is used to indicate that the page pointed to by a pte
	123	* is dirty and requires cleaning before returning it to the user.
	124	*/
	125	#define PG_dcache_dirty PG_arch_1
	126
	127	/*
	128	* MM Cache Management
	129	* ===================
	130	*
	131	* The arch/arm/mm/cache-.S and arch/arm/mm/proc-.S files
	132	* implement these methods.
	133	*
	134	* Start addresses are inclusive and end addresses are exclusive;
	135	* start addresses should be rounded down, end addresses up.
	136	*
	137	* See Documentation/cachetlb.txt for more information.
	138	* Please note that the implementation of these, and the required
	139	* effects are cache-type (VIVT/VIPT/PIPT) specific.
	140	*
	141	* flush_cache_kern_all()
	142	*
	143	* Unconditionally clean and invalidate the entire cache.
	144	*
	145	* flush_cache_user_mm(mm)
	146	*
	147	* Clean and invalidate all user space cache entries
	148	* before a change of page tables.
	149	*
	150	* flush_cache_user_range(start, end, flags)
	151	*
	152	* Clean and invalidate a range of cache entries in the
	153	* specified address space before a change of page tables.
	154	* - start - user start address (inclusive, page aligned)
	155	* - end - user end address (exclusive, page aligned)
	156	* - flags - vma->vm_flags field
	157	*
	158	* coherent_kern_range(start, end)
	159	*
	160	* Ensure coherency between the Icache and the Dcache in the
	161	* region described by start, end. If you have non-snooping
	162	* Harvard caches, you need to implement this function.
	163	* - start - virtual start address
	164	* - end - virtual end address
	165	*
	166	* DMA Cache Coherency
	167	* ===================
	168	*
	169	* dma_inv_range(start, end)
	170	*
	171	* Invalidate (discard) the specified virtual address range.
	172	* May not write back any entries. If 'start' or 'end'
	173	* are not cache line aligned, those lines must be written
	174	* back.
	175	* - start - virtual start address
	176	* - end - virtual end address
	177	*
	178	* dma_clean_range(start, end)
	179	*
	180	* Clean (write back) the specified virtual address range.
181	* - start - virtual start address
182	* - end - virtual end address
183	*
184	* dma_flush_range(start, end)
185	*
186	* Clean and invalidate the specified virtual address range.
187	* - start - virtual start address
188	* - end - virtual end address
189	*/
190
191	struct cpu_cache_fns {
192	void (*flush_kern_all)(void);
193	void (*flush_user_all)(void);
194	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
195
196	void (*coherent_kern_range)(unsigned long, unsigned long);
197	void (*coherent_user_range)(unsigned long, unsigned long);
198	void (flush_kern_dcache_page)(void );
199
7ae5a761 RK	200	void (dma_inv_range)(const void , const void *);
	201	void (dma_clean_range)(const void , const void *);
	202	void (dma_flush_range)(const void , const void *);
1da177e4 LT	203	};
1da177e4 LT	204
953233dc CM	205	struct outer_cache_fns {
	206	void (*inv_range)(unsigned long, unsigned long);
	207	void (*clean_range)(unsigned long, unsigned long);
	208	void (*flush_range)(unsigned long, unsigned long);
	209	};
	210
1da177e4 LT	211	/*
	212	* Select the calling method
	213	*/
	214	#ifdef MULTI_CACHE
	215
	216	extern struct cpu_cache_fns cpu_cache;
	217
	218	#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
	219	#define __cpuc_flush_user_all cpu_cache.flush_user_all
	220	#define __cpuc_flush_user_range cpu_cache.flush_user_range
	221	#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
	222	#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
	223	#define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page
	224
	225	/*
	226	* These are private to the dma-mapping API. Do not use directly.
	227	* Their sole purpose is to ensure that data held in the cache
	228	* is visible to DMA, or data written by DMA to system memory is
	229	* visible to the CPU.
	230	*/
	231	#define dmac_inv_range cpu_cache.dma_inv_range
	232	#define dmac_clean_range cpu_cache.dma_clean_range
	233	#define dmac_flush_range cpu_cache.dma_flush_range
	234
	235	#else
	236
	237	#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
	238	#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
	239	#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
	240	#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
	241	#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
	242	#define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page)
	243
	244	extern void __cpuc_flush_kern_all(void);
	245	extern void __cpuc_flush_user_all(void);
	246	extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
	247	extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
	248	extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
	249	extern void __cpuc_flush_dcache_page(void *);
	250
	251	/*
	252	* These are private to the dma-mapping API. Do not use directly.
	253	* Their sole purpose is to ensure that data held in the cache
	254	* is visible to DMA, or data written by DMA to system memory is
	255	* visible to the CPU.
	256	*/
	257	#define dmac_inv_range __glue(_CACHE,_dma_inv_range)
	258	#define dmac_clean_range __glue(_CACHE,_dma_clean_range)
	259	#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
	260
7ae5a761 RK	261	extern void dmac_inv_range(const void , const void );
	262	extern void dmac_clean_range(const void , const void );
	263	extern void dmac_flush_range(const void , const void );
1da177e4 LT	264
	265	#endif
	266
953233dc CM	267	#ifdef CONFIG_OUTER_CACHE
	268
	269	extern struct outer_cache_fns outer_cache;
	270
	271	static inline void outer_inv_range(unsigned long start, unsigned long end)
	272	{
	273	if (outer_cache.inv_range)
	274	outer_cache.inv_range(start, end);
	275	}
	276	static inline void outer_clean_range(unsigned long start, unsigned long end)
	277	{
	278	if (outer_cache.clean_range)
	279	outer_cache.clean_range(start, end);
	280	}
	281	static inline void outer_flush_range(unsigned long start, unsigned long end)
	282	{
	283	if (outer_cache.flush_range)
	284	outer_cache.flush_range(start, end);
	285	}
	286
	287	#else
	288
	289	static inline void outer_inv_range(unsigned long start, unsigned long end)
	290	{ }
	291	static inline void outer_clean_range(unsigned long start, unsigned long end)
	292	{ }
	293	static inline void outer_flush_range(unsigned long start, unsigned long end)
	294	{ }
	295
	296	#endif
	297
1da177e4 LT	298	/*
	299	* flush_cache_vmap() is used when creating mappings (eg, via vmap,
	300	* vmalloc, ioremap etc) in kernel space for pages. Since the
	301	* direct-mappings of these pages may contain cached data, we need
	302	* to do a full cache flush to ensure that writebacks don't corrupt
	303	* data placed into these pages via the new mappings.
	304	*/
	305	#define flush_cache_vmap(start, end) flush_cache_all()
	306	#define flush_cache_vunmap(start, end) flush_cache_all()
	307
	308	/*
	309	* Copy user data from/to a page which is mapped into a different
	310	* processes address space. Really, we want to allow our "user
	311	* space" model to handle this.
	312	*/
	313	#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
	314	do { \
1da177e4	315	memcpy(dst, src, len); \
a188ad2b	316	flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
1da177e4 LT	317	} while (0)
	318
	319	#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	320	do { \
1da177e4 LT	321	memcpy(dst, src, len); \
	322	} while (0)
	323
	324	/*
	325	* Convert calls to our calling convention.
	326	*/
	327	#define flush_cache_all() __cpuc_flush_kern_all()
d7b6b358	328	#ifndef CONFIG_CPU_CACHE_VIPT
1da177e4 LT	329	static inline void flush_cache_mm(struct mm_struct *mm)
	330	{
	331	if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
	332	__cpuc_flush_user_all();
	333	}
	334
	335	static inline void
	336	flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
	337	{
	338	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
	339	__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
	340	vma->vm_flags);
	341	}
	342
	343	static inline void
	344	flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
	345	{
	346	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
	347	unsigned long addr = user_addr & PAGE_MASK;
	348	__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
	349	}
	350	}
a188ad2b GD	351
	352	static inline void
	353	flush_ptrace_access(struct vm_area_struct vma, struct page page,
	354	unsigned long uaddr, void *kaddr,
	355	unsigned long len, int write)
	356	{
	357	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
	358	unsigned long addr = (unsigned long)kaddr;
	359	__cpuc_coherent_kern_range(addr, addr + len);
	360	}
	361	}
d7b6b358 RK	362	#else
	363	extern void flush_cache_mm(struct mm_struct *mm);
	364	extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
	365	extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
a188ad2b GD	366	extern void flush_ptrace_access(struct vm_area_struct vma, struct page page,
	367	unsigned long uaddr, void *kaddr,
	368	unsigned long len, int write);
d7b6b358	369	#endif
1da177e4	370
ec8c0446 RB	371	#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
ec8c0446 RB	372
1da177e4 LT	373	/*
	374	* flush_cache_user_range is used when we want to ensure that the
	375	* Harvard caches are synchronised for the user space address range.
	376	* This is used for the ARM private sys_cacheflush system call.
	377	*/
	378	#define flush_cache_user_range(vma,start,end) \
	379	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
	380
	381	/*
	382	* Perform necessary cache operations to ensure that data previously
	383	* stored within this range of addresses can be executed by the CPU.
	384	*/
	385	#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
	386
	387	/*
	388	* Perform necessary cache operations to ensure that the TLB will
	389	* see data written in the specified area.
	390	*/
	391	#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
	392
	393	/*
	394	* flush_dcache_page is used when the kernel has written to the page
	395	* cache page at virtual address page->virtual.
	396	*
	397	* If this page isn't mapped (ie, page_mapping == NULL), or it might
	398	* have userspace mappings, then we _must_ always clean + invalidate
	399	* the dcache entries associated with the kernel mapping.
	400	*
	401	* Otherwise we can defer the operation, and clean the cache when we are
	402	* about to change to user space. This is the same method as used on SPARC64.
	403	* See update_mmu_cache for the user space part.
	404	*/
	405	extern void flush_dcache_page(struct page *);
	406
1c9d3df5 RP	407	extern void __flush_dcache_page(struct address_space mapping, struct page page);
1c9d3df5 RP	408
826cbdaf CM	409	static inline void __flush_icache_all(void)
	410	{
	411	asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
	412	:
	413	: "r" (0));
	414	}
	415
6020dff0 RK	416	#define ARCH_HAS_FLUSH_ANON_PAGE
	417	static inline void flush_anon_page(struct vm_area_struct *vma,
	418	struct page *page, unsigned long vmaddr)
	419	{
	420	extern void __flush_anon_page(struct vm_area_struct *vma,
	421	struct page *, unsigned long);
	422	if (PageAnon(page))
	423	__flush_anon_page(vma, page, vmaddr);
	424	}
	425
1da177e4	426	#define flush_dcache_mmap_lock(mapping) \
19fd6231	427	spin_lock_irq(&(mapping)->tree_lock)
1da177e4	428	#define flush_dcache_mmap_unlock(mapping) \
19fd6231	429	spin_unlock_irq(&(mapping)->tree_lock)
1da177e4 LT	430
	431	#define flush_icache_user_range(vma,page,addr,len) \
	432	flush_dcache_page(page)
	433
	434	/*
	435	* We don't appear to need to do anything here. In fact, if we did, we'd
	436	* duplicate cache flushing elsewhere performed by flush_dcache_page().
	437	*/
	438	#define flush_icache_page(vma,page) do { } while (0)
	439
90833fda JH	440	static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
	441	unsigned offset, size_t size)
	442	{
	443	const void start = (void __force )virt + offset;
	444	dmac_inv_range(start, start + size);
	445	}
	446
aaf83acb CM	447	#define __cacheid_present(val) (val != read_cpuid(CPUID_ID))
	448	#define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29))
	449
	450	#define __cacheid_vivt_prev7(val) ((val & (15 << 25)) != (14 << 25))
	451	#define __cacheid_vipt_prev7(val) ((val & (15 << 25)) == (14 << 25))
	452	#define __cacheid_vipt_nonaliasing_prev7(val) ((val & (15 << 25 \| 1 << 23)) == (14 << 25))
	453	#define __cacheid_vipt_aliasing_prev7(val) ((val & (15 << 25 \| 1 << 23)) == (14 << 25 \| 1 << 23))
	454
	455	#define __cacheid_vivt(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
	456	#define __cacheid_vipt(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
	457	#define __cacheid_vipt_nonaliasing(val) (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
	458	#define __cacheid_vipt_aliasing(val) (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
065cf519	459	#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
1da177e4 LT	460
	461	#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
	462
	463	#define cache_is_vivt() 1
	464	#define cache_is_vipt() 0
	465	#define cache_is_vipt_nonaliasing() 0
	466	#define cache_is_vipt_aliasing() 0
065cf519	467	#define icache_is_vivt_asid_tagged() 0
1da177e4 LT	468
	469	#elif defined(CONFIG_CPU_CACHE_VIPT)
	470
	471	#define cache_is_vivt() 0
	472	#define cache_is_vipt() 1
	473	#define cache_is_vipt_nonaliasing() \
	474	({ \
	475	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
	476	__cacheid_vipt_nonaliasing(__val); \
	477	})
	478
	479	#define cache_is_vipt_aliasing() \
	480	({ \
	481	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
	482	__cacheid_vipt_aliasing(__val); \
	483	})
	484
065cf519 CM	485	#define icache_is_vivt_asid_tagged() \
	486	({ \
	487	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
	488	__cacheid_vivt_asid_tagged_instr(__val); \
	489	})
	490
1da177e4 LT	491	#else
	492
	493	#define cache_is_vivt() \
	494	({ \
	495	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
	496	(!__cacheid_present(__val)) \|\| __cacheid_vivt(__val); \
	497	})
	498
	499	#define cache_is_vipt() \
	500	({ \
	501	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
	502	__cacheid_present(__val) && __cacheid_vipt(__val); \
	503	})
	504
	505	#define cache_is_vipt_nonaliasing() \
	506	({ \
	507	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
	508	__cacheid_present(__val) && \
	509	__cacheid_vipt_nonaliasing(__val); \
	510	})
	511
	512	#define cache_is_vipt_aliasing() \
	513	({ \
	514	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
	515	__cacheid_present(__val) && \
	516	__cacheid_vipt_aliasing(__val); \
	517	})
	518
065cf519 CM	519	#define icache_is_vivt_asid_tagged() \
	520	({ \
	521	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
	522	__cacheid_present(__val) && \
	523	__cacheid_vivt_asid_tagged_instr(__val); \
	524	})
	525
1da177e4 LT	526	#endif
	527
	528	#endif