[deliverable/linux.git] / include / asm-arm / cacheflush.h

/*
 *  linux/include/asm-arm/cacheflush.h
 *
 *  Copyright (C) 1999-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ASMARM_CACHEFLUSH_H
#define _ASMARM_CACHEFLUSH_H

#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/glue.h>
#include <asm/shmparam.h>

#define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)

/*
 *	Cache Model
 *	===========
 */
#undef _CACHE
#undef MULTI_CACHE

#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE v3
# endif
#endif

#if defined(CONFIG_CPU_ARM720T)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE v4
# endif
#endif

#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
    defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
# define MULTI_CACHE 1
#endif

#if defined(CONFIG_CPU_ARM926T)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE arm926
# endif
#endif

#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE v4wb
# endif
#endif

#if defined(CONFIG_CPU_XSCALE)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE xscale
# endif
#endif

#if defined(CONFIG_CPU_XSC3)
# ifdef _CACHE
#  define MULTI_CACHE 1
# else
#  define _CACHE xsc3
# endif
#endif

#if defined(CONFIG_CPU_V6)
//# ifdef _CACHE
#  define MULTI_CACHE 1
//# else
//#  define _CACHE v6
//# endif
#endif

#if !defined(_CACHE) && !defined(MULTI_CACHE)
#error Unknown cache maintainence model
#endif

/*
 * This flag is used to indicate that the page pointed to by a pte
 * is dirty and requires cleaning before returning it to the user.
 */
#define PG_dcache_dirty PG_arch_1

/*
 *	MM Cache Management
 *	===================
 *
 *	The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
 *	implement these methods.
 *
 *	Start addresses are inclusive and end addresses are exclusive;
 *	start addresses should be rounded down, end addresses up.
 *
 *	See Documentation/cachetlb.txt for more information.
 *	Please note that the implementation of these, and the required
 *	effects are cache-type (VIVT/VIPT/PIPT) specific.
 *
 *	flush_cache_kern_all()
 *
 *		Unconditionally clean and invalidate the entire cache.
 *
 *	flush_cache_user_mm(mm)
 *
 *		Clean and invalidate all user space cache entries
 *		before a change of page tables.
 *
 *	flush_cache_user_range(start, end, flags)
 *
 *		Clean and invalidate a range of cache entries in the
 *		specified address space before a change of page tables.
 *		- start - user start address (inclusive, page aligned)
 *		- end   - user end address   (exclusive, page aligned)
 *		- flags - vma->vm_flags field
 *
 *	coherent_kern_range(start, end)
 *
 *		Ensure coherency between the Icache and the Dcache in the
 *		region described by start, end.  If you have non-snooping
 *		Harvard caches, you need to implement this function.
 *		- start  - virtual start address
 *		- end    - virtual end address
 *
 *	DMA Cache Coherency
 *	===================
 *
 *	dma_inv_range(start, end)
 *
 *		Invalidate (discard) the specified virtual address range.
 *		May not write back any entries.  If 'start' or 'end'
 *		are not cache line aligned, those lines must be written
 *		back.
 *		- start  - virtual start address
 *		- end    - virtual end address
 *
 *	dma_clean_range(start, end)
 *
 *		Clean (write back) the specified virtual address range.
 *		- start  - virtual start address
 *		- end    - virtual end address
 *
 *	dma_flush_range(start, end)
 *
 *		Clean and invalidate the specified virtual address range.
 *		- start  - virtual start address
 *		- end    - virtual end address
 */

struct cpu_cache_fns {
	void (*flush_kern_all)(void);
	void (*flush_user_all)(void);
	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);

	void (*coherent_kern_range)(unsigned long, unsigned long);
	void (*coherent_user_range)(unsigned long, unsigned long);
	void (*flush_kern_dcache_page)(void *);

	void (*dma_inv_range)(unsigned long, unsigned long);
	void (*dma_clean_range)(unsigned long, unsigned long);
	void (*dma_flush_range)(unsigned long, unsigned long);
};

/*
 * Select the calling method
 */
#ifdef MULTI_CACHE

extern struct cpu_cache_fns cpu_cache;

#define __cpuc_flush_kern_all		cpu_cache.flush_kern_all
#define __cpuc_flush_user_all		cpu_cache.flush_user_all
#define __cpuc_flush_user_range		cpu_cache.flush_user_range
#define __cpuc_coherent_kern_range	cpu_cache.coherent_kern_range
#define __cpuc_coherent_user_range	cpu_cache.coherent_user_range
#define __cpuc_flush_dcache_page	cpu_cache.flush_kern_dcache_page

/*
 * These are private to the dma-mapping API.  Do not use directly.
 * Their sole purpose is to ensure that data held in the cache
 * is visible to DMA, or data written by DMA to system memory is
 * visible to the CPU.
 */
#define dmac_inv_range			cpu_cache.dma_inv_range
#define dmac_clean_range		cpu_cache.dma_clean_range
#define dmac_flush_range		cpu_cache.dma_flush_range

#else

#define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
#define __cpuc_flush_user_all		__glue(_CACHE,_flush_user_cache_all)
#define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
#define __cpuc_coherent_kern_range	__glue(_CACHE,_coherent_kern_range)
#define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
#define __cpuc_flush_dcache_page	__glue(_CACHE,_flush_kern_dcache_page)

extern void __cpuc_flush_kern_all(void);
extern void __cpuc_flush_user_all(void);
extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
extern void __cpuc_flush_dcache_page(void *);

/*
 * These are private to the dma-mapping API.  Do not use directly.
 * Their sole purpose is to ensure that data held in the cache
 * is visible to DMA, or data written by DMA to system memory is
 * visible to the CPU.
 */
#define dmac_inv_range			__glue(_CACHE,_dma_inv_range)
#define dmac_clean_range		__glue(_CACHE,_dma_clean_range)
#define dmac_flush_range		__glue(_CACHE,_dma_flush_range)

extern void dmac_inv_range(unsigned long, unsigned long);
extern void dmac_clean_range(unsigned long, unsigned long);
extern void dmac_flush_range(unsigned long, unsigned long);

#endif

/*
 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 * vmalloc, ioremap etc) in kernel space for pages.  Since the
 * direct-mappings of these pages may contain cached data, we need
 * to do a full cache flush to ensure that writebacks don't corrupt
 * data placed into these pages via the new mappings.
 */
#define flush_cache_vmap(start, end)		flush_cache_all()
#define flush_cache_vunmap(start, end)		flush_cache_all()

/*
 * Copy user data from/to a page which is mapped into a different
 * processes address space.  Really, we want to allow our "user
 * space" model to handle this.
 */
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
	do {							\
		flush_cache_page(vma, vaddr, page_to_pfn(page));\
		memcpy(dst, src, len);				\
		flush_dcache_page(page);			\
	} while (0)

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	do {							\
		flush_cache_page(vma, vaddr, page_to_pfn(page));\
		memcpy(dst, src, len);				\
	} while (0)

/*
 * Convert calls to our calling convention.
 */
#define flush_cache_all()		__cpuc_flush_kern_all()
#ifndef CONFIG_CPU_CACHE_VIPT
static inline void flush_cache_mm(struct mm_struct *mm)
{
	if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
		__cpuc_flush_user_all();
}

static inline void
flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
{
	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
		__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
					vma->vm_flags);
}

static inline void
flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
{
	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
		unsigned long addr = user_addr & PAGE_MASK;
		__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
	}
}
#else
extern void flush_cache_mm(struct mm_struct *mm);
extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
#endif

/*
 * flush_cache_user_range is used when we want to ensure that the
 * Harvard caches are synchronised for the user space address range.
 * This is used for the ARM private sys_cacheflush system call.
 */
#define flush_cache_user_range(vma,start,end) \
	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))

/*
 * Perform necessary cache operations to ensure that data previously
 * stored within this range of addresses can be executed by the CPU.
 */
#define flush_icache_range(s,e)		__cpuc_coherent_kern_range(s,e)

/*
 * Perform necessary cache operations to ensure that the TLB will
 * see data written in the specified area.
 */
#define clean_dcache_area(start,size)	cpu_dcache_clean_area(start, size)

/*
 * flush_dcache_page is used when the kernel has written to the page
 * cache page at virtual address page->virtual.
 *
 * If this page isn't mapped (ie, page_mapping == NULL), or it might
 * have userspace mappings, then we _must_ always clean + invalidate
 * the dcache entries associated with the kernel mapping.
 *
 * Otherwise we can defer the operation, and clean the cache when we are
 * about to change to user space.  This is the same method as used on SPARC64.
 * See update_mmu_cache for the user space part.
 */
extern void flush_dcache_page(struct page *);

#define flush_dcache_mmap_lock(mapping) \
	write_lock_irq(&(mapping)->tree_lock)
#define flush_dcache_mmap_unlock(mapping) \
	write_unlock_irq(&(mapping)->tree_lock)

#define flush_icache_user_range(vma,page,addr,len) \
	flush_dcache_page(page)

/*
 * We don't appear to need to do anything here.  In fact, if we did, we'd
 * duplicate cache flushing elsewhere performed by flush_dcache_page().
 */
#define flush_icache_page(vma,page)	do { } while (0)

#define __cacheid_present(val)		(val != read_cpuid(CPUID_ID))
#define __cacheid_vivt(val)		((val & (15 << 25)) != (14 << 25))
#define __cacheid_vipt(val)		((val & (15 << 25)) == (14 << 25))
#define __cacheid_vipt_nonaliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))
#define __cacheid_vipt_aliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))

#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)

#define cache_is_vivt()			1
#define cache_is_vipt()			0
#define cache_is_vipt_nonaliasing()	0
#define cache_is_vipt_aliasing()	0

#elif defined(CONFIG_CPU_CACHE_VIPT)

#define cache_is_vivt()			0
#define cache_is_vipt()			1
#define cache_is_vipt_nonaliasing()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_vipt_nonaliasing(__val);			\
	})

#define cache_is_vipt_aliasing()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_vipt_aliasing(__val);				\
	})

#else

#define cache_is_vivt()							\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		(!__cacheid_present(__val)) || __cacheid_vivt(__val);	\
	})
		
#define cache_is_vipt()							\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_present(__val) && __cacheid_vipt(__val);	\
	})

#define cache_is_vipt_nonaliasing()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_present(__val) &&				\
		 __cacheid_vipt_nonaliasing(__val);			\
	})

#define cache_is_vipt_aliasing()					\
	({								\
		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
		__cacheid_present(__val) &&				\
		 __cacheid_vipt_aliasing(__val);			\
	})

#endif

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-arm/cacheflush.h
	3	*
	4	* Copyright (C) 1999-2002 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef _ASMARM_CACHEFLUSH_H
	11	#define _ASMARM_CACHEFLUSH_H
	12
1da177e4 LT	13	#include <linux/sched.h>
	14	#include <linux/mm.h>
	15
1da177e4	16	#include <asm/glue.h>
b8a9b66f RK	17	#include <asm/shmparam.h>
	18
	19	#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
1da177e4 LT	20
	21	/*
	22	* Cache Model
	23	* ===========
	24	*/
	25	#undef _CACHE
	26	#undef MULTI_CACHE
	27
	28	#if defined(CONFIG_CPU_ARM610) \|\| defined(CONFIG_CPU_ARM710)
	29	# ifdef _CACHE
	30	# define MULTI_CACHE 1
	31	# else
	32	# define _CACHE v3
	33	# endif
	34	#endif
	35
	36	#if defined(CONFIG_CPU_ARM720T)
	37	# ifdef _CACHE
	38	# define MULTI_CACHE 1
	39	# else
	40	# define _CACHE v4
	41	# endif
	42	#endif
	43
	44	#if defined(CONFIG_CPU_ARM920T) \|\| defined(CONFIG_CPU_ARM922T) \|\| \
	45	defined(CONFIG_CPU_ARM925T) \|\| defined(CONFIG_CPU_ARM1020)
	46	# define MULTI_CACHE 1
	47	#endif
	48
	49	#if defined(CONFIG_CPU_ARM926T)
	50	# ifdef _CACHE
	51	# define MULTI_CACHE 1
	52	# else
	53	# define _CACHE arm926
	54	# endif
	55	#endif
	56
	57	#if defined(CONFIG_CPU_SA110) \|\| defined(CONFIG_CPU_SA1100)
	58	# ifdef _CACHE
	59	# define MULTI_CACHE 1
	60	# else
	61	# define _CACHE v4wb
	62	# endif
	63	#endif
	64
	65	#if defined(CONFIG_CPU_XSCALE)
	66	# ifdef _CACHE
	67	# define MULTI_CACHE 1
	68	# else
	69	# define _CACHE xscale
	70	# endif
	71	#endif
	72
23bdf86a LB	73	#if defined(CONFIG_CPU_XSC3)
	74	# ifdef _CACHE
	75	# define MULTI_CACHE 1
	76	# else
	77	# define _CACHE xsc3
	78	# endif
	79	#endif
	80
1da177e4 LT	81	#if defined(CONFIG_CPU_V6)
	82	//# ifdef _CACHE
	83	# define MULTI_CACHE 1
	84	//# else
	85	//# define _CACHE v6
	86	//# endif
	87	#endif
	88
	89	#if !defined(_CACHE) && !defined(MULTI_CACHE)
	90	#error Unknown cache maintainence model
	91	#endif
	92
	93	/*
	94	* This flag is used to indicate that the page pointed to by a pte
	95	* is dirty and requires cleaning before returning it to the user.
	96	*/
	97	#define PG_dcache_dirty PG_arch_1
	98
	99	/*
	100	* MM Cache Management
	101	* ===================
	102	*
	103	* The arch/arm/mm/cache-.S and arch/arm/mm/proc-.S files
	104	* implement these methods.
	105	*
	106	* Start addresses are inclusive and end addresses are exclusive;
	107	* start addresses should be rounded down, end addresses up.
	108	*
	109	* See Documentation/cachetlb.txt for more information.
	110	* Please note that the implementation of these, and the required
	111	* effects are cache-type (VIVT/VIPT/PIPT) specific.
	112	*
	113	* flush_cache_kern_all()
	114	*
	115	* Unconditionally clean and invalidate the entire cache.
	116	*
	117	* flush_cache_user_mm(mm)
	118	*
	119	* Clean and invalidate all user space cache entries
	120	* before a change of page tables.
	121	*
	122	* flush_cache_user_range(start, end, flags)
	123	*
	124	* Clean and invalidate a range of cache entries in the
	125	* specified address space before a change of page tables.
	126	* - start - user start address (inclusive, page aligned)
	127	* - end - user end address (exclusive, page aligned)
	128	* - flags - vma->vm_flags field
	129	*
	130	* coherent_kern_range(start, end)
	131	*
	132	* Ensure coherency between the Icache and the Dcache in the
	133	* region described by start, end. If you have non-snooping
	134	* Harvard caches, you need to implement this function.
	135	* - start - virtual start address
	136	* - end - virtual end address
	137	*
	138	* DMA Cache Coherency
	139	* ===================
	140	*
	141	* dma_inv_range(start, end)
	142	*
	143	* Invalidate (discard) the specified virtual address range.
	144	* May not write back any entries. If 'start' or 'end'
145	* are not cache line aligned, those lines must be written
146	* back.
147	* - start - virtual start address
148	* - end - virtual end address
149	*
150	* dma_clean_range(start, end)
151	*
152	* Clean (write back) the specified virtual address range.
153	* - start - virtual start address
154	* - end - virtual end address
155	*
156	* dma_flush_range(start, end)
157	*
158	* Clean and invalidate the specified virtual address range.
159	* - start - virtual start address
160	* - end - virtual end address
161	*/
162
163	struct cpu_cache_fns {
164	void (*flush_kern_all)(void);
165	void (*flush_user_all)(void);
166	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
167
168	void (*coherent_kern_range)(unsigned long, unsigned long);
169	void (*coherent_user_range)(unsigned long, unsigned long);
170	void (flush_kern_dcache_page)(void );
171
172	void (*dma_inv_range)(unsigned long, unsigned long);
173	void (*dma_clean_range)(unsigned long, unsigned long);
174	void (*dma_flush_range)(unsigned long, unsigned long);
175	};
176
177	/*
178	* Select the calling method
179	*/
180	#ifdef MULTI_CACHE
181
182	extern struct cpu_cache_fns cpu_cache;
183
184	#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
185	#define __cpuc_flush_user_all cpu_cache.flush_user_all
186	#define __cpuc_flush_user_range cpu_cache.flush_user_range
187	#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
188	#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
189	#define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page
190
191	/*
192	* These are private to the dma-mapping API. Do not use directly.
193	* Their sole purpose is to ensure that data held in the cache
194	* is visible to DMA, or data written by DMA to system memory is
195	* visible to the CPU.
196	*/
197	#define dmac_inv_range cpu_cache.dma_inv_range
198	#define dmac_clean_range cpu_cache.dma_clean_range
199	#define dmac_flush_range cpu_cache.dma_flush_range
200
201	#else
202
203	#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
204	#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
205	#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
206	#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
207	#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
208	#define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page)
209
210	extern void __cpuc_flush_kern_all(void);
211	extern void __cpuc_flush_user_all(void);
212	extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
213	extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
214	extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
215	extern void __cpuc_flush_dcache_page(void *);
216
217	/*
218	* These are private to the dma-mapping API. Do not use directly.
219	* Their sole purpose is to ensure that data held in the cache
220	* is visible to DMA, or data written by DMA to system memory is
221	* visible to the CPU.
222	*/
223	#define dmac_inv_range __glue(_CACHE,_dma_inv_range)
224	#define dmac_clean_range __glue(_CACHE,_dma_clean_range)
225	#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
226
227	extern void dmac_inv_range(unsigned long, unsigned long);
228	extern void dmac_clean_range(unsigned long, unsigned long);
229	extern void dmac_flush_range(unsigned long, unsigned long);
230
231	#endif
232
233	/*
234	* flush_cache_vmap() is used when creating mappings (eg, via vmap,
235	* vmalloc, ioremap etc) in kernel space for pages. Since the
236	* direct-mappings of these pages may contain cached data, we need
237	* to do a full cache flush to ensure that writebacks don't corrupt
238	* data placed into these pages via the new mappings.
239	*/
240	#define flush_cache_vmap(start, end) flush_cache_all()
241	#define flush_cache_vunmap(start, end) flush_cache_all()
242
243	/*
244	* Copy user data from/to a page which is mapped into a different
245	* processes address space. Really, we want to allow our "user
246	* space" model to handle this.
247	*/
248	#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
249	do { \
250	flush_cache_page(vma, vaddr, page_to_pfn(page));\
251	memcpy(dst, src, len); \
252	flush_dcache_page(page); \
253	} while (0)
254
255	#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
256	do { \
257	flush_cache_page(vma, vaddr, page_to_pfn(page));\
258	memcpy(dst, src, len); \
259	} while (0)
260
261	/*
262	* Convert calls to our calling convention.
263	*/
264	#define flush_cache_all() __cpuc_flush_kern_all()
d7b6b358	265	#ifndef CONFIG_CPU_CACHE_VIPT
1da177e4 LT	266	static inline void flush_cache_mm(struct mm_struct *mm)
	267	{
	268	if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
	269	__cpuc_flush_user_all();
	270	}
	271
	272	static inline void
	273	flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
	274	{
	275	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
	276	__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
	277	vma->vm_flags);
	278	}
	279
	280	static inline void
	281	flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
	282	{
	283	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
	284	unsigned long addr = user_addr & PAGE_MASK;
	285	__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
	286	}
	287	}
d7b6b358 RK	288	#else
	289	extern void flush_cache_mm(struct mm_struct *mm);
	290	extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
	291	extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
	292	#endif
1da177e4 LT	293
	294	/*
	295	* flush_cache_user_range is used when we want to ensure that the
	296	* Harvard caches are synchronised for the user space address range.
	297	* This is used for the ARM private sys_cacheflush system call.
	298	*/
	299	#define flush_cache_user_range(vma,start,end) \
	300	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
	301
	302	/*
	303	* Perform necessary cache operations to ensure that data previously
	304	* stored within this range of addresses can be executed by the CPU.
	305	*/
	306	#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
	307
	308	/*
	309	* Perform necessary cache operations to ensure that the TLB will
	310	* see data written in the specified area.
	311	*/
	312	#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
	313
	314	/*
	315	* flush_dcache_page is used when the kernel has written to the page
	316	* cache page at virtual address page->virtual.
	317	*
	318	* If this page isn't mapped (ie, page_mapping == NULL), or it might
	319	* have userspace mappings, then we _must_ always clean + invalidate
	320	* the dcache entries associated with the kernel mapping.
	321	*
	322	* Otherwise we can defer the operation, and clean the cache when we are
	323	* about to change to user space. This is the same method as used on SPARC64.
	324	* See update_mmu_cache for the user space part.
	325	*/
	326	extern void flush_dcache_page(struct page *);
	327
	328	#define flush_dcache_mmap_lock(mapping) \
	329	write_lock_irq(&(mapping)->tree_lock)
	330	#define flush_dcache_mmap_unlock(mapping) \
	331	write_unlock_irq(&(mapping)->tree_lock)
	332
	333	#define flush_icache_user_range(vma,page,addr,len) \
	334	flush_dcache_page(page)
	335
	336	/*
	337	* We don't appear to need to do anything here. In fact, if we did, we'd
	338	* duplicate cache flushing elsewhere performed by flush_dcache_page().
	339	*/
	340	#define flush_icache_page(vma,page) do { } while (0)
	341
	342	#define __cacheid_present(val) (val != read_cpuid(CPUID_ID))
	343	#define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25))
	344	#define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25))
	345	#define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 \| 1 << 23)) == (14 << 25))
	346	#define __cacheid_vipt_aliasing(val) ((val & (15 << 25 \| 1 << 23)) == (14 << 25 \| 1 << 23))
	347
	348	#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
	349
	350	#define cache_is_vivt() 1
	351	#define cache_is_vipt() 0
	352	#define cache_is_vipt_nonaliasing() 0
	353	#define cache_is_vipt_aliasing() 0
	354
	355	#elif defined(CONFIG_CPU_CACHE_VIPT)
	356
357	#define cache_is_vivt() 0
358	#define cache_is_vipt() 1
359	#define cache_is_vipt_nonaliasing() \
360	({ \
361	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
362	__cacheid_vipt_nonaliasing(__val); \
363	})
364
365	#define cache_is_vipt_aliasing() \
366	({ \
367	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
368	__cacheid_vipt_aliasing(__val); \
369	})
370
371	#else
372
373	#define cache_is_vivt() \
374	({ \
375	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
376	(!__cacheid_present(__val)) \|\| __cacheid_vivt(__val); \
377	})
378
379	#define cache_is_vipt() \
380	({ \
381	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
382	__cacheid_present(__val) && __cacheid_vipt(__val); \
383	})
384
385	#define cache_is_vipt_nonaliasing() \
386	({ \
387	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
388	__cacheid_present(__val) && \
389	__cacheid_vipt_nonaliasing(__val); \
390	})
391
392	#define cache_is_vipt_aliasing() \
393	({ \
394	unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
395	__cacheid_present(__val) && \
396	__cacheid_vipt_aliasing(__val); \
397	})
398
399	#endif
400
401	#endif