projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a09e64fb | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-iic.h |
| 1da177e4 LT |
2 | * |
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * S3C2410 I2C Controller | |
| 1da177e4 LT |
11 | */ |
| 12 | ||
| 13 | #ifndef __ASM_ARCH_REGS_IIC_H | |
| 14 | #define __ASM_ARCH_REGS_IIC_H __FILE__ | |
| 15 | ||
| 16 | /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ | |
| 17 | ||
| 18 | #define S3C2410_IICREG(x) (x) | |
| 19 | ||
| 20 | #define S3C2410_IICCON S3C2410_IICREG(0x00) | |
| 21 | #define S3C2410_IICSTAT S3C2410_IICREG(0x04) | |
| 22 | #define S3C2410_IICADD S3C2410_IICREG(0x08) | |
| 23 | #define S3C2410_IICDS S3C2410_IICREG(0x0C) | |
| 24 | #define S3C2440_IICLC S3C2410_IICREG(0x10) | |
| 25 | ||
| 26 | #define S3C2410_IICCON_ACKEN (1<<7) | |
| 27 | #define S3C2410_IICCON_TXDIV_16 (0<<6) | |
| 28 | #define S3C2410_IICCON_TXDIV_512 (1<<6) | |
| 29 | #define S3C2410_IICCON_IRQEN (1<<5) | |
| 30 | #define S3C2410_IICCON_IRQPEND (1<<4) | |
| 31 | #define S3C2410_IICCON_SCALE(x) ((x)&15) | |
| 32 | #define S3C2410_IICCON_SCALEMASK (0xf) | |
| 33 | ||
| 34 | #define S3C2410_IICSTAT_MASTER_RX (2<<6) | |
| 35 | #define S3C2410_IICSTAT_MASTER_TX (3<<6) | |
| 36 | #define S3C2410_IICSTAT_SLAVE_RX (0<<6) | |
| 37 | #define S3C2410_IICSTAT_SLAVE_TX (1<<6) | |
| 38 | #define S3C2410_IICSTAT_MODEMASK (3<<6) | |
| 39 | ||
| 40 | #define S3C2410_IICSTAT_START (1<<5) | |
| 41 | #define S3C2410_IICSTAT_BUSBUSY (1<<5) | |
| 42 | #define S3C2410_IICSTAT_TXRXEN (1<<4) | |
| 43 | #define S3C2410_IICSTAT_ARBITR (1<<3) | |
| 44 | #define S3C2410_IICSTAT_ASSLAVE (1<<2) | |
| 45 | #define S3C2410_IICSTAT_ADDR0 (1<<1) | |
| 46 | #define S3C2410_IICSTAT_LASTBIT (1<<0) | |
| 47 | ||
| 48 | #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) | |
| 49 | #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) | |
| 50 | #define S3C2410_IICLC_SDA_DELAY10 (2 << 0) | |
| 51 | #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) | |
| 52 | #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) | |
| 53 | ||
| 54 | #define S3C2410_IICLC_FILTER_ON (1<<2) | |
| 55 | ||
| 56 | #endif /* __ASM_ARCH_REGS_IIC_H */ |