[deliverable/linux.git] / include / asm-arm / tlbflush.h

/*
 *  linux/include/asm-arm/tlbflush.h
 *
 *  Copyright (C) 1999-2003 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ASMARM_TLBFLUSH_H
#define _ASMARM_TLBFLUSH_H


#ifndef CONFIG_MMU

#define tlb_flush(tlb)	((void) tlb)

#else /* CONFIG_MMU */

#include <asm/glue.h>

#define TLB_V3_PAGE	(1 << 0)
#define TLB_V4_U_PAGE	(1 << 1)
#define TLB_V4_D_PAGE	(1 << 2)
#define TLB_V4_I_PAGE	(1 << 3)
#define TLB_V6_U_PAGE	(1 << 4)
#define TLB_V6_D_PAGE	(1 << 5)
#define TLB_V6_I_PAGE	(1 << 6)

#define TLB_V3_FULL	(1 << 8)
#define TLB_V4_U_FULL	(1 << 9)
#define TLB_V4_D_FULL	(1 << 10)
#define TLB_V4_I_FULL	(1 << 11)
#define TLB_V6_U_FULL	(1 << 12)
#define TLB_V6_D_FULL	(1 << 13)
#define TLB_V6_I_FULL	(1 << 14)

#define TLB_V6_U_ASID	(1 << 16)
#define TLB_V6_D_ASID	(1 << 17)
#define TLB_V6_I_ASID	(1 << 18)

#define TLB_DCLEAN	(1 << 30)
#define TLB_WB		(1 << 31)

/*
 *	MMU TLB Model
 *	=============
 *
 *	We have the following to choose from:
 *	  v3    - ARMv3
 *	  v4    - ARMv4 without write buffer
 *	  v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
 *	  v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
 *	  v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
 */
#undef _TLB
#undef MULTI_TLB

#define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)

#ifdef CONFIG_CPU_TLB_V3
# define v3_possible_flags	v3_tlb_flags
# define v3_always_flags	v3_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v3
# endif
#else
# define v3_possible_flags	0
# define v3_always_flags	(-1UL)
#endif

#define v4_tlb_flags	(TLB_V4_U_FULL | TLB_V4_U_PAGE)

#ifdef CONFIG_CPU_TLB_V4WT
# define v4_possible_flags	v4_tlb_flags
# define v4_always_flags	v4_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4
# endif
#else
# define v4_possible_flags	0
# define v4_always_flags	(-1UL)
#endif

#define v4wbi_tlb_flags	(TLB_WB | TLB_DCLEAN | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_V4WBI
# define v4wbi_possible_flags	v4wbi_tlb_flags
# define v4wbi_always_flags	v4wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wbi
# endif
#else
# define v4wbi_possible_flags	0
# define v4wbi_always_flags	(-1UL)
#endif

#define v4wb_tlb_flags	(TLB_WB | TLB_DCLEAN | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_V4WB
# define v4wb_possible_flags	v4wb_tlb_flags
# define v4wb_always_flags	v4wb_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wb
# endif
#else
# define v4wb_possible_flags	0
# define v4wb_always_flags	(-1UL)
#endif

#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
			 TLB_V6_I_FULL | TLB_V6_D_FULL | \
			 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
			 TLB_V6_I_ASID | TLB_V6_D_ASID)

#ifdef CONFIG_CPU_TLB_V6
# define v6wbi_possible_flags	v6wbi_tlb_flags
# define v6wbi_always_flags	v6wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v6wbi
# endif
#else
# define v6wbi_possible_flags	0
# define v6wbi_always_flags	(-1UL)
#endif

#ifdef CONFIG_CPU_TLB_V7
# define v7wbi_possible_flags	v6wbi_tlb_flags
# define v7wbi_always_flags	v6wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v7wbi
# endif
#else
# define v7wbi_possible_flags	0
# define v7wbi_always_flags	(-1UL)
#endif

#ifndef _TLB
#error Unknown TLB model
#endif

#ifndef __ASSEMBLY__

#include <linux/sched.h>

struct cpu_tlb_fns {
	void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
	void (*flush_kern_range)(unsigned long, unsigned long);
	unsigned long tlb_flags;
};

/*
 * Select the calling method
 */
#ifdef MULTI_TLB

#define __cpu_flush_user_tlb_range	cpu_tlb.flush_user_range
#define __cpu_flush_kern_tlb_range	cpu_tlb.flush_kern_range

#else

#define __cpu_flush_user_tlb_range	__glue(_TLB,_flush_user_tlb_range)
#define __cpu_flush_kern_tlb_range	__glue(_TLB,_flush_kern_tlb_range)

extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);

#endif

extern struct cpu_tlb_fns cpu_tlb;

#define __cpu_tlb_flags			cpu_tlb.tlb_flags

/*
 *	TLB Management
 *	==============
 *
 *	The arch/arm/mm/tlb-*.S files implement these methods.
 *
 *	The TLB specific code is expected to perform whatever tests it
 *	needs to determine if it should invalidate the TLB for each
 *	call.  Start addresses are inclusive and end addresses are
 *	exclusive; it is safe to round these addresses down.
 *
 *	flush_tlb_all()
 *
 *		Invalidate the entire TLB.
 *
 *	flush_tlb_mm(mm)
 *
 *		Invalidate all TLB entries in a particular address
 *		space.
 *		- mm	- mm_struct describing address space
 *
 *	flush_tlb_range(mm,start,end)
 *
 *		Invalidate a range of TLB entries in the specified
 *		address space.
 *		- mm	- mm_struct describing address space
 *		- start - start address (may not be aligned)
 *		- end	- end address (exclusive, may not be aligned)
 *
 *	flush_tlb_page(vaddr,vma)
 *
 *		Invalidate the specified page in the specified address range.
 *		- vaddr - virtual address (may not be aligned)
 *		- vma	- vma_struct describing address range
 *
 *	flush_kern_tlb_page(kaddr)
 *
 *		Invalidate the TLB entry for the specified page.  The address
 *		will be in the kernels virtual memory space.  Current uses
 *		only require the D-TLB to be invalidated.
 *		- kaddr - Kernel virtual memory address
 */

/*
 * We optimise the code below by:
 *  - building a set of TLB flags that might be set in __cpu_tlb_flags
 *  - building a set of TLB flags that will always be set in __cpu_tlb_flags
 *  - if we're going to need __cpu_tlb_flags, access it once and only once
 *
 * This allows us to build optimal assembly for the single-CPU type case,
 * and as close to optimal given the compiler constrants for multi-CPU
 * case.  We could do better for the multi-CPU case if the compiler
 * implemented the "%?" method, but this has been discontinued due to too
 * many people getting it wrong.
 */
#define possible_tlb_flags	(v3_possible_flags | \
				 v4_possible_flags | \
				 v4wbi_possible_flags | \
				 v4wb_possible_flags | \
				 v6wbi_possible_flags)

#define always_tlb_flags	(v3_always_flags & \
				 v4_always_flags & \
				 v4wbi_always_flags & \
				 v4wb_always_flags & \
				 v6wbi_always_flags)

#define tlb_flag(f)	((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))

static inline void local_flush_tlb_all(void)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_WB))
		dsb();

	if (tlb_flag(TLB_V3_FULL))
		asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
	if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
		asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
	if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
		asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
	if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
		asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");

	if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
		     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
		     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
		/* flush the branch target cache */
		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
		dsb();
		isb();
	}
}

static inline void local_flush_tlb_mm(struct mm_struct *mm)
{
	const int zero = 0;
	const int asid = ASID(mm);
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_WB))
		dsb();

	if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
		if (tlb_flag(TLB_V3_FULL))
			asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
		if (tlb_flag(TLB_V4_U_FULL))
			asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
		if (tlb_flag(TLB_V4_D_FULL))
			asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
		if (tlb_flag(TLB_V4_I_FULL))
			asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
	}

	if (tlb_flag(TLB_V6_U_ASID))
		asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
	if (tlb_flag(TLB_V6_D_ASID))
		asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
	if (tlb_flag(TLB_V6_I_ASID))
		asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");

	if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
		     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
		     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
		/* flush the branch target cache */
		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
		dsb();
	}
}

static inline void
local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);

	if (tlb_flag(TLB_WB))
		dsb();

	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
		if (tlb_flag(TLB_V3_PAGE))
			asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
		if (tlb_flag(TLB_V4_U_PAGE))
			asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
		if (tlb_flag(TLB_V4_D_PAGE))
			asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
		if (tlb_flag(TLB_V4_I_PAGE))
			asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
		if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
			asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
	}

	if (tlb_flag(TLB_V6_U_PAGE))
		asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
	if (tlb_flag(TLB_V6_D_PAGE))
		asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
	if (tlb_flag(TLB_V6_I_PAGE))
		asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");

	if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
		     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
		     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
		/* flush the branch target cache */
		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
		dsb();
	}
}

static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	kaddr &= PAGE_MASK;

	if (tlb_flag(TLB_WB))
		dsb();

	if (tlb_flag(TLB_V3_PAGE))
		asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V4_U_PAGE))
		asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V4_D_PAGE))
		asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V4_I_PAGE))
		asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
		asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");

	if (tlb_flag(TLB_V6_U_PAGE))
		asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V6_D_PAGE))
		asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V6_I_PAGE))
		asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");

	if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
		     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
		     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
		/* flush the branch target cache */
		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
		dsb();
		isb();
	}
}

/*
 *	flush_pmd_entry
 *
 *	Flush a PMD entry (word aligned, or double-word aligned) to
 *	RAM if the TLB for the CPU we are running on requires this.
 *	This is typically used when we are creating PMD entries.
 *
 *	clean_pmd_entry
 *
 *	Clean (but don't drain the write buffer) if the CPU requires
 *	these operations.  This is typically used when we are removing
 *	PMD entries.
 */
static inline void flush_pmd_entry(pmd_t *pmd)
{
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_DCLEAN))
		asm("mcr	p15, 0, %0, c7, c10, 1	@ flush_pmd"
			: : "r" (pmd) : "cc");
	if (tlb_flag(TLB_WB))
		dsb();
}

static inline void clean_pmd_entry(pmd_t *pmd)
{
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_DCLEAN))
		asm("mcr	p15, 0, %0, c7, c10, 1	@ flush_pmd"
			: : "r" (pmd) : "cc");
}

#undef tlb_flag
#undef always_tlb_flags
#undef possible_tlb_flags

/*
 * Convert calls to our calling convention.
 */
#define local_flush_tlb_range(vma,start,end)	__cpu_flush_user_tlb_range(start,end,vma)
#define local_flush_tlb_kernel_range(s,e)	__cpu_flush_kern_tlb_range(s,e)

#ifndef CONFIG_SMP
#define flush_tlb_all		local_flush_tlb_all
#define flush_tlb_mm		local_flush_tlb_mm
#define flush_tlb_page		local_flush_tlb_page
#define flush_tlb_kernel_page	local_flush_tlb_kernel_page
#define flush_tlb_range		local_flush_tlb_range
#define flush_tlb_kernel_range	local_flush_tlb_kernel_range
#else
extern void flush_tlb_all(void);
extern void flush_tlb_mm(struct mm_struct *mm);
extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
extern void flush_tlb_kernel_page(unsigned long kaddr);
extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
#endif

/*
 * if PG_dcache_dirty is set for the page, we need to ensure that any
 * cache entries for the kernels virtual memory range are written
 * back to the page.
 */
extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);

#endif

#endif /* CONFIG_MMU */

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-arm/tlbflush.h
	3	*
	4	* Copyright (C) 1999-2003 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef _ASMARM_TLBFLUSH_H
	11	#define _ASMARM_TLBFLUSH_H
	12
0157903e HC	13
	14	#ifndef CONFIG_MMU
	15
	16	#define tlb_flush(tlb) ((void) tlb)
	17
fb1c7762	18	#else /* CONFIG_MMU */
0157903e	19
1da177e4 LT	20	#include <asm/glue.h>
	21
	22	#define TLB_V3_PAGE (1 << 0)
	23	#define TLB_V4_U_PAGE (1 << 1)
	24	#define TLB_V4_D_PAGE (1 << 2)
	25	#define TLB_V4_I_PAGE (1 << 3)
	26	#define TLB_V6_U_PAGE (1 << 4)
	27	#define TLB_V6_D_PAGE (1 << 5)
	28	#define TLB_V6_I_PAGE (1 << 6)
	29
	30	#define TLB_V3_FULL (1 << 8)
	31	#define TLB_V4_U_FULL (1 << 9)
	32	#define TLB_V4_D_FULL (1 << 10)
	33	#define TLB_V4_I_FULL (1 << 11)
	34	#define TLB_V6_U_FULL (1 << 12)
	35	#define TLB_V6_D_FULL (1 << 13)
	36	#define TLB_V6_I_FULL (1 << 14)
	37
	38	#define TLB_V6_U_ASID (1 << 16)
	39	#define TLB_V6_D_ASID (1 << 17)
	40	#define TLB_V6_I_ASID (1 << 18)
	41
	42	#define TLB_DCLEAN (1 << 30)
	43	#define TLB_WB (1 << 31)
	44
	45	/*
	46	* MMU TLB Model
	47	* =============
	48	*
	49	* We have the following to choose from:
	50	* v3 - ARMv3
	51	* v4 - ARMv4 without write buffer
	52	* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
	53	* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
	54	* v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
	55	*/
	56	#undef _TLB
	57	#undef MULTI_TLB
	58
	59	#define v3_tlb_flags (TLB_V3_FULL \| TLB_V3_PAGE)
	60
	61	#ifdef CONFIG_CPU_TLB_V3
	62	# define v3_possible_flags v3_tlb_flags
	63	# define v3_always_flags v3_tlb_flags
	64	# ifdef _TLB
	65	# define MULTI_TLB 1
	66	# else
	67	# define _TLB v3
	68	# endif
	69	#else
	70	# define v3_possible_flags 0
	71	# define v3_always_flags (-1UL)
	72	#endif
	73
	74	#define v4_tlb_flags (TLB_V4_U_FULL \| TLB_V4_U_PAGE)
	75
	76	#ifdef CONFIG_CPU_TLB_V4WT
	77	# define v4_possible_flags v4_tlb_flags
	78	# define v4_always_flags v4_tlb_flags
	79	# ifdef _TLB
	80	# define MULTI_TLB 1
	81	# else
	82	# define _TLB v4
	83	# endif
84	#else
85	# define v4_possible_flags 0
86	# define v4_always_flags (-1UL)
87	#endif
88
89	#define v4wbi_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
90	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
91	TLB_V4_I_PAGE \| TLB_V4_D_PAGE)
92
93	#ifdef CONFIG_CPU_TLB_V4WBI
94	# define v4wbi_possible_flags v4wbi_tlb_flags
95	# define v4wbi_always_flags v4wbi_tlb_flags
96	# ifdef _TLB
97	# define MULTI_TLB 1
98	# else
99	# define _TLB v4wbi
100	# endif
101	#else
102	# define v4wbi_possible_flags 0
103	# define v4wbi_always_flags (-1UL)
104	#endif
105
106	#define v4wb_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
107	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
108	TLB_V4_D_PAGE)
109
110	#ifdef CONFIG_CPU_TLB_V4WB
111	# define v4wb_possible_flags v4wb_tlb_flags
112	# define v4wb_always_flags v4wb_tlb_flags
113	# ifdef _TLB
114	# define MULTI_TLB 1
115	# else
116	# define _TLB v4wb
117	# endif
118	#else
119	# define v4wb_possible_flags 0
120	# define v4wb_always_flags (-1UL)
121	#endif
122
123	#define v6wbi_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
124	TLB_V6_I_FULL \| TLB_V6_D_FULL \| \
125	TLB_V6_I_PAGE \| TLB_V6_D_PAGE \| \
126	TLB_V6_I_ASID \| TLB_V6_D_ASID)
127
128	#ifdef CONFIG_CPU_TLB_V6
129	# define v6wbi_possible_flags v6wbi_tlb_flags
130	# define v6wbi_always_flags v6wbi_tlb_flags
131	# ifdef _TLB
132	# define MULTI_TLB 1
133	# else
134	# define _TLB v6wbi
135	# endif
136	#else
137	# define v6wbi_possible_flags 0
138	# define v6wbi_always_flags (-1UL)
139	#endif
140
2ccdd1e7 CM	141	#ifdef CONFIG_CPU_TLB_V7
	142	# define v7wbi_possible_flags v6wbi_tlb_flags
	143	# define v7wbi_always_flags v6wbi_tlb_flags
	144	# ifdef _TLB
	145	# define MULTI_TLB 1
	146	# else
	147	# define _TLB v7wbi
	148	# endif
	149	#else
	150	# define v7wbi_possible_flags 0
	151	# define v7wbi_always_flags (-1UL)
	152	#endif
	153
1da177e4 LT	154	#ifndef _TLB
	155	#error Unknown TLB model
	156	#endif
	157
	158	#ifndef __ASSEMBLY__
	159
e8edc6e0 AD	160	#include <linux/sched.h>
e8edc6e0 AD	161
1da177e4 LT	162	struct cpu_tlb_fns {
	163	void (flush_user_range)(unsigned long, unsigned long, struct vm_area_struct );
	164	void (*flush_kern_range)(unsigned long, unsigned long);
	165	unsigned long tlb_flags;
	166	};
	167
	168	/*
	169	* Select the calling method
	170	*/
	171	#ifdef MULTI_TLB
	172
	173	#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
	174	#define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
	175
	176	#else
	177
	178	#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
	179	#define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
	180
	181	extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
	182	extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
	183
	184	#endif
	185
	186	extern struct cpu_tlb_fns cpu_tlb;
	187
	188	#define __cpu_tlb_flags cpu_tlb.tlb_flags
	189
	190	/*
	191	* TLB Management
	192	* ==============
	193	*
	194	* The arch/arm/mm/tlb-*.S files implement these methods.
	195	*
	196	* The TLB specific code is expected to perform whatever tests it
	197	* needs to determine if it should invalidate the TLB for each
	198	* call. Start addresses are inclusive and end addresses are
	199	* exclusive; it is safe to round these addresses down.
	200	*
	201	* flush_tlb_all()
	202	*
	203	* Invalidate the entire TLB.
	204	*
	205	* flush_tlb_mm(mm)
	206	*
	207	* Invalidate all TLB entries in a particular address
	208	* space.
	209	* - mm - mm_struct describing address space
	210	*
	211	* flush_tlb_range(mm,start,end)
	212	*
	213	* Invalidate a range of TLB entries in the specified
	214	* address space.
	215	* - mm - mm_struct describing address space
	216	* - start - start address (may not be aligned)
	217	* - end - end address (exclusive, may not be aligned)
	218	*
	219	* flush_tlb_page(vaddr,vma)
	220	*
	221	* Invalidate the specified page in the specified address range.
	222	* - vaddr - virtual address (may not be aligned)
	223	* - vma - vma_struct describing address range
	224	*
	225	* flush_kern_tlb_page(kaddr)
226	*
227	* Invalidate the TLB entry for the specified page. The address
228	* will be in the kernels virtual memory space. Current uses
229	* only require the D-TLB to be invalidated.
230	* - kaddr - Kernel virtual memory address
231	*/
232
233	/*
234	* We optimise the code below by:
235	* - building a set of TLB flags that might be set in __cpu_tlb_flags
236	* - building a set of TLB flags that will always be set in __cpu_tlb_flags
237	* - if we're going to need __cpu_tlb_flags, access it once and only once
238	*
239	* This allows us to build optimal assembly for the single-CPU type case,
240	* and as close to optimal given the compiler constrants for multi-CPU
241	* case. We could do better for the multi-CPU case if the compiler
242	* implemented the "%?" method, but this has been discontinued due to too
243	* many people getting it wrong.
244	*/
245	#define possible_tlb_flags (v3_possible_flags \| \
246	v4_possible_flags \| \
247	v4wbi_possible_flags \| \
248	v4wb_possible_flags \| \
249	v6wbi_possible_flags)
250
251	#define always_tlb_flags (v3_always_flags & \
252	v4_always_flags & \
253	v4wbi_always_flags & \
254	v4wb_always_flags & \
255	v6wbi_always_flags)
256
257	#define tlb_flag(f) ((always_tlb_flags & (f)) \|\| (__tlb_flag & possible_tlb_flags & (f)))
258
603fff54	259	static inline void local_flush_tlb_all(void)
1da177e4 LT	260	{
	261	const int zero = 0;
	262	const unsigned int __tlb_flag = __cpu_tlb_flags;
	263
	264	if (tlb_flag(TLB_WB))
e6a5d66f	265	dsb();
1da177e4 LT	266
1da177e4 LT	267	if (tlb_flag(TLB_V3_FULL))
6a39dd62	268	asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
1da177e4	269	if (tlb_flag(TLB_V4_U_FULL \| TLB_V6_U_FULL))
6a39dd62	270	asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
1da177e4	271	if (tlb_flag(TLB_V4_D_FULL \| TLB_V6_D_FULL))
6a39dd62	272	asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
1da177e4	273	if (tlb_flag(TLB_V4_I_FULL \| TLB_V6_I_FULL))
6a39dd62	274	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
e6a5d66f CM	275
	276	if (tlb_flag(TLB_V6_I_FULL \| TLB_V6_D_FULL \|
	277	TLB_V6_I_PAGE \| TLB_V6_D_PAGE \|
	278	TLB_V6_I_ASID \| TLB_V6_D_ASID)) {
	279	/* flush the branch target cache */
	280	asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
	281	dsb();
	282	isb();
	283	}
1da177e4 LT	284	}
1da177e4 LT	285
603fff54	286	static inline void local_flush_tlb_mm(struct mm_struct *mm)
1da177e4 LT	287	{
	288	const int zero = 0;
	289	const int asid = ASID(mm);
	290	const unsigned int __tlb_flag = __cpu_tlb_flags;
	291
	292	if (tlb_flag(TLB_WB))
e6a5d66f	293	dsb();
1da177e4 LT	294
	295	if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
	296	if (tlb_flag(TLB_V3_FULL))
6a39dd62	297	asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
1da177e4	298	if (tlb_flag(TLB_V4_U_FULL))
6a39dd62	299	asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
1da177e4	300	if (tlb_flag(TLB_V4_D_FULL))
6a39dd62	301	asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
1da177e4	302	if (tlb_flag(TLB_V4_I_FULL))
6a39dd62	303	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4 LT	304	}
	305
	306	if (tlb_flag(TLB_V6_U_ASID))
6a39dd62	307	asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
1da177e4	308	if (tlb_flag(TLB_V6_D_ASID))
6a39dd62	309	asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
1da177e4	310	if (tlb_flag(TLB_V6_I_ASID))
6a39dd62	311	asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
e6a5d66f CM	312
	313	if (tlb_flag(TLB_V6_I_FULL \| TLB_V6_D_FULL \|
	314	TLB_V6_I_PAGE \| TLB_V6_D_PAGE \|
	315	TLB_V6_I_ASID \| TLB_V6_D_ASID)) {
	316	/* flush the branch target cache */
	317	asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
	318	dsb();
	319	}
1da177e4 LT	320	}
	321
	322	static inline void
603fff54	323	local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
1da177e4 LT	324	{
	325	const int zero = 0;
	326	const unsigned int __tlb_flag = __cpu_tlb_flags;
	327
	328	uaddr = (uaddr & PAGE_MASK) \| ASID(vma->vm_mm);
	329
	330	if (tlb_flag(TLB_WB))
e6a5d66f	331	dsb();
1da177e4 LT	332
	333	if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
	334	if (tlb_flag(TLB_V3_PAGE))
6a39dd62	335	asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
1da177e4	336	if (tlb_flag(TLB_V4_U_PAGE))
6a39dd62	337	asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
1da177e4	338	if (tlb_flag(TLB_V4_D_PAGE))
6a39dd62	339	asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
1da177e4	340	if (tlb_flag(TLB_V4_I_PAGE))
6a39dd62	341	asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
1da177e4	342	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
6a39dd62	343	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4 LT	344	}
	345
	346	if (tlb_flag(TLB_V6_U_PAGE))
6a39dd62	347	asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
1da177e4	348	if (tlb_flag(TLB_V6_D_PAGE))
6a39dd62	349	asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
1da177e4	350	if (tlb_flag(TLB_V6_I_PAGE))
6a39dd62	351	asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
e6a5d66f CM	352
	353	if (tlb_flag(TLB_V6_I_FULL \| TLB_V6_D_FULL \|
	354	TLB_V6_I_PAGE \| TLB_V6_D_PAGE \|
	355	TLB_V6_I_ASID \| TLB_V6_D_ASID)) {
	356	/* flush the branch target cache */
	357	asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
	358	dsb();
	359	}
1da177e4 LT	360	}
1da177e4 LT	361
603fff54	362	static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
1da177e4 LT	363	{
	364	const int zero = 0;
	365	const unsigned int __tlb_flag = __cpu_tlb_flags;
	366
	367	kaddr &= PAGE_MASK;
	368
	369	if (tlb_flag(TLB_WB))
e6a5d66f	370	dsb();
1da177e4 LT	371
1da177e4 LT	372	if (tlb_flag(TLB_V3_PAGE))
6a39dd62	373	asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
1da177e4	374	if (tlb_flag(TLB_V4_U_PAGE))
6a39dd62	375	asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
1da177e4	376	if (tlb_flag(TLB_V4_D_PAGE))
6a39dd62	377	asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
1da177e4	378	if (tlb_flag(TLB_V4_I_PAGE))
6a39dd62	379	asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
1da177e4	380	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
6a39dd62	381	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4 LT	382
1da177e4 LT	383	if (tlb_flag(TLB_V6_U_PAGE))
6a39dd62	384	asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
1da177e4	385	if (tlb_flag(TLB_V6_D_PAGE))
6a39dd62	386	asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
1da177e4	387	if (tlb_flag(TLB_V6_I_PAGE))
6a39dd62	388	asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
6a0e2430	389
e6a5d66f CM	390	if (tlb_flag(TLB_V6_I_FULL \| TLB_V6_D_FULL \|
	391	TLB_V6_I_PAGE \| TLB_V6_D_PAGE \|
	392	TLB_V6_I_ASID \| TLB_V6_D_ASID)) {
	393	/* flush the branch target cache */
	394	asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
	395	dsb();
	396	isb();
	397	}
1da177e4 LT	398	}
	399
	400	/*
	401	* flush_pmd_entry
	402	*
	403	* Flush a PMD entry (word aligned, or double-word aligned) to
	404	* RAM if the TLB for the CPU we are running on requires this.
	405	* This is typically used when we are creating PMD entries.
	406	*
	407	* clean_pmd_entry
	408	*
	409	* Clean (but don't drain the write buffer) if the CPU requires
	410	* these operations. This is typically used when we are removing
	411	* PMD entries.
	412	*/
	413	static inline void flush_pmd_entry(pmd_t *pmd)
	414	{
1da177e4 LT	415	const unsigned int __tlb_flag = __cpu_tlb_flags;
	416
	417	if (tlb_flag(TLB_DCLEAN))
6a39dd62 DJ	418	asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
6a39dd62 DJ	419	: : "r" (pmd) : "cc");
1da177e4	420	if (tlb_flag(TLB_WB))
e6a5d66f	421	dsb();
1da177e4 LT	422	}
	423
	424	static inline void clean_pmd_entry(pmd_t *pmd)
	425	{
	426	const unsigned int __tlb_flag = __cpu_tlb_flags;
	427
	428	if (tlb_flag(TLB_DCLEAN))
6a39dd62 DJ	429	asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
6a39dd62 DJ	430	: : "r" (pmd) : "cc");
1da177e4 LT	431	}
	432
	433	#undef tlb_flag
	434	#undef always_tlb_flags
	435	#undef possible_tlb_flags
	436
	437	/*
	438	* Convert calls to our calling convention.
	439	*/
603fff54 RK	440	#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
	441	#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
	442
	443	#ifndef CONFIG_SMP
	444	#define flush_tlb_all local_flush_tlb_all
	445	#define flush_tlb_mm local_flush_tlb_mm
	446	#define flush_tlb_page local_flush_tlb_page
	447	#define flush_tlb_kernel_page local_flush_tlb_kernel_page
	448	#define flush_tlb_range local_flush_tlb_range
	449	#define flush_tlb_kernel_range local_flush_tlb_kernel_range
	450	#else
	451	extern void flush_tlb_all(void);
	452	extern void flush_tlb_mm(struct mm_struct *mm);
	453	extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
	454	extern void flush_tlb_kernel_page(unsigned long kaddr);
	455	extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
	456	extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
	457	#endif
1da177e4 LT	458
	459	/*
	460	* if PG_dcache_dirty is set for the page, we need to ensure that any
	461	* cache entries for the kernels virtual memory range are written
	462	* back to the page.
	463	*/
	464	extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
	465
1da177e4 LT	466	#endif
1da177e4 LT	467
0157903e HC	468	#endif /* CONFIG_MMU */
0157903e HC	469
1da177e4	470	#endif