projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 780431e3 | 1 | /* |
| fee40119 | 2 | * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes |
| 780431e3 | 3 | * |
| fee40119 | 4 | * Copyright (c) 2005-2008 Analog Devices Inc. |
| 780431e3 MF |
5 | * Copyright (C) 2005 John DeHority |
| 6 | * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de) | |
| 7 | * | |
| fee40119 | 8 | * Licensed under the GPL-2. |
| 780431e3 MF |
9 | */ |
| 10 | ||
| 11 | #ifndef _BLACKFIN_TIMERS_H_ | |
| 12 | #define _BLACKFIN_TIMERS_H_ | |
| 13 | ||
| 14 | #include <linux/types.h> | |
| 15 | #include <asm/blackfin.h> | |
| 16 | ||
| 17 | /* | |
| 18 | * BF537/BF527: 8 timers: | |
| 19 | */ | |
| 20 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) | |
| 21 | # define MAX_BLACKFIN_GPTIMERS 8 | |
| 22 | # define TIMER0_GROUP_REG TIMER_ENABLE | |
| 23 | #endif | |
| 6eceb0d4 MF |
24 | /* |
| 25 | * BF54x: 11 timers (BF542: 8 timers): | |
| 26 | */ | |
| 27 | #if defined(BF548_FAMILY) | |
| 28 | # ifdef CONFIG_BF542 | |
| 29 | # define MAX_BLACKFIN_GPTIMERS 8 | |
| 30 | # else | |
| 31 | # define MAX_BLACKFIN_GPTIMERS 11 | |
| 32 | # define TIMER8_GROUP_REG TIMER_ENABLE1 | |
| 33 | # endif | |
| 34 | # define TIMER0_GROUP_REG TIMER_ENABLE0 | |
| 35 | #endif | |
| 780431e3 MF |
36 | /* |
| 37 | * BF561: 12 timers: | |
| 38 | */ | |
| 39 | #if defined(CONFIG_BF561) | |
| 40 | # define MAX_BLACKFIN_GPTIMERS 12 | |
| 41 | # define TIMER0_GROUP_REG TMRS8_ENABLE | |
| 42 | # define TIMER8_GROUP_REG TMRS4_ENABLE | |
| 43 | #endif | |
| 44 | /* | |
| 45 | * All others: 3 timers: | |
| 46 | */ | |
| 47 | #if !defined(MAX_BLACKFIN_GPTIMERS) | |
| 48 | # define MAX_BLACKFIN_GPTIMERS 3 | |
| 49 | # define TIMER0_GROUP_REG TIMER_ENABLE | |
| 50 | #endif | |
| 51 | ||
| 52 | #define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1) | |
| 53 | #define BFIN_TIMER_OCTET(x) ((x) >> 3) | |
| 54 | ||
| 55 | /* used in masks for timer_enable() and timer_disable() */ | |
| 56 | #define TIMER0bit 0x0001 /* 0001b */ | |
| 57 | #define TIMER1bit 0x0002 /* 0010b */ | |
| 58 | #define TIMER2bit 0x0004 /* 0100b */ | |
| 6eceb0d4 MF |
59 | #define TIMER3bit 0x0008 |
| 60 | #define TIMER4bit 0x0010 | |
| 61 | #define TIMER5bit 0x0020 | |
| 62 | #define TIMER6bit 0x0040 | |
| 63 | #define TIMER7bit 0x0080 | |
| 64 | #define TIMER8bit 0x0100 | |
| 65 | #define TIMER9bit 0x0200 | |
| 66 | #define TIMER10bit 0x0400 | |
| 67 | #define TIMER11bit 0x0800 | |
| 780431e3 MF |
68 | |
| 69 | #define TIMER0_id 0 | |
| 70 | #define TIMER1_id 1 | |
| 71 | #define TIMER2_id 2 | |
| 6eceb0d4 MF |
72 | #define TIMER3_id 3 |
| 73 | #define TIMER4_id 4 | |
| 74 | #define TIMER5_id 5 | |
| 75 | #define TIMER6_id 6 | |
| 76 | #define TIMER7_id 7 | |
| 77 | #define TIMER8_id 8 | |
| 78 | #define TIMER9_id 9 | |
| 79 | #define TIMER10_id 10 | |
| 80 | #define TIMER11_id 11 | |
| 780431e3 MF |
81 | |
| 82 | /* associated timers for ppi framesync: */ | |
| 83 | ||
| 84 | #if defined(CONFIG_BF561) | |
| 85 | # define FS0_1_TIMER_ID TIMER8_id | |
| 86 | # define FS0_2_TIMER_ID TIMER9_id | |
| 87 | # define FS1_1_TIMER_ID TIMER10_id | |
| 88 | # define FS1_2_TIMER_ID TIMER11_id | |
| 89 | # define FS0_1_TIMER_BIT TIMER8bit | |
| 90 | # define FS0_2_TIMER_BIT TIMER9bit | |
| 91 | # define FS1_1_TIMER_BIT TIMER10bit | |
| 92 | # define FS1_2_TIMER_BIT TIMER11bit | |
| 93 | # undef FS1_TIMER_ID | |
| 94 | # undef FS2_TIMER_ID | |
| 95 | # undef FS1_TIMER_BIT | |
| 96 | # undef FS2_TIMER_BIT | |
| 97 | #else | |
| 98 | # define FS1_TIMER_ID TIMER0_id | |
| 99 | # define FS2_TIMER_ID TIMER1_id | |
| 100 | # define FS1_TIMER_BIT TIMER0bit | |
| 101 | # define FS2_TIMER_BIT TIMER1bit | |
| 102 | #endif | |
| 103 | ||
| 104 | /* | |
| 105 | * Timer Configuration Register Bits | |
| 106 | */ | |
| 107 | #define TIMER_ERR 0xC000 | |
| 108 | #define TIMER_ERR_OVFL 0x4000 | |
| 109 | #define TIMER_ERR_PROG_PER 0x8000 | |
| 110 | #define TIMER_ERR_PROG_PW 0xC000 | |
| 111 | #define TIMER_EMU_RUN 0x0200 | |
| 112 | #define TIMER_TOGGLE_HI 0x0100 | |
| 113 | #define TIMER_CLK_SEL 0x0080 | |
| 114 | #define TIMER_OUT_DIS 0x0040 | |
| 115 | #define TIMER_TIN_SEL 0x0020 | |
| 116 | #define TIMER_IRQ_ENA 0x0010 | |
| 117 | #define TIMER_PERIOD_CNT 0x0008 | |
| 118 | #define TIMER_PULSE_HI 0x0004 | |
| 119 | #define TIMER_MODE 0x0003 | |
| 120 | #define TIMER_MODE_PWM 0x0001 | |
| 121 | #define TIMER_MODE_WDTH 0x0002 | |
| 122 | #define TIMER_MODE_EXT_CLK 0x0003 | |
| 123 | ||
| 124 | /* | |
| 125 | * Timer Status Register Bits | |
| 126 | */ | |
| 6eceb0d4 MF |
127 | #define TIMER_STATUS_TIMIL0 0x0001 |
| 128 | #define TIMER_STATUS_TIMIL1 0x0002 | |
| 129 | #define TIMER_STATUS_TIMIL2 0x0004 | |
| 130 | #define TIMER_STATUS_TIMIL3 0x00000008 | |
| 131 | #define TIMER_STATUS_TIMIL4 0x00010000 | |
| 132 | #define TIMER_STATUS_TIMIL5 0x00020000 | |
| 133 | #define TIMER_STATUS_TIMIL6 0x00040000 | |
| 134 | #define TIMER_STATUS_TIMIL7 0x00080000 | |
| 135 | #define TIMER_STATUS_TIMIL8 0x0001 | |
| 136 | #define TIMER_STATUS_TIMIL9 0x0002 | |
| 137 | #define TIMER_STATUS_TIMIL10 0x0004 | |
| 138 | #define TIMER_STATUS_TIMIL11 0x0008 | |
| 139 | ||
| 140 | #define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ | |
| 141 | #define TIMER_STATUS_TOVF1 0x0020 | |
| 142 | #define TIMER_STATUS_TOVF2 0x0040 | |
| 143 | #define TIMER_STATUS_TOVF3 0x00000080 | |
| 144 | #define TIMER_STATUS_TOVF4 0x00100000 | |
| 145 | #define TIMER_STATUS_TOVF5 0x00200000 | |
| 146 | #define TIMER_STATUS_TOVF6 0x00400000 | |
| 147 | #define TIMER_STATUS_TOVF7 0x00800000 | |
| 148 | #define TIMER_STATUS_TOVF8 0x0010 | |
| 149 | #define TIMER_STATUS_TOVF9 0x0020 | |
| 150 | #define TIMER_STATUS_TOVF10 0x0040 | |
| 151 | #define TIMER_STATUS_TOVF11 0x0080 | |
| 780431e3 MF |
152 | |
| 153 | /* | |
| 154 | * Timer Slave Enable Status : write 1 to clear | |
| 155 | */ | |
| 156 | #define TIMER_STATUS_TRUN0 0x1000 | |
| 157 | #define TIMER_STATUS_TRUN1 0x2000 | |
| 158 | #define TIMER_STATUS_TRUN2 0x4000 | |
| 6eceb0d4 MF |
159 | #define TIMER_STATUS_TRUN3 0x00008000 |
| 160 | #define TIMER_STATUS_TRUN4 0x10000000 | |
| 161 | #define TIMER_STATUS_TRUN5 0x20000000 | |
| 162 | #define TIMER_STATUS_TRUN6 0x40000000 | |
| 163 | #define TIMER_STATUS_TRUN7 0x80000000 | |
| 164 | #define TIMER_STATUS_TRUN 0xF000F000 | |
| 165 | #define TIMER_STATUS_TRUN8 0x1000 | |
| 166 | #define TIMER_STATUS_TRUN9 0x2000 | |
| 167 | #define TIMER_STATUS_TRUN10 0x4000 | |
| 168 | #define TIMER_STATUS_TRUN11 0x8000 | |
| 780431e3 MF |
169 | |
| 170 | /* The actual gptimer API */ | |
| 171 | ||
| 172 | void set_gptimer_pwidth (int timer_id, uint32_t width); | |
| 173 | uint32_t get_gptimer_pwidth (int timer_id); | |
| 174 | void set_gptimer_period (int timer_id, uint32_t period); | |
| 175 | uint32_t get_gptimer_period (int timer_id); | |
| 176 | uint32_t get_gptimer_count (int timer_id); | |
| 177 | uint16_t get_gptimer_intr (int timer_id); | |
| 178 | void clear_gptimer_intr (int timer_id); | |
| 4ad1ec71 MF |
179 | uint16_t get_gptimer_over (int timer_id); |
| 180 | void clear_gptimer_over (int timer_id); | |
| 780431e3 MF |
181 | void set_gptimer_config (int timer_id, uint16_t config); |
| 182 | uint16_t get_gptimer_config (int timer_id); | |
| 183 | void set_gptimer_pulse_hi (int timer_id); | |
| 184 | void clear_gptimer_pulse_hi(int timer_id); | |
| 185 | void enable_gptimers (uint16_t mask); | |
| 186 | void disable_gptimers (uint16_t mask); | |
| 187 | uint16_t get_enabled_gptimers (void); | |
| 188 | uint32_t get_gptimer_status (int group); | |
| 189 | void set_gptimer_status (int group, uint32_t value); | |
| 190 | ||
| 191 | #endif |