Commit | Line | Data |
---|---|---|
088eec11 | 1 | /* |
287050fe MF |
2 | * File: include/asm-blackfin/mach-bf548/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
088eec11 | 4 | * |
287050fe MF |
5 | * Copyright (C) 2004-2007 Analog Devices Inc. |
6 | * Licensed under the GPL-2 or later. | |
088eec11 RH |
7 | */ |
8 | ||
1aafd909 | 9 | /* This file shoule be up to date with: |
7cc1c4b2 | 10 | * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
1aafd909 MF |
11 | */ |
12 | ||
088eec11 RH |
13 | #ifndef _MACH_ANOMALY_H_ |
14 | #define _MACH_ANOMALY_H_ | |
287050fe | 15 | |
1aafd909 MF |
16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ |
17 | #define ANOMALY_05000074 (1) | |
18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
19 | #define ANOMALY_05000119 (1) | |
20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
21 | #define ANOMALY_05000122 (1) | |
22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
23 | #define ANOMALY_05000245 (1) | |
1aafd909 MF |
24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
25 | #define ANOMALY_05000265 (1) | |
26 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
27 | #define ANOMALY_05000272 (1) | |
60e9356d | 28 | /* False Hardware Error Exception when ISR context is not restored */ |
7cc1c4b2 | 29 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 30 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
7cc1c4b2 | 31 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) |
1aafd909 MF |
32 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
33 | #define ANOMALY_05000310 (1) | |
34 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
7cc1c4b2 | 35 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) |
1aafd909 | 36 | /* TWI Slave Boot Mode Is Not Functional */ |
7cc1c4b2 | 37 | #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) |
1aafd909 | 38 | /* External FIFO Boot Mode Is Not Functional */ |
7cc1c4b2 | 39 | #define ANOMALY_05000325 (__SILICON_REVISION__ < 1) |
1aafd909 | 40 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ |
7cc1c4b2 | 41 | #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) |
1aafd909 | 42 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
7cc1c4b2 | 43 | #define ANOMALY_05000328 (__SILICON_REVISION__ < 1) |
1aafd909 | 44 | /* Synchronous Burst Flash Boot Mode Is Not Functional */ |
7cc1c4b2 | 45 | #define ANOMALY_05000329 (__SILICON_REVISION__ < 1) |
1aafd909 | 46 | /* Host DMA Boot Mode Is Not Functional */ |
7cc1c4b2 | 47 | #define ANOMALY_05000330 (__SILICON_REVISION__ < 1) |
1aafd909 | 48 | /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ |
7cc1c4b2 | 49 | #define ANOMALY_05000334 (__SILICON_REVISION__ < 1) |
1aafd909 | 50 | /* Inadequate Rotary Debounce Logic Duration */ |
7cc1c4b2 | 51 | #define ANOMALY_05000335 (__SILICON_REVISION__ < 1) |
1aafd909 | 52 | /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ |
7cc1c4b2 | 53 | #define ANOMALY_05000336 (__SILICON_REVISION__ < 1) |
1aafd909 | 54 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
7cc1c4b2 | 55 | #define ANOMALY_05000337 (__SILICON_REVISION__ < 1) |
1aafd909 | 56 | /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ |
7cc1c4b2 | 57 | #define ANOMALY_05000338 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 58 | /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ |
7cc1c4b2 | 59 | #define ANOMALY_05000340 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 60 | /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ |
7cc1c4b2 | 61 | #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 62 | /* USB Calibration Value Is Not Intialized */ |
7cc1c4b2 | 63 | #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 64 | /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ |
7cc1c4b2 | 65 | #define ANOMALY_05000347 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 66 | /* Data Lost when Core Reads SDH Data FIFO */ |
7cc1c4b2 | 67 | #define ANOMALY_05000349 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 68 | /* PLL Status Register Is Inaccurate */ |
7cc1c4b2 MF |
69 | #define ANOMALY_05000351 (__SILICON_REVISION__ < 1) |
70 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | |
71 | #define ANOMALY_05000357 (1) | |
72 | /* External Memory Read Access Hangs Core With PLL Bypass */ | |
73 | #define ANOMALY_05000360 (1) | |
74 | /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ | |
75 | #define ANOMALY_05000365 (1) | |
76 | /* Addressing Conflict between Boot ROM and Asynchronous Memory */ | |
77 | #define ANOMALY_05000369 (1) | |
78 | /* Mobile DDR Operation Not Functional */ | |
79 | #define ANOMALY_05000377 (1) | |
80 | /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ | |
81 | #define ANOMALY_05000378 (1) | |
1aafd909 MF |
82 | |
83 | /* Anomalies that don't exist on this proc */ | |
84 | #define ANOMALY_05000125 (0) | |
2cbfe107 | 85 | #define ANOMALY_05000158 (0) |
1aafd909 MF |
86 | #define ANOMALY_05000183 (0) |
87 | #define ANOMALY_05000198 (0) | |
0174dd59 | 88 | #define ANOMALY_05000230 (0) |
1aafd909 | 89 | #define ANOMALY_05000244 (0) |
60e9356d | 90 | #define ANOMALY_05000261 (0) |
1aafd909 MF |
91 | #define ANOMALY_05000263 (0) |
92 | #define ANOMALY_05000266 (0) | |
93 | #define ANOMALY_05000273 (0) | |
94 | #define ANOMALY_05000311 (0) | |
2b39331a | 95 | #define ANOMALY_05000323 (0) |
088eec11 | 96 | |
1aafd909 | 97 | #endif |