projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 088eec11 | 1 | /* |
| 287050fe MF |
2 | * File: include/asm-blackfin/mach-bf548/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
| 088eec11 | 4 | * |
| 287050fe MF |
5 | * Copyright (C) 2004-2007 Analog Devices Inc. |
| 6 | * Licensed under the GPL-2 or later. | |
| 088eec11 RH |
7 | */ |
| 8 | ||
| 1aafd909 MF |
9 | /* This file shoule be up to date with: |
| 10 | * - Revision B, April 6, 2007; ADSP-BF549 Silicon Anomaly List | |
| 11 | */ | |
| 12 | ||
| 088eec11 RH |
13 | #ifndef _MACH_ANOMALY_H_ |
| 14 | #define _MACH_ANOMALY_H_ | |
| 287050fe | 15 | |
| 1aafd909 MF |
16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ |
| 17 | #define ANOMALY_05000074 (1) | |
| 18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
| 19 | #define ANOMALY_05000119 (1) | |
| 20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
| 21 | #define ANOMALY_05000122 (1) | |
| 22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
| 23 | #define ANOMALY_05000245 (1) | |
| 24 | /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ | |
| 25 | #define ANOMALY_05000255 (1) | |
| 26 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | |
| 27 | #define ANOMALY_05000265 (1) | |
| 28 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
| 29 | #define ANOMALY_05000272 (1) | |
| 30 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | |
| 31 | #define ANOMALY_05000310 (1) | |
| 32 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
| 33 | #define ANOMALY_05000312 (1) | |
| 34 | /* TWI Slave Boot Mode Is Not Functional */ | |
| 35 | #define ANOMALY_05000324 (1) | |
| 36 | /* External FIFO Boot Mode Is Not Functional */ | |
| 37 | #define ANOMALY_05000325 (1) | |
| 38 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ | |
| 39 | #define ANOMALY_05000327 (1) | |
| 40 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | |
| 41 | #define ANOMALY_05000328 (1) | |
| 42 | /* Synchronous Burst Flash Boot Mode Is Not Functional */ | |
| 43 | #define ANOMALY_05000329 (1) | |
| 44 | /* Host DMA Boot Mode Is Not Functional */ | |
| 45 | #define ANOMALY_05000330 (1) | |
| 46 | /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ | |
| 47 | #define ANOMALY_05000334 (1) | |
| 48 | /* Inadequate Rotary Debounce Logic Duration */ | |
| 49 | #define ANOMALY_05000335 (1) | |
| 50 | /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ | |
| 51 | #define ANOMALY_05000336 (1) | |
| 52 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | |
| 53 | #define ANOMALY_05000337 (1) | |
| 54 | /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ | |
| 55 | #define ANOMALY_05000338 (1) | |
| 56 | ||
| 57 | /* Anomalies that don't exist on this proc */ | |
| 58 | #define ANOMALY_05000125 (0) | |
| 59 | #define ANOMALY_05000183 (0) | |
| 60 | #define ANOMALY_05000198 (0) | |
| 61 | #define ANOMALY_05000244 (0) | |
| 62 | #define ANOMALY_05000263 (0) | |
| 63 | #define ANOMALY_05000266 (0) | |
| 64 | #define ANOMALY_05000273 (0) | |
| 65 | #define ANOMALY_05000311 (0) | |
| 088eec11 | 66 | |
| 1aafd909 | 67 | #endif |