[deliverable/linux.git] / include / asm-blackfin / mach-bf548 / anomaly.h

/*
 * File: include/asm-blackfin/mach-bf548/anomaly.h
 * Bugs: Enter bugs at http://blackfin.uclinux.org/
 *
 * Copyright (C) 2004-2007 Analog Devices Inc.
 * Licensed under the GPL-2 or later.
 */

#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_

#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
			  * slot1 and store of a P register in slot 2 is not
			  * supported */
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
			  * Channel DMA stops */
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
			  * registers. */
#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
			  * Shadow of a Conditional Branch */
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
			  * interrupt not functional */
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
			  * SPORT external receive and transmit clocks. */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
			  * VDDint <=0.9V */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
			  * not restored */
#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
			  * Boundary of Reserved Memory */
#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
			  * LC Registers Are Interrupted */
#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
			  * the USB FIFO Simultaneously */
#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
			  * function */
#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
			  * */
#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
			  * Skew */
#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
			  * of Host DMA Port */
#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
			  * Allowed Configuration on Host DMA Port */
#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */

#endif /* _MACH_ANOMALY_H_ */
Commit	Line	Data
088eec11	1	/*
287050fe MF	2	* File: include/asm-blackfin/mach-bf548/anomaly.h
287050fe MF	3	* Bugs: Enter bugs at http://blackfin.uclinux.org/
088eec11	4	*
287050fe MF	5	* Copyright (C) 2004-2007 Analog Devices Inc.
287050fe MF	6	* Licensed under the GPL-2 or later.
088eec11 RH	7	*/
	8
	9	#ifndef _MACH_ANOMALY_H_
	10	#define _MACH_ANOMALY_H_
287050fe	11
088eec11	12	#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
287050fe MF	13	* slot1 and store of a P register in slot 2 is not
287050fe MF	14	* supported */
088eec11	15	#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
287050fe	16	* Channel DMA stops */
088eec11	17	#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
287050fe	18	* registers. */
088eec11	19	#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
287050fe	20	* Shadow of a Conditional Branch */
088eec11	21	#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
287050fe	22	* interrupt not functional */
088eec11	23	#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
287050fe	24	* SPORT external receive and transmit clocks. */
088eec11	25	#define ANOMALY_05000272 /* Certain data cache write through modes fail for
287050fe	26	* VDDint <=0.9V */
24a07a12	27	#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
287050fe	28	* not restored */
088eec11	29	#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
287050fe	30	* Boundary of Reserved Memory */
088eec11	31	#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
287050fe	32	* LC Registers Are Interrupted */
088eec11 RH	33	#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
	34	#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
	35	#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
287050fe	36	* the USB FIFO Simultaneously */
088eec11	37	#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
287050fe	38	* function */
088eec11	39	#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
287050fe	40	* */
088eec11 RH	41	#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
088eec11 RH	42	#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
287050fe	43	* Skew */
088eec11 RH	44	#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
088eec11 RH	45	#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
287050fe	46	* of Host DMA Port */
088eec11	47	#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
287050fe	48	* Allowed Configuration on Host DMA Port */
088eec11 RH	49	#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
	50
	51	#endif /* _MACH_ANOMALY_H_ */