Commit | Line | Data |
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088eec11 | 1 | /* |
287050fe MF |
2 | * File: include/asm-blackfin/mach-bf548/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
088eec11 | 4 | * |
287050fe MF |
5 | * Copyright (C) 2004-2007 Analog Devices Inc. |
6 | * Licensed under the GPL-2 or later. | |
088eec11 RH |
7 | */ |
8 | ||
1aafd909 | 9 | /* This file shoule be up to date with: |
bc8c84c9 | 10 | * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List |
1aafd909 MF |
11 | */ |
12 | ||
088eec11 RH |
13 | #ifndef _MACH_ANOMALY_H_ |
14 | #define _MACH_ANOMALY_H_ | |
287050fe | 15 | |
1aafd909 MF |
16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ |
17 | #define ANOMALY_05000074 (1) | |
18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
19 | #define ANOMALY_05000119 (1) | |
20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
21 | #define ANOMALY_05000122 (1) | |
22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
23 | #define ANOMALY_05000245 (1) | |
1aafd909 MF |
24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
25 | #define ANOMALY_05000265 (1) | |
26 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
27 | #define ANOMALY_05000272 (1) | |
60e9356d MF |
28 | /* False Hardware Error Exception when ISR context is not restored */ |
29 | #define ANOMALY_05000281 (1) | |
bc8c84c9 MF |
30 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
31 | #define ANOMALY_05000304 (1) | |
1aafd909 MF |
32 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
33 | #define ANOMALY_05000310 (1) | |
34 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
35 | #define ANOMALY_05000312 (1) | |
36 | /* TWI Slave Boot Mode Is Not Functional */ | |
37 | #define ANOMALY_05000324 (1) | |
38 | /* External FIFO Boot Mode Is Not Functional */ | |
39 | #define ANOMALY_05000325 (1) | |
40 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ | |
41 | #define ANOMALY_05000327 (1) | |
42 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | |
43 | #define ANOMALY_05000328 (1) | |
44 | /* Synchronous Burst Flash Boot Mode Is Not Functional */ | |
45 | #define ANOMALY_05000329 (1) | |
46 | /* Host DMA Boot Mode Is Not Functional */ | |
47 | #define ANOMALY_05000330 (1) | |
48 | /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ | |
49 | #define ANOMALY_05000334 (1) | |
50 | /* Inadequate Rotary Debounce Logic Duration */ | |
51 | #define ANOMALY_05000335 (1) | |
52 | /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ | |
53 | #define ANOMALY_05000336 (1) | |
54 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | |
55 | #define ANOMALY_05000337 (1) | |
56 | /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ | |
57 | #define ANOMALY_05000338 (1) | |
bc8c84c9 MF |
58 | /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ |
59 | #define ANOMALY_05000340 (1) | |
60 | /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ | |
61 | #define ANOMALY_05000344 (1) | |
62 | /* USB Calibration Value Is Not Intialized */ | |
63 | #define ANOMALY_05000346 (1) | |
64 | /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ | |
65 | #define ANOMALY_05000347 (1) | |
66 | /* Data Lost when Core Reads SDH Data FIFO */ | |
67 | #define ANOMALY_05000349 (1) | |
68 | /* PLL Status Register Is Inaccurate */ | |
69 | #define ANOMALY_05000351 (1) | |
1aafd909 MF |
70 | |
71 | /* Anomalies that don't exist on this proc */ | |
72 | #define ANOMALY_05000125 (0) | |
2cbfe107 | 73 | #define ANOMALY_05000158 (0) |
1aafd909 MF |
74 | #define ANOMALY_05000183 (0) |
75 | #define ANOMALY_05000198 (0) | |
0174dd59 | 76 | #define ANOMALY_05000230 (0) |
1aafd909 | 77 | #define ANOMALY_05000244 (0) |
60e9356d | 78 | #define ANOMALY_05000261 (0) |
1aafd909 MF |
79 | #define ANOMALY_05000263 (0) |
80 | #define ANOMALY_05000266 (0) | |
81 | #define ANOMALY_05000273 (0) | |
82 | #define ANOMALY_05000311 (0) | |
2b39331a | 83 | #define ANOMALY_05000323 (0) |
088eec11 | 84 | |
1aafd909 | 85 | #endif |