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1da177e4 LT |
1 | #ifndef __GENERIC_IO_H |
2 | #define __GENERIC_IO_H | |
3 | ||
4 | #include <linux/linkage.h> | |
dae409a2 | 5 | #include <asm/byteorder.h> |
1da177e4 LT |
6 | |
7 | /* | |
8 | * These are the "generic" interfaces for doing new-style | |
9 | * memory-mapped or PIO accesses. Architectures may do | |
10 | * their own arch-optimized versions, these just act as | |
11 | * wrappers around the old-style IO register access functions: | |
12 | * read[bwl]/write[bwl]/in[bwl]/out[bwl] | |
13 | * | |
14 | * Don't include this directly, include it from <asm/io.h>. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * Read/write from/to an (offsettable) iomem cookie. It might be a PIO | |
19 | * access or a MMIO access, these functions don't care. The info is | |
20 | * encoded in the hardware mapping set up by the mapping functions | |
21 | * (or the cookie itself, depending on implementation and hw). | |
22 | * | |
23 | * The generic routines just encode the PIO/MMIO as part of the | |
24 | * cookie, and coldly assume that the MMIO IO mappings are not | |
25 | * in the low address range. Architectures for which this is not | |
26 | * true can't use this generic implementation. | |
27 | */ | |
144b2a91 HH |
28 | extern unsigned int ioread8(void __iomem *); |
29 | extern unsigned int ioread16(void __iomem *); | |
30 | extern unsigned int ioread16be(void __iomem *); | |
31 | extern unsigned int ioread32(void __iomem *); | |
32 | extern unsigned int ioread32be(void __iomem *); | |
1da177e4 | 33 | |
144b2a91 HH |
34 | extern void iowrite8(u8, void __iomem *); |
35 | extern void iowrite16(u16, void __iomem *); | |
36 | extern void iowrite16be(u16, void __iomem *); | |
37 | extern void iowrite32(u32, void __iomem *); | |
38 | extern void iowrite32be(u32, void __iomem *); | |
1da177e4 LT |
39 | |
40 | /* | |
41 | * "string" versions of the above. Note that they | |
42 | * use native byte ordering for the accesses (on | |
43 | * the assumption that IO and memory agree on a | |
44 | * byte order, and CPU byteorder is irrelevant). | |
45 | * | |
46 | * They do _not_ update the port address. If you | |
47 | * want MMIO that copies stuff laid out in MMIO | |
48 | * memory across multiple ports, use "memcpy_toio()" | |
49 | * and friends. | |
50 | */ | |
144b2a91 HH |
51 | extern void ioread8_rep(void __iomem *port, void *buf, unsigned long count); |
52 | extern void ioread16_rep(void __iomem *port, void *buf, unsigned long count); | |
53 | extern void ioread32_rep(void __iomem *port, void *buf, unsigned long count); | |
1da177e4 | 54 | |
144b2a91 HH |
55 | extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count); |
56 | extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count); | |
57 | extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count); | |
1da177e4 | 58 | |
ce816fa8 | 59 | #ifdef CONFIG_HAS_IOPORT_MAP |
1da177e4 LT |
60 | /* Create a virtual mapping cookie for an IO port range */ |
61 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | |
62 | extern void ioport_unmap(void __iomem *); | |
82ed223c | 63 | #endif |
1da177e4 | 64 | |
1526a756 | 65 | #ifndef ARCH_HAS_IOREMAP_WC |
66 | #define ioremap_wc ioremap_nocache | |
67 | #endif | |
68 | ||
d838270e TK |
69 | #ifndef ARCH_HAS_IOREMAP_WT |
70 | #define ioremap_wt ioremap_nocache | |
71 | #endif | |
72 | ||
82ed223c | 73 | #ifdef CONFIG_PCI |
66eab4df | 74 | /* Destroy a virtual mapping cookie for a PCI BAR (memory or IO) */ |
1da177e4 | 75 | struct pci_dev; |
1da177e4 | 76 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *); |
97a29d59 | 77 | #elif defined(CONFIG_GENERIC_IOMAP) |
fea80311 | 78 | struct pci_dev; |
fea80311 RD |
79 | static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) |
80 | { } | |
82ed223c | 81 | #endif |
1da177e4 | 82 | |
66eab4df MT |
83 | #include <asm-generic/pci_iomap.h> |
84 | ||
1da177e4 | 85 | #endif |