arm64: hugetlb: add support for PTE contiguous bit
[deliverable/linux.git] / include / asm-generic / pgtable.h
CommitLineData
1da177e4
LT
1#ifndef _ASM_GENERIC_PGTABLE_H
2#define _ASM_GENERIC_PGTABLE_H
3
673eae82 4#ifndef __ASSEMBLY__
9535239f 5#ifdef CONFIG_MMU
673eae82 6
fbd71844 7#include <linux/mm_types.h>
187f1882 8#include <linux/bug.h>
e61ce6ad 9#include <linux/errno.h>
fbd71844 10
235a8f02
KS
11#if 4 - defined(__PAGETABLE_PUD_FOLDED) - defined(__PAGETABLE_PMD_FOLDED) != \
12 CONFIG_PGTABLE_LEVELS
13#error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{PUD,PMD}_FOLDED
14#endif
15
6ee8630e
HD
16/*
17 * On almost all architectures and configurations, 0 can be used as the
18 * upper ceiling to free_pgtables(): on many architectures it has the same
19 * effect as using TASK_SIZE. However, there is one configuration which
20 * must impose a more careful limit, to avoid freeing kernel pgtables.
21 */
22#ifndef USER_PGTABLES_CEILING
23#define USER_PGTABLES_CEILING 0UL
24#endif
25
1da177e4 26#ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
e2cda322
AA
27extern int ptep_set_access_flags(struct vm_area_struct *vma,
28 unsigned long address, pte_t *ptep,
29 pte_t entry, int dirty);
30#endif
31
32#ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
bd5e88ad 33#ifdef CONFIG_TRANSPARENT_HUGEPAGE
e2cda322
AA
34extern int pmdp_set_access_flags(struct vm_area_struct *vma,
35 unsigned long address, pmd_t *pmdp,
36 pmd_t entry, int dirty);
bd5e88ad
VG
37#else
38static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
39 unsigned long address, pmd_t *pmdp,
40 pmd_t entry, int dirty)
41{
42 BUILD_BUG();
43 return 0;
44}
45#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
46#endif
47
48#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
e2cda322
AA
49static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
50 unsigned long address,
51 pte_t *ptep)
52{
53 pte_t pte = *ptep;
54 int r = 1;
55 if (!pte_young(pte))
56 r = 0;
57 else
58 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte));
59 return r;
60}
61#endif
62
63#ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
64#ifdef CONFIG_TRANSPARENT_HUGEPAGE
65static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
66 unsigned long address,
67 pmd_t *pmdp)
68{
69 pmd_t pmd = *pmdp;
70 int r = 1;
71 if (!pmd_young(pmd))
72 r = 0;
73 else
74 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd));
75 return r;
76}
bd5e88ad 77#else
e2cda322
AA
78static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
79 unsigned long address,
80 pmd_t *pmdp)
81{
bd5e88ad 82 BUILD_BUG();
e2cda322
AA
83 return 0;
84}
85#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
86#endif
87
88#ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
e2cda322
AA
89int ptep_clear_flush_young(struct vm_area_struct *vma,
90 unsigned long address, pte_t *ptep);
91#endif
92
93#ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
bd5e88ad
VG
94#ifdef CONFIG_TRANSPARENT_HUGEPAGE
95extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
96 unsigned long address, pmd_t *pmdp);
97#else
98/*
99 * Despite relevant to THP only, this API is called from generic rmap code
100 * under PageTransHuge(), hence needs a dummy implementation for !THP
101 */
102static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
103 unsigned long address, pmd_t *pmdp)
104{
105 BUILD_BUG();
106 return 0;
107}
108#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
109#endif
110
1da177e4 111#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
e2cda322
AA
112static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
113 unsigned long address,
114 pte_t *ptep)
115{
116 pte_t pte = *ptep;
117 pte_clear(mm, address, ptep);
118 return pte;
119}
120#endif
121
8809aa2d 122#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
e2cda322 123#ifdef CONFIG_TRANSPARENT_HUGEPAGE
8809aa2d
AK
124static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
125 unsigned long address,
126 pmd_t *pmdp)
e2cda322
AA
127{
128 pmd_t pmd = *pmdp;
2d28a227 129 pmd_clear(pmdp);
e2cda322 130 return pmd;
49b24d6b 131}
e2cda322 132#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
133#endif
134
8809aa2d 135#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
fcbe08d6 136#ifdef CONFIG_TRANSPARENT_HUGEPAGE
8809aa2d 137static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm,
fcbe08d6
MS
138 unsigned long address, pmd_t *pmdp,
139 int full)
140{
8809aa2d 141 return pmdp_huge_get_and_clear(mm, address, pmdp);
fcbe08d6
MS
142}
143#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
144#endif
145
a600388d 146#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
e2cda322
AA
147static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
148 unsigned long address, pte_t *ptep,
149 int full)
150{
151 pte_t pte;
152 pte = ptep_get_and_clear(mm, address, ptep);
153 return pte;
154}
a600388d
ZA
155#endif
156
9888a1ca
ZA
157/*
158 * Some architectures may be able to avoid expensive synchronization
159 * primitives when modifications are made to PTE's which are already
160 * not present, or in the process of an address space destruction.
161 */
162#ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
e2cda322
AA
163static inline void pte_clear_not_present_full(struct mm_struct *mm,
164 unsigned long address,
165 pte_t *ptep,
166 int full)
167{
168 pte_clear(mm, address, ptep);
169}
a600388d
ZA
170#endif
171
1da177e4 172#ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
e2cda322
AA
173extern pte_t ptep_clear_flush(struct vm_area_struct *vma,
174 unsigned long address,
175 pte_t *ptep);
176#endif
177
8809aa2d
AK
178#ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
179extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
e2cda322
AA
180 unsigned long address,
181 pmd_t *pmdp);
1da177e4
LT
182#endif
183
184#ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
8c65b4a6 185struct mm_struct;
1da177e4
LT
186static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
187{
188 pte_t old_pte = *ptep;
189 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
190}
191#endif
192
e2cda322
AA
193#ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT
194#ifdef CONFIG_TRANSPARENT_HUGEPAGE
195static inline void pmdp_set_wrprotect(struct mm_struct *mm,
196 unsigned long address, pmd_t *pmdp)
197{
198 pmd_t old_pmd = *pmdp;
199 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd));
200}
bd5e88ad 201#else
e2cda322
AA
202static inline void pmdp_set_wrprotect(struct mm_struct *mm,
203 unsigned long address, pmd_t *pmdp)
204{
bd5e88ad 205 BUILD_BUG();
e2cda322
AA
206}
207#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
208#endif
209
210#ifndef __HAVE_ARCH_PMDP_SPLITTING_FLUSH
73636b1a
CM
211extern void pmdp_splitting_flush(struct vm_area_struct *vma,
212 unsigned long address, pmd_t *pmdp);
e2cda322
AA
213#endif
214
15a25b2e
AK
215#ifndef pmdp_collapse_flush
216#ifdef CONFIG_TRANSPARENT_HUGEPAGE
f28b6ff8
AK
217extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
218 unsigned long address, pmd_t *pmdp);
15a25b2e
AK
219#else
220static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
221 unsigned long address,
222 pmd_t *pmdp)
223{
224 BUILD_BUG();
225 return *pmdp;
226}
227#define pmdp_collapse_flush pmdp_collapse_flush
228#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
229#endif
230
e3ebcf64 231#ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
6b0b50b0
AK
232extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
233 pgtable_t pgtable);
e3ebcf64
GS
234#endif
235
236#ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
6b0b50b0 237extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
e3ebcf64
GS
238#endif
239
46dcde73
GS
240#ifndef __HAVE_ARCH_PMDP_INVALIDATE
241extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
242 pmd_t *pmdp);
243#endif
244
1da177e4 245#ifndef __HAVE_ARCH_PTE_SAME
e2cda322
AA
246static inline int pte_same(pte_t pte_a, pte_t pte_b)
247{
248 return pte_val(pte_a) == pte_val(pte_b);
249}
250#endif
251
45961722
KW
252#ifndef __HAVE_ARCH_PTE_UNUSED
253/*
254 * Some architectures provide facilities to virtualization guests
255 * so that they can flag allocated pages as unused. This allows the
256 * host to transparently reclaim unused pages. This function returns
257 * whether the pte's page is unused.
258 */
259static inline int pte_unused(pte_t pte)
260{
261 return 0;
262}
263#endif
264
e2cda322
AA
265#ifndef __HAVE_ARCH_PMD_SAME
266#ifdef CONFIG_TRANSPARENT_HUGEPAGE
267static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
268{
269 return pmd_val(pmd_a) == pmd_val(pmd_b);
270}
271#else /* CONFIG_TRANSPARENT_HUGEPAGE */
272static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
273{
bd5e88ad 274 BUILD_BUG();
e2cda322
AA
275 return 0;
276}
277#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
278#endif
279
1da177e4
LT
280#ifndef __HAVE_ARCH_PGD_OFFSET_GATE
281#define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
282#endif
283
0b0968a3 284#ifndef __HAVE_ARCH_MOVE_PTE
8b1f3124 285#define move_pte(pte, prot, old_addr, new_addr) (pte)
8b1f3124
NP
286#endif
287
2c3cf556 288#ifndef pte_accessible
20841405 289# define pte_accessible(mm, pte) ((void)(pte), 1)
2c3cf556
RR
290#endif
291
61c77326
SL
292#ifndef flush_tlb_fix_spurious_fault
293#define flush_tlb_fix_spurious_fault(vma, address) flush_tlb_page(vma, address)
294#endif
295
0634a632
PM
296#ifndef pgprot_noncached
297#define pgprot_noncached(prot) (prot)
298#endif
299
2520bd31 300#ifndef pgprot_writecombine
301#define pgprot_writecombine pgprot_noncached
302#endif
303
d1b4bfbf
TK
304#ifndef pgprot_writethrough
305#define pgprot_writethrough pgprot_noncached
306#endif
307
8b921acf
LD
308#ifndef pgprot_device
309#define pgprot_device pgprot_noncached
310#endif
311
64e45507
PF
312#ifndef pgprot_modify
313#define pgprot_modify pgprot_modify
314static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
315{
316 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
317 newprot = pgprot_noncached(newprot);
318 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
319 newprot = pgprot_writecombine(newprot);
320 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
321 newprot = pgprot_device(newprot);
322 return newprot;
323}
324#endif
325
1da177e4 326/*
8f6c99c1
HD
327 * When walking page tables, get the address of the next boundary,
328 * or the end address of the range if that comes earlier. Although no
329 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
1da177e4
LT
330 */
331
1da177e4
LT
332#define pgd_addr_end(addr, end) \
333({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
334 (__boundary - 1 < (end) - 1)? __boundary: (end); \
335})
1da177e4
LT
336
337#ifndef pud_addr_end
338#define pud_addr_end(addr, end) \
339({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
340 (__boundary - 1 < (end) - 1)? __boundary: (end); \
341})
342#endif
343
344#ifndef pmd_addr_end
345#define pmd_addr_end(addr, end) \
346({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
347 (__boundary - 1 < (end) - 1)? __boundary: (end); \
348})
349#endif
350
1da177e4
LT
351/*
352 * When walking page tables, we usually want to skip any p?d_none entries;
353 * and any p?d_bad entries - reporting the error before resetting to none.
354 * Do the tests inline, but report and clear the bad entry in mm/memory.c.
355 */
356void pgd_clear_bad(pgd_t *);
357void pud_clear_bad(pud_t *);
358void pmd_clear_bad(pmd_t *);
359
360static inline int pgd_none_or_clear_bad(pgd_t *pgd)
361{
362 if (pgd_none(*pgd))
363 return 1;
364 if (unlikely(pgd_bad(*pgd))) {
365 pgd_clear_bad(pgd);
366 return 1;
367 }
368 return 0;
369}
370
371static inline int pud_none_or_clear_bad(pud_t *pud)
372{
373 if (pud_none(*pud))
374 return 1;
375 if (unlikely(pud_bad(*pud))) {
376 pud_clear_bad(pud);
377 return 1;
378 }
379 return 0;
380}
381
382static inline int pmd_none_or_clear_bad(pmd_t *pmd)
383{
384 if (pmd_none(*pmd))
385 return 1;
386 if (unlikely(pmd_bad(*pmd))) {
387 pmd_clear_bad(pmd);
388 return 1;
389 }
390 return 0;
391}
9535239f 392
1ea0704e
JF
393static inline pte_t __ptep_modify_prot_start(struct mm_struct *mm,
394 unsigned long addr,
395 pte_t *ptep)
396{
397 /*
398 * Get the current pte state, but zero it out to make it
399 * non-present, preventing the hardware from asynchronously
400 * updating it.
401 */
402 return ptep_get_and_clear(mm, addr, ptep);
403}
404
405static inline void __ptep_modify_prot_commit(struct mm_struct *mm,
406 unsigned long addr,
407 pte_t *ptep, pte_t pte)
408{
409 /*
410 * The pte is non-present, so there's no hardware state to
411 * preserve.
412 */
413 set_pte_at(mm, addr, ptep, pte);
414}
415
416#ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
417/*
418 * Start a pte protection read-modify-write transaction, which
419 * protects against asynchronous hardware modifications to the pte.
420 * The intention is not to prevent the hardware from making pte
421 * updates, but to prevent any updates it may make from being lost.
422 *
423 * This does not protect against other software modifications of the
424 * pte; the appropriate pte lock must be held over the transation.
425 *
426 * Note that this interface is intended to be batchable, meaning that
427 * ptep_modify_prot_commit may not actually update the pte, but merely
428 * queue the update to be done at some later time. The update must be
429 * actually committed before the pte lock is released, however.
430 */
431static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
432 unsigned long addr,
433 pte_t *ptep)
434{
435 return __ptep_modify_prot_start(mm, addr, ptep);
436}
437
438/*
439 * Commit an update to a pte, leaving any hardware-controlled bits in
440 * the PTE unmodified.
441 */
442static inline void ptep_modify_prot_commit(struct mm_struct *mm,
443 unsigned long addr,
444 pte_t *ptep, pte_t pte)
445{
446 __ptep_modify_prot_commit(mm, addr, ptep, pte);
447}
448#endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
fe1a6875 449#endif /* CONFIG_MMU */
1ea0704e 450
9535239f
GU
451/*
452 * A facility to provide lazy MMU batching. This allows PTE updates and
453 * page invalidations to be delayed until a call to leave lazy MMU mode
454 * is issued. Some architectures may benefit from doing this, and it is
455 * beneficial for both shadow and direct mode hypervisors, which may batch
456 * the PTE updates which happen during this window. Note that using this
457 * interface requires that read hazards be removed from the code. A read
458 * hazard could result in the direct mode hypervisor case, since the actual
459 * write to the page tables may not yet have taken place, so reads though
460 * a raw PTE pointer after it has been modified are not guaranteed to be
461 * up to date. This mode can only be entered and left under the protection of
462 * the page table locks for all page tables which may be modified. In the UP
463 * case, this is required so that preemption is disabled, and in the SMP case,
464 * it must synchronize the delayed page table writes properly on other CPUs.
465 */
466#ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE
467#define arch_enter_lazy_mmu_mode() do {} while (0)
468#define arch_leave_lazy_mmu_mode() do {} while (0)
469#define arch_flush_lazy_mmu_mode() do {} while (0)
470#endif
471
472/*
7fd7d83d
JF
473 * A facility to provide batching of the reload of page tables and
474 * other process state with the actual context switch code for
475 * paravirtualized guests. By convention, only one of the batched
476 * update (lazy) modes (CPU, MMU) should be active at any given time,
477 * entry should never be nested, and entry and exits should always be
478 * paired. This is for sanity of maintaining and reasoning about the
479 * kernel code. In this case, the exit (end of the context switch) is
480 * in architecture-specific code, and so doesn't need a generic
481 * definition.
9535239f 482 */
7fd7d83d 483#ifndef __HAVE_ARCH_START_CONTEXT_SWITCH
224101ed 484#define arch_start_context_switch(prev) do {} while (0)
9535239f
GU
485#endif
486
0f8975ec
PE
487#ifndef CONFIG_HAVE_ARCH_SOFT_DIRTY
488static inline int pte_soft_dirty(pte_t pte)
489{
490 return 0;
491}
492
493static inline int pmd_soft_dirty(pmd_t pmd)
494{
495 return 0;
496}
497
498static inline pte_t pte_mksoft_dirty(pte_t pte)
499{
500 return pte;
501}
502
503static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
504{
505 return pmd;
506}
179ef71c 507
a7b76174
MS
508static inline pte_t pte_clear_soft_dirty(pte_t pte)
509{
510 return pte;
511}
512
513static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
514{
515 return pmd;
516}
517
179ef71c
CG
518static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
519{
520 return pte;
521}
522
523static inline int pte_swp_soft_dirty(pte_t pte)
524{
525 return 0;
526}
527
528static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
529{
530 return pte;
531}
0f8975ec
PE
532#endif
533
34801ba9 534#ifndef __HAVE_PFNMAP_TRACKING
535/*
5180da41
SS
536 * Interfaces that can be used by architecture code to keep track of
537 * memory type of pfn mappings specified by the remap_pfn_range,
538 * vm_insert_pfn.
539 */
540
541/*
542 * track_pfn_remap is called when a _new_ pfn mapping is being established
543 * by remap_pfn_range() for physical range indicated by pfn and size.
34801ba9 544 */
5180da41 545static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
b3b9c293
KK
546 unsigned long pfn, unsigned long addr,
547 unsigned long size)
34801ba9 548{
549 return 0;
550}
551
552/*
5180da41
SS
553 * track_pfn_insert is called when a _new_ single pfn is established
554 * by vm_insert_pfn().
555 */
556static inline int track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
557 unsigned long pfn)
558{
559 return 0;
560}
561
562/*
563 * track_pfn_copy is called when vma that is covering the pfnmap gets
34801ba9 564 * copied through copy_page_range().
565 */
5180da41 566static inline int track_pfn_copy(struct vm_area_struct *vma)
34801ba9 567{
568 return 0;
569}
570
571/*
34801ba9 572 * untrack_pfn_vma is called while unmapping a pfnmap for a region.
573 * untrack can be called for a specific region indicated by pfn and size or
5180da41 574 * can be for the entire vma (in which case pfn, size are zero).
34801ba9 575 */
5180da41
SS
576static inline void untrack_pfn(struct vm_area_struct *vma,
577 unsigned long pfn, unsigned long size)
34801ba9 578{
579}
580#else
5180da41 581extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
b3b9c293
KK
582 unsigned long pfn, unsigned long addr,
583 unsigned long size);
5180da41
SS
584extern int track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
585 unsigned long pfn);
586extern int track_pfn_copy(struct vm_area_struct *vma);
587extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
588 unsigned long size);
34801ba9 589#endif
590
816422ad
KS
591#ifdef __HAVE_COLOR_ZERO_PAGE
592static inline int is_zero_pfn(unsigned long pfn)
593{
594 extern unsigned long zero_pfn;
595 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
596 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
597}
598
2f91ec8c
KS
599#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
600
816422ad
KS
601#else
602static inline int is_zero_pfn(unsigned long pfn)
603{
604 extern unsigned long zero_pfn;
605 return pfn == zero_pfn;
606}
607
608static inline unsigned long my_zero_pfn(unsigned long addr)
609{
610 extern unsigned long zero_pfn;
611 return zero_pfn;
612}
613#endif
614
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615#ifdef CONFIG_MMU
616
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617#ifndef CONFIG_TRANSPARENT_HUGEPAGE
618static inline int pmd_trans_huge(pmd_t pmd)
619{
620 return 0;
621}
622static inline int pmd_trans_splitting(pmd_t pmd)
623{
624 return 0;
625}
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626#ifndef __HAVE_ARCH_PMD_WRITE
627static inline int pmd_write(pmd_t pmd)
628{
629 BUG();
630 return 0;
631}
632#endif /* __HAVE_ARCH_PMD_WRITE */
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633#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
634
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635#ifndef pmd_read_atomic
636static inline pmd_t pmd_read_atomic(pmd_t *pmdp)
637{
638 /*
639 * Depend on compiler for an atomic pmd read. NOTE: this is
640 * only going to work, if the pmdval_t isn't larger than
641 * an unsigned long.
642 */
643 return *pmdp;
644}
645#endif
646
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647#ifndef pmd_move_must_withdraw
648static inline int pmd_move_must_withdraw(spinlock_t *new_pmd_ptl,
649 spinlock_t *old_pmd_ptl)
650{
651 /*
652 * With split pmd lock we also need to move preallocated
653 * PTE page table if new_pmd is on different PMD page table.
654 */
655 return new_pmd_ptl != old_pmd_ptl;
656}
657#endif
658
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659/*
660 * This function is meant to be used by sites walking pagetables with
661 * the mmap_sem hold in read mode to protect against MADV_DONTNEED and
662 * transhuge page faults. MADV_DONTNEED can convert a transhuge pmd
663 * into a null pmd and the transhuge page fault can convert a null pmd
664 * into an hugepmd or into a regular pmd (if the hugepage allocation
665 * fails). While holding the mmap_sem in read mode the pmd becomes
666 * stable and stops changing under us only if it's not null and not a
667 * transhuge pmd. When those races occurs and this function makes a
668 * difference vs the standard pmd_none_or_clear_bad, the result is
669 * undefined so behaving like if the pmd was none is safe (because it
670 * can return none anyway). The compiler level barrier() is critically
671 * important to compute the two checks atomically on the same pmdval.
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672 *
673 * For 32bit kernels with a 64bit large pmd_t this automatically takes
674 * care of reading the pmd atomically to avoid SMP race conditions
675 * against pmd_populate() when the mmap_sem is hold for reading by the
676 * caller (a special atomic read not done by "gcc" as in the generic
677 * version above, is also needed when THP is disabled because the page
678 * fault can populate the pmd from under us).
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679 */
680static inline int pmd_none_or_trans_huge_or_clear_bad(pmd_t *pmd)
681{
26c19178 682 pmd_t pmdval = pmd_read_atomic(pmd);
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683 /*
684 * The barrier will stabilize the pmdval in a register or on
685 * the stack so that it will stop changing under the code.
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686 *
687 * When CONFIG_TRANSPARENT_HUGEPAGE=y on x86 32bit PAE,
688 * pmd_read_atomic is allowed to return a not atomic pmdval
689 * (for example pointing to an hugepage that has never been
690 * mapped in the pmd). The below checks will only care about
691 * the low part of the pmd with 32bit PAE x86 anyway, with the
692 * exception of pmd_none(). So the important thing is that if
693 * the low part of the pmd is found null, the high part will
694 * be also null or the pmd_none() check below would be
695 * confused.
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696 */
697#ifdef CONFIG_TRANSPARENT_HUGEPAGE
698 barrier();
699#endif
ee53664b 700 if (pmd_none(pmdval) || pmd_trans_huge(pmdval))
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701 return 1;
702 if (unlikely(pmd_bad(pmdval))) {
ee53664b 703 pmd_clear_bad(pmd);
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704 return 1;
705 }
706 return 0;
707}
708
709/*
710 * This is a noop if Transparent Hugepage Support is not built into
711 * the kernel. Otherwise it is equivalent to
712 * pmd_none_or_trans_huge_or_clear_bad(), and shall only be called in
713 * places that already verified the pmd is not none and they want to
714 * walk ptes while holding the mmap sem in read mode (write mode don't
715 * need this). If THP is not enabled, the pmd can't go away under the
716 * code even if MADV_DONTNEED runs, but if THP is enabled we need to
717 * run a pmd_trans_unstable before walking the ptes after
718 * split_huge_page_pmd returns (because it may have run when the pmd
719 * become null, but then a page fault can map in a THP and not a
720 * regular page).
721 */
722static inline int pmd_trans_unstable(pmd_t *pmd)
723{
724#ifdef CONFIG_TRANSPARENT_HUGEPAGE
725 return pmd_none_or_trans_huge_or_clear_bad(pmd);
726#else
727 return 0;
5f6e8da7 728#endif
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729}
730
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731#ifndef CONFIG_NUMA_BALANCING
732/*
733 * Technically a PTE can be PROTNONE even when not doing NUMA balancing but
734 * the only case the kernel cares is for NUMA balancing and is only ever set
735 * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked
736 * _PAGE_PROTNONE so by by default, implement the helper as "always no". It
737 * is the responsibility of the caller to distinguish between PROT_NONE
738 * protections and NUMA hinting fault protections.
739 */
740static inline int pte_protnone(pte_t pte)
741{
742 return 0;
743}
744
745static inline int pmd_protnone(pmd_t pmd)
746{
747 return 0;
748}
749#endif /* CONFIG_NUMA_BALANCING */
750
1a5a9906 751#endif /* CONFIG_MMU */
5f6e8da7 752
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753#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
754int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
755int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
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756int pud_clear_huge(pud_t *pud);
757int pmd_clear_huge(pmd_t *pmd);
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758#else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */
759static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
760{
761 return 0;
762}
763static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
764{
765 return 0;
766}
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767static inline int pud_clear_huge(pud_t *pud)
768{
769 return 0;
770}
771static inline int pmd_clear_huge(pmd_t *pmd)
772{
773 return 0;
774}
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775#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
776
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777#endif /* !__ASSEMBLY__ */
778
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779#ifndef io_remap_pfn_range
780#define io_remap_pfn_range remap_pfn_range
781#endif
782
1da177e4 783#endif /* _ASM_GENERIC_PGTABLE_H */
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