Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* internal Peripherals Register address define */ |
2 | /* CPU: H8/306x */ | |
3 | ||
4 | #if !defined(__REGS_H8306x__) | |
5 | #define __REGS_H8306x__ | |
6 | ||
7 | #if defined(__KERNEL__) | |
8 | ||
9 | #define DASTCR 0xFEE01A | |
10 | #define DADR0 0xFEE09C | |
11 | #define DADR1 0xFEE09D | |
12 | #define DACR 0xFEE09E | |
13 | ||
14 | #define ADDRAH 0xFFFFE0 | |
15 | #define ADDRAL 0xFFFFE1 | |
16 | #define ADDRBH 0xFFFFE2 | |
17 | #define ADDRBL 0xFFFFE3 | |
18 | #define ADDRCH 0xFFFFE4 | |
19 | #define ADDRCL 0xFFFFE5 | |
20 | #define ADDRDH 0xFFFFE6 | |
21 | #define ADDRDL 0xFFFFE7 | |
22 | #define ADCSR 0xFFFFE8 | |
23 | #define ADCR 0xFFFFE9 | |
24 | ||
25 | #define BRCR 0xFEE013 | |
26 | #define ADRCR 0xFEE01E | |
27 | #define CSCR 0xFEE01F | |
28 | #define ABWCR 0xFEE020 | |
29 | #define ASTCR 0xFEE021 | |
30 | #define WCRH 0xFEE022 | |
31 | #define WCRL 0xFEE023 | |
32 | #define BCR 0xFEE024 | |
33 | #define DRCRA 0xFEE026 | |
34 | #define DRCRB 0xFEE027 | |
35 | #define RTMCSR 0xFEE028 | |
36 | #define RTCNT 0xFEE029 | |
37 | #define RTCOR 0xFEE02A | |
38 | ||
39 | #define MAR0AR 0xFFFF20 | |
40 | #define MAR0AE 0xFFFF21 | |
41 | #define MAR0AH 0xFFFF22 | |
42 | #define MAR0AL 0xFFFF23 | |
43 | #define ETCR0AL 0xFFFF24 | |
44 | #define ETCR0AH 0xFFFF25 | |
45 | #define IOAR0A 0xFFFF26 | |
46 | #define DTCR0A 0xFFFF27 | |
47 | #define MAR0BR 0xFFFF28 | |
48 | #define MAR0BE 0xFFFF29 | |
49 | #define MAR0BH 0xFFFF2A | |
50 | #define MAR0BL 0xFFFF2B | |
51 | #define ETCR0BL 0xFFFF2C | |
52 | #define ETCR0BH 0xFFFF2D | |
53 | #define IOAR0B 0xFFFF2E | |
54 | #define DTCR0B 0xFFFF2F | |
55 | #define MAR1AR 0xFFFF30 | |
56 | #define MAR1AE 0xFFFF31 | |
57 | #define MAR1AH 0xFFFF32 | |
58 | #define MAR1AL 0xFFFF33 | |
59 | #define ETCR1AL 0xFFFF34 | |
60 | #define ETCR1AH 0xFFFF35 | |
61 | #define IOAR1A 0xFFFF36 | |
62 | #define DTCR1A 0xFFFF37 | |
63 | #define MAR1BR 0xFFFF38 | |
64 | #define MAR1BE 0xFFFF39 | |
65 | #define MAR1BH 0xFFFF3A | |
66 | #define MAR1BL 0xFFFF3B | |
67 | #define ETCR1BL 0xFFFF3C | |
68 | #define ETCR1BH 0xFFFF3D | |
69 | #define IOAR1B 0xFFFF3E | |
70 | #define DTCR1B 0xFFFF3F | |
71 | ||
72 | #define ISCR 0xFEE014 | |
73 | #define IER 0xFEE015 | |
74 | #define ISR 0xFEE016 | |
75 | #define IPRA 0xFEE018 | |
76 | #define IPRB 0xFEE019 | |
77 | ||
78 | #define P1DDR 0xFEE000 | |
79 | #define P2DDR 0xFEE001 | |
80 | #define P3DDR 0xFEE002 | |
81 | #define P4DDR 0xFEE003 | |
82 | #define P5DDR 0xFEE004 | |
83 | #define P6DDR 0xFEE005 | |
84 | /*#define P7DDR 0xFEE006*/ | |
85 | #define P8DDR 0xFEE007 | |
86 | #define P9DDR 0xFEE008 | |
87 | #define PADDR 0xFEE009 | |
88 | #define PBDDR 0xFEE00A | |
89 | ||
90 | #define P1DR 0xFFFFD0 | |
91 | #define P2DR 0xFFFFD1 | |
92 | #define P3DR 0xFFFFD2 | |
93 | #define P4DR 0xFFFFD3 | |
94 | #define P5DR 0xFFFFD4 | |
95 | #define P6DR 0xFFFFD5 | |
96 | /*#define P7DR 0xFFFFD6*/ | |
97 | #define P8DR 0xFFFFD7 | |
98 | #define P9DR 0xFFFFD8 | |
99 | #define PADR 0xFFFFD9 | |
100 | #define PBDR 0xFFFFDA | |
101 | ||
102 | #define P2CR 0xFEE03C | |
103 | #define P4CR 0xFEE03E | |
104 | #define P5CR 0xFEE03F | |
105 | ||
106 | #define SMR0 0xFFFFB0 | |
107 | #define BRR0 0xFFFFB1 | |
108 | #define SCR0 0xFFFFB2 | |
109 | #define TDR0 0xFFFFB3 | |
110 | #define SSR0 0xFFFFB4 | |
111 | #define RDR0 0xFFFFB5 | |
112 | #define SCMR0 0xFFFFB6 | |
113 | #define SMR1 0xFFFFB8 | |
114 | #define BRR1 0xFFFFB9 | |
115 | #define SCR1 0xFFFFBA | |
116 | #define TDR1 0xFFFFBB | |
117 | #define SSR1 0xFFFFBC | |
118 | #define RDR1 0xFFFFBD | |
119 | #define SCMR1 0xFFFFBE | |
120 | #define SMR2 0xFFFFC0 | |
121 | #define BRR2 0xFFFFC1 | |
122 | #define SCR2 0xFFFFC2 | |
123 | #define TDR2 0xFFFFC3 | |
124 | #define SSR2 0xFFFFC4 | |
125 | #define RDR2 0xFFFFC5 | |
126 | #define SCMR2 0xFFFFC6 | |
127 | ||
128 | #define MDCR 0xFEE011 | |
129 | #define SYSCR 0xFEE012 | |
130 | #define DIVCR 0xFEE01B | |
131 | #define MSTCRH 0xFEE01C | |
132 | #define MSTCRL 0xFEE01D | |
133 | #define FLMCR1 0xFEE030 | |
134 | #define FLMCR2 0xFEE031 | |
135 | #define EBR1 0xFEE032 | |
136 | #define EBR2 0xFEE033 | |
137 | #define RAMCR 0xFEE077 | |
138 | ||
139 | #define TSTR 0xFFFF60 | |
140 | #define TSNC 0XFFFF61 | |
141 | #define TMDR 0xFFFF62 | |
142 | #define TOLR 0xFFFF63 | |
143 | #define TISRA 0xFFFF64 | |
144 | #define TISRB 0xFFFF65 | |
145 | #define TISRC 0xFFFF66 | |
146 | #define TCR0 0xFFFF68 | |
147 | #define TIOR0 0xFFFF69 | |
148 | #define TCNT0H 0xFFFF6A | |
149 | #define TCNT0L 0xFFFF6B | |
150 | #define GRA0H 0xFFFF6C | |
151 | #define GRA0L 0xFFFF6D | |
152 | #define GRB0H 0xFFFF6E | |
153 | #define GRB0L 0xFFFF6F | |
154 | #define TCR1 0xFFFF70 | |
155 | #define TIOR1 0xFFFF71 | |
156 | #define TCNT1H 0xFFFF72 | |
157 | #define TCNT1L 0xFFFF73 | |
158 | #define GRA1H 0xFFFF74 | |
159 | #define GRA1L 0xFFFF75 | |
160 | #define GRB1H 0xFFFF76 | |
161 | #define GRB1L 0xFFFF77 | |
162 | #define TCR3 0xFFFF78 | |
163 | #define TIOR3 0xFFFF79 | |
164 | #define TCNT3H 0xFFFF7A | |
165 | #define TCNT3L 0xFFFF7B | |
166 | #define GRA3H 0xFFFF7C | |
167 | #define GRA3L 0xFFFF7D | |
168 | #define GRB3H 0xFFFF7E | |
169 | #define GRB3L 0xFFFF7F | |
170 | ||
171 | #define _8TCR0 0xFFFF80 | |
172 | #define _8TCR1 0xFFFF81 | |
173 | #define _8TCSR0 0xFFFF82 | |
174 | #define _8TCSR1 0xFFFF83 | |
175 | #define TCORA0 0xFFFF84 | |
176 | #define TCORA1 0xFFFF85 | |
177 | #define TCORB0 0xFFFF86 | |
178 | #define TCORB1 0xFFFF87 | |
179 | #define _8TCNT0 0xFFFF88 | |
180 | #define _8TCNT1 0xFFFF89 | |
181 | ||
182 | #define _8TCR2 0xFFFF90 | |
183 | #define _8TCR3 0xFFFF91 | |
184 | #define _8TCSR2 0xFFFF92 | |
185 | #define _8TCSR3 0xFFFF93 | |
186 | #define TCORA2 0xFFFF94 | |
187 | #define TCORA3 0xFFFF95 | |
188 | #define TCORB2 0xFFFF96 | |
189 | #define TCORB3 0xFFFF97 | |
190 | #define _8TCNT2 0xFFFF98 | |
191 | #define _8TCNT3 0xFFFF99 | |
192 | ||
193 | #define TCSR 0xFFFF8C | |
194 | #define TCNT 0xFFFF8D | |
195 | #define RSTCSR 0xFFFF8F | |
196 | ||
197 | #define TPMR 0xFFFFA0 | |
198 | #define TPCR 0xFFFFA1 | |
199 | #define NDERB 0xFFFFA2 | |
200 | #define NDERA 0xFFFFA3 | |
201 | #define NDRB1 0xFFFFA4 | |
202 | #define NDRA1 0xFFFFA5 | |
203 | #define NDRB2 0xFFFFA6 | |
204 | #define NDRA2 0xFFFFA7 | |
205 | ||
206 | #define TCSR 0xFFFF8C | |
207 | #define TCNT 0xFFFF8D | |
208 | #define RSTCSRW 0xFFFF8E | |
209 | #define RSTCSRR 0xFFFF8F | |
210 | ||
211 | #endif /* __KERNEL__ */ | |
212 | #endif /* __REGS_H8306x__ */ |