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[PATCH] i386: Fix double #includes in arch/i386
[deliverable/linux.git] / include / asm-i386 / processor.h
CommitLineData
1da177e4
LT		 1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
1da177e4
LT		 20#include <linux/threads.h>
21#include <asm/percpu.h>
1e9f28fa 22#include <linux/cpumask.h>
1da177e4
LT		 23
24/* flag for disabling the tsc */
25extern int tsc_disable;
26
27struct desc_struct {
28 unsigned long a,b;
29};
30
31#define desc_empty(desc) \
12aaa085 32 (!((desc)->a | (desc)->b))
1da177e4
LT		 33
34#define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36/*
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
39 */
40#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
41
42/*
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
46 */
47
48struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
3f98bc49
AK		 64 char fdiv_bug;
65 char f00f_bug;
66 char coma_bug;
67 char pad0;
68 int x86_power;
1da177e4 69 unsigned long loops_per_jiffy;
1e9f28fa
SS		 70#ifdef CONFIG_SMP
71 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
72#endif
94605eff 73 unsigned char x86_max_cores; /* cpuid returned max cores value */
94605eff 74 unsigned char apicid;
770d132f 75 unsigned short x86_clflush_size;
4b89aff9
RS		 76#ifdef CONFIG_SMP
77 unsigned char booted_cores; /* number of cores as seen by OS */
78 __u8 phys_proc_id; /* Physical processor id. */
79 __u8 cpu_core_id; /* Core id */
80#endif
1da177e4
LT		 81} __attribute__((__aligned__(SMP_CACHE_BYTES)));
82
83#define X86_VENDOR_INTEL 0
84#define X86_VENDOR_CYRIX 1
85#define X86_VENDOR_AMD 2
86#define X86_VENDOR_UMC 3
87#define X86_VENDOR_NEXGEN 4
88#define X86_VENDOR_CENTAUR 5
89#define X86_VENDOR_RISE 6
90#define X86_VENDOR_TRANSMETA 7
91#define X86_VENDOR_NSC 8
92#define X86_VENDOR_NUM 9
93#define X86_VENDOR_UNKNOWN 0xff
94
95/*
96 * capabilities of CPUs
97 */
98
99extern struct cpuinfo_x86 boot_cpu_data;
100extern struct cpuinfo_x86 new_cpu_data;
101extern struct tss_struct doublefault_tss;
102DECLARE_PER_CPU(struct tss_struct, init_tss);
103
104#ifdef CONFIG_SMP
105extern struct cpuinfo_x86 cpu_data[];
106#define current_cpu_data cpu_data[smp_processor_id()]
107#else
108#define cpu_data (&boot_cpu_data)
109#define current_cpu_data boot_cpu_data
110#endif
111
1e9f28fa 112extern int cpu_llc_id[NR_CPUS];
1da177e4
LT		 113extern char ignore_fpu_irq;
114
115extern void identify_cpu(struct cpuinfo_x86 *);
116extern void print_cpu_info(struct cpuinfo_x86 *);
117extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
240cd6a8 118extern unsigned short num_cache_leaves;
1da177e4
LT		 119
120#ifdef CONFIG_X86_HT
121extern void detect_ht(struct cpuinfo_x86 *c);
122#else
123static inline void detect_ht(struct cpuinfo_x86 *c) {}
124#endif
125
126/*
127 * EFLAGS bits
128 */
129#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
130#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
131#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
132#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
133#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
134#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
135#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
136#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
137#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
138#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
139#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
140#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
141#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
142#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
143#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
144#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
145#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
146
9f093394
RR		 147static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
148 unsigned int *ecx, unsigned int *edx)
149{
150 /* ecx is often an input as well as an output. */
151 __asm__("cpuid"
152 : "=a" (*eax),
153 "=b" (*ebx),
154 "=c" (*ecx),
155 "=d" (*edx)
156 : "0" (*eax), "2" (*ecx));
157}
158
1da177e4
LT		 159/*
160 * Generic CPUID function
161 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
162 * resulting in stale register contents being returned.
163 */
164static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
165{
9f093394
RR		 166 *eax = op;
167 *ecx = 0;
168 __cpuid(eax, ebx, ecx, edx);
1da177e4
LT		 169}
170
171/* Some CPUID calls want 'count' to be placed in ecx */
172static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
9f093394 173 int *edx)
1da177e4 174{
9f093394
RR		 175 *eax = op;
176 *ecx = count;
177 __cpuid(eax, ebx, ecx, edx);
1da177e4
LT		 178}
179
180/*
181 * CPUID functions returning a single datum
182 */
183static inline unsigned int cpuid_eax(unsigned int op)
184{
9f093394 185 unsigned int eax, ebx, ecx, edx;
1da177e4 186
9f093394 187 cpuid(op, &eax, &ebx, &ecx, &edx);
1da177e4
LT		 188 return eax;
189}
190static inline unsigned int cpuid_ebx(unsigned int op)
191{
9f093394 192 unsigned int eax, ebx, ecx, edx;
1da177e4 193
9f093394 194 cpuid(op, &eax, &ebx, &ecx, &edx);
1da177e4
LT		 195 return ebx;
196}
197static inline unsigned int cpuid_ecx(unsigned int op)
198{
9f093394 199 unsigned int eax, ebx, ecx, edx;
1da177e4 200
9f093394 201 cpuid(op, &eax, &ebx, &ecx, &edx);
1da177e4
LT		 202 return ecx;
203}
204static inline unsigned int cpuid_edx(unsigned int op)
205{
9f093394 206 unsigned int eax, ebx, ecx, edx;
1da177e4 207
9f093394 208 cpuid(op, &eax, &ebx, &ecx, &edx);
1da177e4
LT		 209 return edx;
210}
211
4bb0d3ec 212#define load_cr3(pgdir) write_cr3(__pa(pgdir))
1da177e4
LT		 213
214/*
215 * Intel CPU features in CR4
216 */
217#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
218#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
219#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
220#define X86_CR4_DE 0x0008 /* enable debugging extensions */
221#define X86_CR4_PSE 0x0010 /* enable page size extensions */
222#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
223#define X86_CR4_MCE 0x0040 /* Machine check enable */
224#define X86_CR4_PGE 0x0080 /* enable global pages */
225#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
226#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
227#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
228
229/*
230 * Save the cr4 feature set we're using (ie
231 * Pentium 4MB enable and PPro Global page
232 * enable), so that any CPU's that boot up
233 * after us can get the correct flags.
234 */
235extern unsigned long mmu_cr4_features;
236
237static inline void set_in_cr4 (unsigned long mask)
238{
4bb0d3ec 239 unsigned cr4;
1da177e4 240 mmu_cr4_features |= mask;
4bb0d3ec
ZA		 241 cr4 = read_cr4();
242 cr4 |= mask;
243 write_cr4(cr4);
1da177e4
LT		 244}
245
246static inline void clear_in_cr4 (unsigned long mask)
247{
4bb0d3ec 248 unsigned cr4;
1da177e4 249 mmu_cr4_features &= ~mask;
4bb0d3ec
ZA		 250 cr4 = read_cr4();
251 cr4 &= ~mask;
252 write_cr4(cr4);
1da177e4
LT		 253}
254
255/*
256 * NSC/Cyrix CPU configuration register indexes
257 */
258
259#define CX86_PCR0 0x20
260#define CX86_GCR 0xb8
261#define CX86_CCR0 0xc0
262#define CX86_CCR1 0xc1
263#define CX86_CCR2 0xc2
264#define CX86_CCR3 0xc3
265#define CX86_CCR4 0xe8
266#define CX86_CCR5 0xe9
267#define CX86_CCR6 0xea
268#define CX86_CCR7 0xeb
269#define CX86_PCR1 0xf0
270#define CX86_DIR0 0xfe
271#define CX86_DIR1 0xff
272#define CX86_ARR_BASE 0xc4
273#define CX86_RCR_BASE 0xdc
274
275/*
276 * NSC/Cyrix CPU indexed register access macros
277 */
278
279#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
280
281#define setCx86(reg, data) do { \
282 outb((reg), 0x22); \
283 outb((data), 0x23); \
284} while (0)
285
487472bc
AK		 286/* Stop speculative execution */
287static inline void sync_core(void)
245067d1 288{
487472bc
AK		 289 int tmp;
290 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
245067d1
ZA		 291}
292
1da177e4
LT		 293static inline void __monitor(const void *eax, unsigned long ecx,
294 unsigned long edx)
295{
296 /* "monitor %eax,%ecx,%edx;" */
297 asm volatile(
298 ".byte 0x0f,0x01,0xc8;"
299 : :"a" (eax), "c" (ecx), "d"(edx));
300}
301
302static inline void __mwait(unsigned long eax, unsigned long ecx)
303{
304 /* "mwait %eax,%ecx;" */
305 asm volatile(
306 ".byte 0x0f,0x01,0xc9;"
307 : :"a" (eax), "c" (ecx));
308}
309
991528d7
VP		 310extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
311
1da177e4
LT		 312/* from system description table in BIOS. Mostly for MCA use, but
313others may find it useful. */
314extern unsigned int machine_id;
315extern unsigned int machine_submodel_id;
316extern unsigned int BIOS_revision;
317extern unsigned int mca_pentium_flag;
318
319/* Boot loader type from the setup header */
320extern int bootloader_type;
321
322/*
323 * User space process size: 3GB (default).
324 */
325#define TASK_SIZE (PAGE_OFFSET)
326
327/* This decides where the kernel will search for a free chunk of vm
328 * space during mmap's.
329 */
330#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
331
332#define HAVE_ARCH_PICK_MMAP_LAYOUT
333
334/*
335 * Size of io_bitmap.
336 */
337#define IO_BITMAP_BITS 65536
338#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
339#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
340#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
341#define INVALID_IO_BITMAP_OFFSET 0x8000
342#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
343
344struct i387_fsave_struct {
345 long cwd;
346 long swd;
347 long twd;
348 long fip;
349 long fcs;
350 long foo;
351 long fos;
352 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
353 long status; /* software status information */
354};
355
356struct i387_fxsave_struct {
357 unsigned short cwd;
358 unsigned short swd;
359 unsigned short twd;
360 unsigned short fop;
361 long fip;
362 long fcs;
363 long foo;
364 long fos;
365 long mxcsr;
366 long mxcsr_mask;
367 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
368 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
369 long padding[56];
370} __attribute__ ((aligned (16)));
371
372struct i387_soft_struct {
373 long cwd;
374 long swd;
375 long twd;
376 long fip;
377 long fcs;
378 long foo;
379 long fos;
380 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
381 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
382 struct info *info;
383 unsigned long entry_eip;
384};
385
386union i387_union {
387 struct i387_fsave_struct fsave;
388 struct i387_fxsave_struct fxsave;
389 struct i387_soft_struct soft;
390};
391
392typedef struct {
393 unsigned long seg;
394} mm_segment_t;
395
396struct thread_struct;
397
398struct tss_struct {
399 unsigned short back_link,__blh;
400 unsigned long esp0;
401 unsigned short ss0,__ss0h;
402 unsigned long esp1;
403 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
404 unsigned long esp2;
405 unsigned short ss2,__ss2h;
406 unsigned long __cr3;
407 unsigned long eip;
408 unsigned long eflags;
409 unsigned long eax,ecx,edx,ebx;
410 unsigned long esp;
411 unsigned long ebp;
412 unsigned long esi;
413 unsigned long edi;
414 unsigned short es, __esh;
415 unsigned short cs, __csh;
416 unsigned short ss, __ssh;
417 unsigned short ds, __dsh;
418 unsigned short fs, __fsh;
419 unsigned short gs, __gsh;
420 unsigned short ldt, __ldth;
421 unsigned short trace, io_bitmap_base;
422 /*
423 * The extra 1 is there because the CPU will access an
424 * additional byte beyond the end of the IO permission
425 * bitmap. The extra byte must be all 1 bits, and must
426 * be within the limit.
427 */
428 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
429 /*
430 * Cache the current maximum and the last task that used the bitmap:
431 */
432 unsigned long io_bitmap_max;
433 struct thread_struct *io_bitmap_owner;
434 /*
435 * pads the TSS to be cacheline-aligned (size is 0x100)
436 */
437 unsigned long __cacheline_filler[35];
438 /*
439 * .. and then another 0x100 bytes for emergency kernel stack
440 */
441 unsigned long stack[64];
442} __attribute__((packed));
443
444#define ARCH_MIN_TASKALIGN 16
445
446struct thread_struct {
447/* cached TLS descriptors. */
448 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
449 unsigned long esp0;
450 unsigned long sysenter_cs;
451 unsigned long eip;
452 unsigned long esp;
453 unsigned long fs;
454 unsigned long gs;
455/* Hardware debugging registers */
456 unsigned long debugreg[8]; /* %%db0-7 debug registers */
457/* fault info */
458 unsigned long cr2, trap_no, error_code;
459/* floating point info */
460 union i387_union i387;
461/* virtual 86 mode info */
462 struct vm86_struct __user * vm86_info;
463 unsigned long screen_bitmap;
464 unsigned long v86flags, v86mask, saved_esp0;
465 unsigned int saved_fs, saved_gs;
466/* IO permissions */
467 unsigned long *io_bitmap_ptr;
a5201129 468 unsigned long iopl;
1da177e4
LT		 469/* max allowed port in the bitmap, in bytes: */
470 unsigned long io_bitmap_max;
471};
472
473#define INIT_THREAD { \
474 .vm86_info = NULL, \
475 .sysenter_cs = __KERNEL_CS, \
476 .io_bitmap_ptr = NULL, \
f95d47ca 477 .gs = __KERNEL_PDA, \
1da177e4
LT		 478}
479
480/*
481 * Note that the .io_bitmap member must be extra-big. This is because
482 * the CPU will access an additional byte beyond the end of the IO
483 * permission bitmap. The extra byte must be all 1 bits, and must
484 * be within the limit.
485 */
486#define INIT_TSS { \
487 .esp0 = sizeof(init_stack) + (long)&init_stack, \
488 .ss0 = __KERNEL_DS, \
489 .ss1 = __KERNEL_CS, \
1da177e4
LT		 490 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
491 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
492}
493
494static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
495{
496 tss->esp0 = thread->esp0;
497 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
498 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
499 tss->ss1 = thread->sysenter_cs;
500 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
501 }
502}
503
504#define start_thread(regs, new_eip, new_esp) do { \
f95d47ca
JF		 505 __asm__("movl %0,%%fs": :"r" (0)); \
506 regs->xgs = 0; \
1da177e4
LT		 507 set_fs(USER_DS); \
508 regs->xds = __USER_DS; \
509 regs->xes = __USER_DS; \
510 regs->xss = __USER_DS; \
511 regs->xcs = __USER_CS; \
512 regs->eip = new_eip; \
513 regs->esp = new_esp; \
514} while (0)
515
ecd02ddd 516/*
f5012310 517 * These special macros can be used to get or set a debugging register
ecd02ddd 518 */
f5012310
VH		 519#define get_debugreg(var, register) \
520 __asm__("movl %%db" #register ", %0" \
521 :"=r" (var))
522#define set_debugreg(value, register) \
523 __asm__("movl %0,%%db" #register \
524 : /* no output */ \
525 :"r" (value))
526
a5201129
ZA		 527/*
528 * Set IOPL bits in EFLAGS from given mask
529 */
530static inline void set_iopl_mask(unsigned mask)
531{
532 unsigned int reg;
533 __asm__ __volatile__ ("pushfl;"
534 "popl %0;"
535 "andl %1, %0;"
536 "orl %2, %0;"
537 "pushl %0;"
538 "popfl"
539 : "=&r" (reg)
540 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
541}
ecd02ddd 542
1da177e4
LT		 543/* Forward declaration, a strange C thing */
544struct task_struct;
545struct mm_struct;
546
547/* Free all resources held by a thread. */
548extern void release_thread(struct task_struct *);
549
550/* Prepare to copy thread state - unlazy all lazy status */
551extern void prepare_to_copy(struct task_struct *tsk);
552
553/*
554 * create a kernel thread without removing it from tasklists
555 */
556extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
557
558extern unsigned long thread_saved_pc(struct task_struct *tsk);
176a2718 559void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
1da177e4
LT		 560
561unsigned long get_wchan(struct task_struct *p);
562
563#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
564#define KSTK_TOP(info) \
565({ \
566 unsigned long *__ptr = (unsigned long *)(info); \
567 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
568})
569
07b047fc 570/*
571 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
572 * This is necessary to guarantee that the entire "struct pt_regs"
573 * is accessable even if the CPU haven't stored the SS/ESP registers
574 * on the stack (interrupt gate does not save these registers
575 * when switching to the same priv ring).
576 * Therefore beware: accessing the xss/esp fields of the
577 * "struct pt_regs" is possible, but they may contain the
578 * completely wrong values.
579 */
1da177e4
LT		 580#define task_pt_regs(task) \
581({ \
582 struct pt_regs *__regs__; \
65e0fdff 583 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
1da177e4
LT		 584 __regs__ - 1; \
585})
586
587#define KSTK_EIP(task) (task_pt_regs(task)->eip)
588#define KSTK_ESP(task) (task_pt_regs(task)->esp)
589
590
591struct microcode_header {
592 unsigned int hdrver;
593 unsigned int rev;
594 unsigned int date;
595 unsigned int sig;
596 unsigned int cksum;
597 unsigned int ldrver;
598 unsigned int pf;
599 unsigned int datasize;
600 unsigned int totalsize;
601 unsigned int reserved[3];
602};
603
604struct microcode {
605 struct microcode_header hdr;
606 unsigned int bits[0];
607};
608
609typedef struct microcode microcode_t;
610typedef struct microcode_header microcode_header_t;
611
612/* microcode format is extended from prescott processors */
613struct extended_signature {
614 unsigned int sig;
615 unsigned int pf;
616 unsigned int cksum;
617};
618
619struct extended_sigtable {
620 unsigned int count;
621 unsigned int cksum;
622 unsigned int reserved[3];
623 struct extended_signature sigs[0];
624};
1da177e4
LT		 625
626/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
627static inline void rep_nop(void)
628{
629 __asm__ __volatile__("rep;nop": : :"memory");
630}
631
632#define cpu_relax() rep_nop()
633
634/* generic versions from gas */
635#define GENERIC_NOP1 ".byte 0x90\n"
636#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
637#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
638#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
639#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
640#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
641#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
642#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
643
644/* Opteron nops */
645#define K8_NOP1 GENERIC_NOP1
646#define K8_NOP2 ".byte 0x66,0x90\n"
647#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
648#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
649#define K8_NOP5 K8_NOP3 K8_NOP2
650#define K8_NOP6 K8_NOP3 K8_NOP3
651#define K8_NOP7 K8_NOP4 K8_NOP3
652#define K8_NOP8 K8_NOP4 K8_NOP4
653
654/* K7 nops */
655/* uses eax dependencies (arbitary choice) */
656#define K7_NOP1 GENERIC_NOP1
657#define K7_NOP2 ".byte 0x8b,0xc0\n"
658#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
659#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
660#define K7_NOP5 K7_NOP4 ASM_NOP1
661#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
662#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
663#define K7_NOP8 K7_NOP7 ASM_NOP1
664
665#ifdef CONFIG_MK8
666#define ASM_NOP1 K8_NOP1
667#define ASM_NOP2 K8_NOP2
668#define ASM_NOP3 K8_NOP3
669#define ASM_NOP4 K8_NOP4
670#define ASM_NOP5 K8_NOP5
671#define ASM_NOP6 K8_NOP6
672#define ASM_NOP7 K8_NOP7
673#define ASM_NOP8 K8_NOP8
674#elif defined(CONFIG_MK7)
675#define ASM_NOP1 K7_NOP1
676#define ASM_NOP2 K7_NOP2
677#define ASM_NOP3 K7_NOP3
678#define ASM_NOP4 K7_NOP4
679#define ASM_NOP5 K7_NOP5
680#define ASM_NOP6 K7_NOP6
681#define ASM_NOP7 K7_NOP7
682#define ASM_NOP8 K7_NOP8
683#else
684#define ASM_NOP1 GENERIC_NOP1
685#define ASM_NOP2 GENERIC_NOP2
686#define ASM_NOP3 GENERIC_NOP3
687#define ASM_NOP4 GENERIC_NOP4
688#define ASM_NOP5 GENERIC_NOP5
689#define ASM_NOP6 GENERIC_NOP6
690#define ASM_NOP7 GENERIC_NOP7
691#define ASM_NOP8 GENERIC_NOP8
692#endif
693
694#define ASM_NOP_MAX 8
695
696/* Prefetch instructions for Pentium III and AMD Athlon */
697/* It's not worth to care about 3dnow! prefetches for the K6
698 because they are microcoded there and very slow.
699 However we don't do prefetches for pre XP Athlons currently
700 That should be fixed. */
701#define ARCH_HAS_PREFETCH
e2afe674 702static inline void prefetch(const void *x)
1da177e4
LT		 703{
704 alternative_input(ASM_NOP4,
705 "prefetchnta (%1)",
706 X86_FEATURE_XMM,
707 "r" (x));
708}
709
710#define ARCH_HAS_PREFETCH
711#define ARCH_HAS_PREFETCHW
712#define ARCH_HAS_SPINLOCK_PREFETCH
713
714/* 3dnow! prefetch to get an exclusive cache line. Useful for
715 spinlocks to avoid one state transition in the cache coherency protocol. */
e2afe674 716static inline void prefetchw(const void *x)
1da177e4
LT		 717{
718 alternative_input(ASM_NOP4,
719 "prefetchw (%1)",
720 X86_FEATURE_3DNOW,
721 "r" (x));
722}
723#define spin_lock_prefetch(x) prefetchw(x)
724
725extern void select_idle_routine(const struct cpuinfo_x86 *c);
726
727#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
728
729extern unsigned long boot_option_idle_override;
6fe940d6
LS		 730extern void enable_sep_cpu(void);
731extern int sysenter_setup(void);
1da177e4 732
62111195
JF		 733extern int init_gdt(int cpu, struct task_struct *idle);
734extern void secondary_cpu_init(void);
735
1da177e4 736#endif /* __ASM_I386_PROCESSOR_H */
Linux kernel - Deliverables
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