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1da177e4 LT |
1 | #ifndef _ASM_IA64_PAL_H |
2 | #define _ASM_IA64_PAL_H | |
3 | ||
4 | /* | |
5 | * Processor Abstraction Layer definitions. | |
6 | * | |
7 | * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0 | |
8 | * chapter 11 IA-64 Processor Abstraction Layer | |
9 | * | |
10 | * Copyright (C) 1998-2001 Hewlett-Packard Co | |
11 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
12 | * Stephane Eranian <eranian@hpl.hp.com> | |
13 | * Copyright (C) 1999 VA Linux Systems | |
14 | * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
15 | * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> | |
c19b2930 | 16 | * Copyright (C) 2008 Silicon Graphics, Inc. (SGI) |
1da177e4 LT |
17 | * |
18 | * 99/10/01 davidm Make sure we pass zero for reserved parameters. | |
19 | * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6. | |
20 | * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info | |
21 | * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added | |
22 | * 00/05/25 eranian Support for stack calls, and static physical calls | |
23 | * 00/06/18 eranian Support for stacked physical calls | |
5b4d5681 RA |
24 | * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's |
25 | * Manual Rev 2.2 (Jan 2006) | |
1da177e4 LT |
26 | */ |
27 | ||
28 | /* | |
29 | * Note that some of these calls use a static-register only calling | |
30 | * convention which has nothing to do with the regular calling | |
31 | * convention. | |
32 | */ | |
33 | #define PAL_CACHE_FLUSH 1 /* flush i/d cache */ | |
34 | #define PAL_CACHE_INFO 2 /* get detailed i/d cache info */ | |
35 | #define PAL_CACHE_INIT 3 /* initialize i/d cache */ | |
1b3c3714 | 36 | #define PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */ |
1da177e4 LT |
37 | #define PAL_MEM_ATTRIB 5 /* list supported memory attributes */ |
38 | #define PAL_PTCE_INFO 6 /* purge TLB info */ | |
39 | #define PAL_VM_INFO 7 /* return supported virtual memory features */ | |
40 | #define PAL_VM_SUMMARY 8 /* return summary on supported vm features */ | |
41 | #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */ | |
42 | #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */ | |
43 | #define PAL_DEBUG_INFO 11 /* get number of debug registers */ | |
44 | #define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */ | |
45 | #define PAL_FREQ_BASE 13 /* base frequency of the platform */ | |
46 | #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */ | |
47 | #define PAL_PERF_MON_INFO 15 /* return performance monitor info */ | |
48 | #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */ | |
49 | #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */ | |
50 | #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */ | |
51 | #define PAL_RSE_INFO 19 /* return rse information */ | |
52 | #define PAL_VERSION 20 /* return version of PAL code */ | |
53 | #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */ | |
54 | #define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */ | |
55 | #define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */ | |
56 | #define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */ | |
57 | #define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */ | |
58 | #define PAL_MC_RESUME 26 /* Return to interrupted process */ | |
59 | #define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */ | |
60 | #define PAL_HALT 28 /* enter the low power HALT state */ | |
61 | #define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/ | |
62 | #define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */ | |
63 | #define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */ | |
64 | #define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */ | |
65 | #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */ | |
66 | #define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */ | |
67 | ||
68 | #define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */ | |
69 | #define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */ | |
70 | #define PAL_REGISTER_INFO 39 /* return AR and CR register information*/ | |
71 | #define PAL_SHUTDOWN 40 /* enter processor shutdown state */ | |
72 | #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */ | |
e927ecb0 | 73 | #define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */ |
f1918005 | 74 | #define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */ |
5b4d5681 RA |
75 | #define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */ |
76 | #define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */ | |
c19b2930 RA |
77 | #define PAL_VP_INFO 50 /* Information about virtual processor features */ |
78 | #define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */ | |
1da177e4 LT |
79 | |
80 | #define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ | |
81 | #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */ | |
82 | #define PAL_TEST_PROC 258 /* perform late processor self-test */ | |
83 | #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ | |
84 | #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ | |
85 | #define PAL_VM_TR_READ 261 /* read contents of translation register */ | |
4db8699b VP |
86 | #define PAL_GET_PSTATE 262 /* get the current P-state */ |
87 | #define PAL_SET_PSTATE 263 /* set the P-state */ | |
76d08bb3 | 88 | #define PAL_BRAND_INFO 274 /* Processor branding information */ |
1da177e4 | 89 | |
17e77b1c VP |
90 | #define PAL_GET_PSTATE_TYPE_LASTSET 0 |
91 | #define PAL_GET_PSTATE_TYPE_AVGANDRESET 1 | |
92 | #define PAL_GET_PSTATE_TYPE_AVGNORESET 2 | |
93 | #define PAL_GET_PSTATE_TYPE_INSTANT 3 | |
94 | ||
1138b7e2 FY |
95 | #define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */ |
96 | ||
1da177e4 LT |
97 | #ifndef __ASSEMBLY__ |
98 | ||
99 | #include <linux/types.h> | |
100 | #include <asm/fpu.h> | |
101 | ||
102 | /* | |
103 | * Data types needed to pass information into PAL procedures and | |
104 | * interpret information returned by them. | |
105 | */ | |
106 | ||
107 | /* Return status from the PAL procedure */ | |
108 | typedef s64 pal_status_t; | |
109 | ||
110 | #define PAL_STATUS_SUCCESS 0 /* No error */ | |
111 | #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */ | |
112 | #define PAL_STATUS_EINVAL (-2) /* Invalid argument */ | |
113 | #define PAL_STATUS_ERROR (-3) /* Error */ | |
114 | #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the | |
115 | * specified level and type of | |
116 | * cache without sideeffects | |
117 | * and "restrict" was 1 | |
118 | */ | |
5b4d5681 | 119 | #define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */ |
1da177e4 | 120 | |
1b3c3714 | 121 | /* Processor cache level in the hierarchy */ |
1da177e4 LT |
122 | typedef u64 pal_cache_level_t; |
123 | #define PAL_CACHE_LEVEL_L0 0 /* L0 */ | |
124 | #define PAL_CACHE_LEVEL_L1 1 /* L1 */ | |
125 | #define PAL_CACHE_LEVEL_L2 2 /* L2 */ | |
126 | ||
127 | ||
1b3c3714 | 128 | /* Processor cache type at a particular level in the hierarchy */ |
1da177e4 LT |
129 | |
130 | typedef u64 pal_cache_type_t; | |
131 | #define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */ | |
132 | #define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */ | |
133 | #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */ | |
134 | ||
135 | ||
136 | #define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */ | |
137 | #define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */ | |
138 | ||
139 | /* Processor cache line size in bytes */ | |
140 | typedef int pal_cache_line_size_t; | |
141 | ||
142 | /* Processor cache line state */ | |
143 | typedef u64 pal_cache_line_state_t; | |
144 | #define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */ | |
145 | #define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */ | |
146 | #define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */ | |
147 | #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */ | |
148 | ||
149 | typedef struct pal_freq_ratio { | |
2ab9391d | 150 | u32 den, num; /* numerator & denominator */ |
1da177e4 LT |
151 | } itc_ratio, proc_ratio; |
152 | ||
153 | typedef union pal_cache_config_info_1_s { | |
154 | struct { | |
155 | u64 u : 1, /* 0 Unified cache ? */ | |
156 | at : 2, /* 2-1 Cache mem attr*/ | |
157 | reserved : 5, /* 7-3 Reserved */ | |
158 | associativity : 8, /* 16-8 Associativity*/ | |
159 | line_size : 8, /* 23-17 Line size */ | |
160 | stride : 8, /* 31-24 Stride */ | |
161 | store_latency : 8, /*39-32 Store latency*/ | |
162 | load_latency : 8, /* 47-40 Load latency*/ | |
163 | store_hints : 8, /* 55-48 Store hints*/ | |
164 | load_hints : 8; /* 63-56 Load hints */ | |
165 | } pcci1_bits; | |
166 | u64 pcci1_data; | |
167 | } pal_cache_config_info_1_t; | |
168 | ||
169 | typedef union pal_cache_config_info_2_s { | |
170 | struct { | |
2ab9391d | 171 | u32 cache_size; /*cache size in bytes*/ |
1da177e4 LT |
172 | |
173 | ||
2ab9391d | 174 | u32 alias_boundary : 8, /* 39-32 aliased addr |
1da177e4 LT |
175 | * separation for max |
176 | * performance. | |
177 | */ | |
178 | tag_ls_bit : 8, /* 47-40 LSb of addr*/ | |
179 | tag_ms_bit : 8, /* 55-48 MSb of addr*/ | |
180 | reserved : 8; /* 63-56 Reserved */ | |
181 | } pcci2_bits; | |
182 | u64 pcci2_data; | |
183 | } pal_cache_config_info_2_t; | |
184 | ||
185 | ||
186 | typedef struct pal_cache_config_info_s { | |
187 | pal_status_t pcci_status; | |
188 | pal_cache_config_info_1_t pcci_info_1; | |
189 | pal_cache_config_info_2_t pcci_info_2; | |
190 | u64 pcci_reserved; | |
191 | } pal_cache_config_info_t; | |
192 | ||
193 | #define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints | |
194 | #define pcci_st_hints pcci_info_1.pcci1_bits.store_hints | |
195 | #define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency | |
196 | #define pcci_st_latency pcci_info_1.pcci1_bits.store_latency | |
197 | #define pcci_stride pcci_info_1.pcci1_bits.stride | |
198 | #define pcci_line_size pcci_info_1.pcci1_bits.line_size | |
199 | #define pcci_assoc pcci_info_1.pcci1_bits.associativity | |
200 | #define pcci_cache_attr pcci_info_1.pcci1_bits.at | |
201 | #define pcci_unified pcci_info_1.pcci1_bits.u | |
202 | #define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit | |
203 | #define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit | |
204 | #define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary | |
205 | #define pcci_cache_size pcci_info_2.pcci2_bits.cache_size | |
206 | ||
207 | ||
208 | ||
209 | /* Possible values for cache attributes */ | |
210 | ||
211 | #define PAL_CACHE_ATTR_WT 0 /* Write through cache */ | |
212 | #define PAL_CACHE_ATTR_WB 1 /* Write back cache */ | |
213 | #define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write | |
214 | * back depending on TLB | |
215 | * memory attributes | |
216 | */ | |
217 | ||
218 | ||
219 | /* Possible values for cache hints */ | |
220 | ||
221 | #define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */ | |
222 | #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */ | |
223 | #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */ | |
224 | ||
225 | /* Processor cache protection information */ | |
226 | typedef union pal_cache_protection_element_u { | |
227 | u32 pcpi_data; | |
228 | struct { | |
229 | u32 data_bits : 8, /* # data bits covered by | |
230 | * each unit of protection | |
231 | */ | |
232 | ||
233 | tagprot_lsb : 6, /* Least -do- */ | |
234 | tagprot_msb : 6, /* Most Sig. tag address | |
235 | * bit that this | |
236 | * protection covers. | |
237 | */ | |
238 | prot_bits : 6, /* # of protection bits */ | |
239 | method : 4, /* Protection method */ | |
240 | t_d : 2; /* Indicates which part | |
241 | * of the cache this | |
242 | * protection encoding | |
243 | * applies. | |
244 | */ | |
245 | } pcp_info; | |
246 | } pal_cache_protection_element_t; | |
247 | ||
248 | #define pcpi_cache_prot_part pcp_info.t_d | |
249 | #define pcpi_prot_method pcp_info.method | |
250 | #define pcpi_prot_bits pcp_info.prot_bits | |
251 | #define pcpi_tagprot_msb pcp_info.tagprot_msb | |
252 | #define pcpi_tagprot_lsb pcp_info.tagprot_lsb | |
253 | #define pcpi_data_bits pcp_info.data_bits | |
254 | ||
255 | /* Processor cache part encodings */ | |
256 | #define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */ | |
257 | #define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */ | |
258 | #define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is | |
259 | * more significant ) | |
260 | */ | |
261 | #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is | |
262 | * more significant ) | |
263 | */ | |
264 | #define PAL_CACHE_PROT_PART_MAX 6 | |
265 | ||
266 | ||
267 | typedef struct pal_cache_protection_info_s { | |
268 | pal_status_t pcpi_status; | |
269 | pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX]; | |
270 | } pal_cache_protection_info_t; | |
271 | ||
272 | ||
273 | /* Processor cache protection method encodings */ | |
274 | #define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */ | |
275 | #define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */ | |
276 | #define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */ | |
277 | #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */ | |
278 | ||
279 | ||
1b3c3714 | 280 | /* Processor cache line identification in the hierarchy */ |
1da177e4 LT |
281 | typedef union pal_cache_line_id_u { |
282 | u64 pclid_data; | |
283 | struct { | |
284 | u64 cache_type : 8, /* 7-0 cache type */ | |
285 | level : 8, /* 15-8 level of the | |
286 | * cache in the | |
1b3c3714 | 287 | * hierarchy. |
1da177e4 LT |
288 | */ |
289 | way : 8, /* 23-16 way in the set | |
290 | */ | |
291 | part : 8, /* 31-24 part of the | |
292 | * cache | |
293 | */ | |
294 | reserved : 32; /* 63-32 is reserved*/ | |
295 | } pclid_info_read; | |
296 | struct { | |
297 | u64 cache_type : 8, /* 7-0 cache type */ | |
298 | level : 8, /* 15-8 level of the | |
299 | * cache in the | |
1b3c3714 | 300 | * hierarchy. |
1da177e4 LT |
301 | */ |
302 | way : 8, /* 23-16 way in the set | |
303 | */ | |
304 | part : 8, /* 31-24 part of the | |
305 | * cache | |
306 | */ | |
307 | mesi : 8, /* 39-32 cache line | |
308 | * state | |
309 | */ | |
310 | start : 8, /* 47-40 lsb of data to | |
311 | * invert | |
312 | */ | |
313 | length : 8, /* 55-48 #bits to | |
314 | * invert | |
315 | */ | |
316 | trigger : 8; /* 63-56 Trigger error | |
317 | * by doing a load | |
318 | * after the write | |
319 | */ | |
320 | ||
321 | } pclid_info_write; | |
322 | } pal_cache_line_id_u_t; | |
323 | ||
324 | #define pclid_read_part pclid_info_read.part | |
325 | #define pclid_read_way pclid_info_read.way | |
326 | #define pclid_read_level pclid_info_read.level | |
327 | #define pclid_read_cache_type pclid_info_read.cache_type | |
328 | ||
329 | #define pclid_write_trigger pclid_info_write.trigger | |
330 | #define pclid_write_length pclid_info_write.length | |
331 | #define pclid_write_start pclid_info_write.start | |
332 | #define pclid_write_mesi pclid_info_write.mesi | |
333 | #define pclid_write_part pclid_info_write.part | |
334 | #define pclid_write_way pclid_info_write.way | |
335 | #define pclid_write_level pclid_info_write.level | |
336 | #define pclid_write_cache_type pclid_info_write.cache_type | |
337 | ||
338 | /* Processor cache line part encodings */ | |
339 | #define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */ | |
340 | #define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */ | |
341 | #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */ | |
342 | #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */ | |
343 | #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag | |
344 | * protection | |
345 | */ | |
346 | typedef struct pal_cache_line_info_s { | |
347 | pal_status_t pcli_status; /* Return status of the read cache line | |
348 | * info call. | |
349 | */ | |
350 | u64 pcli_data; /* 64-bit data, tag, protection bits .. */ | |
351 | u64 pcli_data_len; /* data length in bits */ | |
352 | pal_cache_line_state_t pcli_cache_line_state; /* mesi state */ | |
353 | ||
354 | } pal_cache_line_info_t; | |
355 | ||
356 | ||
357 | /* Machine Check related crap */ | |
358 | ||
359 | /* Pending event status bits */ | |
360 | typedef u64 pal_mc_pending_events_t; | |
361 | ||
362 | #define PAL_MC_PENDING_MCA (1 << 0) | |
363 | #define PAL_MC_PENDING_INIT (1 << 1) | |
364 | ||
365 | /* Error information type */ | |
366 | typedef u64 pal_mc_info_index_t; | |
367 | ||
368 | #define PAL_MC_INFO_PROCESSOR 0 /* Processor */ | |
369 | #define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */ | |
370 | #define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */ | |
371 | #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */ | |
372 | #define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */ | |
373 | #define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */ | |
374 | #define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */ | |
375 | #define PAL_MC_INFO_IMPL_DEP 7 /* Implementation | |
376 | * dependent | |
377 | */ | |
378 | ||
618b206f | 379 | #define PAL_TLB_CHECK_OP_PURGE 8 |
1da177e4 LT |
380 | |
381 | typedef struct pal_process_state_info_s { | |
382 | u64 reserved1 : 2, | |
383 | rz : 1, /* PAL_CHECK processor | |
384 | * rendezvous | |
385 | * successful. | |
386 | */ | |
387 | ||
388 | ra : 1, /* PAL_CHECK attempted | |
389 | * a rendezvous. | |
390 | */ | |
391 | me : 1, /* Distinct multiple | |
392 | * errors occurred | |
393 | */ | |
394 | ||
395 | mn : 1, /* Min. state save | |
396 | * area has been | |
397 | * registered with PAL | |
398 | */ | |
399 | ||
400 | sy : 1, /* Storage integrity | |
401 | * synched | |
402 | */ | |
403 | ||
404 | ||
405 | co : 1, /* Continuable */ | |
406 | ci : 1, /* MC isolated */ | |
407 | us : 1, /* Uncontained storage | |
408 | * damage. | |
409 | */ | |
410 | ||
411 | ||
412 | hd : 1, /* Non-essential hw | |
413 | * lost (no loss of | |
414 | * functionality) | |
415 | * causing the | |
416 | * processor to run in | |
417 | * degraded mode. | |
418 | */ | |
419 | ||
420 | tl : 1, /* 1 => MC occurred | |
421 | * after an instr was | |
422 | * executed but before | |
423 | * the trap that | |
424 | * resulted from instr | |
425 | * execution was | |
426 | * generated. | |
427 | * (Trap Lost ) | |
428 | */ | |
429 | mi : 1, /* More information available | |
430 | * call PAL_MC_ERROR_INFO | |
431 | */ | |
432 | pi : 1, /* Precise instruction pointer */ | |
433 | pm : 1, /* Precise min-state save area */ | |
434 | ||
435 | dy : 1, /* Processor dynamic | |
436 | * state valid | |
437 | */ | |
438 | ||
439 | ||
440 | in : 1, /* 0 = MC, 1 = INIT */ | |
441 | rs : 1, /* RSE valid */ | |
442 | cm : 1, /* MC corrected */ | |
443 | ex : 1, /* MC is expected */ | |
444 | cr : 1, /* Control regs valid*/ | |
445 | pc : 1, /* Perf cntrs valid */ | |
446 | dr : 1, /* Debug regs valid */ | |
447 | tr : 1, /* Translation regs | |
448 | * valid | |
449 | */ | |
450 | rr : 1, /* Region regs valid */ | |
451 | ar : 1, /* App regs valid */ | |
452 | br : 1, /* Branch regs valid */ | |
453 | pr : 1, /* Predicate registers | |
454 | * valid | |
455 | */ | |
456 | ||
457 | fp : 1, /* fp registers valid*/ | |
458 | b1 : 1, /* Preserved bank one | |
459 | * general registers | |
460 | * are valid | |
461 | */ | |
462 | b0 : 1, /* Preserved bank zero | |
463 | * general registers | |
464 | * are valid | |
465 | */ | |
466 | gr : 1, /* General registers | |
467 | * are valid | |
468 | * (excl. banked regs) | |
469 | */ | |
470 | dsize : 16, /* size of dynamic | |
471 | * state returned | |
472 | * by the processor | |
473 | */ | |
474 | ||
6533bded RA |
475 | se : 1, /* Shared error. MCA in a |
476 | shared structure */ | |
477 | reserved2 : 10, | |
1da177e4 LT |
478 | cc : 1, /* Cache check */ |
479 | tc : 1, /* TLB check */ | |
480 | bc : 1, /* Bus check */ | |
481 | rc : 1, /* Register file check */ | |
482 | uc : 1; /* Uarch check */ | |
483 | ||
484 | } pal_processor_state_info_t; | |
485 | ||
486 | typedef struct pal_cache_check_info_s { | |
487 | u64 op : 4, /* Type of cache | |
488 | * operation that | |
489 | * caused the machine | |
490 | * check. | |
491 | */ | |
492 | level : 2, /* Cache level */ | |
493 | reserved1 : 2, | |
494 | dl : 1, /* Failure in data part | |
495 | * of cache line | |
496 | */ | |
497 | tl : 1, /* Failure in tag part | |
498 | * of cache line | |
499 | */ | |
500 | dc : 1, /* Failure in dcache */ | |
501 | ic : 1, /* Failure in icache */ | |
502 | mesi : 3, /* Cache line state */ | |
503 | mv : 1, /* mesi valid */ | |
504 | way : 5, /* Way in which the | |
505 | * error occurred | |
506 | */ | |
507 | wiv : 1, /* Way field valid */ | |
323cbb09 RA |
508 | reserved2 : 1, |
509 | dp : 1, /* Data poisoned on MBE */ | |
c19b2930 RA |
510 | reserved3 : 6, |
511 | hlth : 2, /* Health indicator */ | |
1da177e4 LT |
512 | |
513 | index : 20, /* Cache line index */ | |
323cbb09 | 514 | reserved4 : 2, |
1da177e4 LT |
515 | |
516 | is : 1, /* instruction set (1 == ia32) */ | |
517 | iv : 1, /* instruction set field valid */ | |
518 | pl : 2, /* privilege level */ | |
519 | pv : 1, /* privilege level field valid */ | |
520 | mcc : 1, /* Machine check corrected */ | |
521 | tv : 1, /* Target address | |
522 | * structure is valid | |
523 | */ | |
524 | rq : 1, /* Requester identifier | |
525 | * structure is valid | |
526 | */ | |
527 | rp : 1, /* Responder identifier | |
528 | * structure is valid | |
529 | */ | |
530 | pi : 1; /* Precise instruction pointer | |
531 | * structure is valid | |
532 | */ | |
533 | } pal_cache_check_info_t; | |
534 | ||
535 | typedef struct pal_tlb_check_info_s { | |
536 | ||
537 | u64 tr_slot : 8, /* Slot# of TR where | |
538 | * error occurred | |
539 | */ | |
540 | trv : 1, /* tr_slot field is valid */ | |
541 | reserved1 : 1, | |
542 | level : 2, /* TLB level where failure occurred */ | |
543 | reserved2 : 4, | |
544 | dtr : 1, /* Fail in data TR */ | |
545 | itr : 1, /* Fail in inst TR */ | |
546 | dtc : 1, /* Fail in data TC */ | |
547 | itc : 1, /* Fail in inst. TC */ | |
548 | op : 4, /* Cache operation */ | |
c19b2930 RA |
549 | reserved3 : 6, |
550 | hlth : 2, /* Health indicator */ | |
551 | reserved4 : 22, | |
1da177e4 LT |
552 | |
553 | is : 1, /* instruction set (1 == ia32) */ | |
554 | iv : 1, /* instruction set field valid */ | |
555 | pl : 2, /* privilege level */ | |
556 | pv : 1, /* privilege level field valid */ | |
557 | mcc : 1, /* Machine check corrected */ | |
558 | tv : 1, /* Target address | |
559 | * structure is valid | |
560 | */ | |
561 | rq : 1, /* Requester identifier | |
562 | * structure is valid | |
563 | */ | |
564 | rp : 1, /* Responder identifier | |
565 | * structure is valid | |
566 | */ | |
567 | pi : 1; /* Precise instruction pointer | |
568 | * structure is valid | |
569 | */ | |
570 | } pal_tlb_check_info_t; | |
571 | ||
572 | typedef struct pal_bus_check_info_s { | |
573 | u64 size : 5, /* Xaction size */ | |
574 | ib : 1, /* Internal bus error */ | |
575 | eb : 1, /* External bus error */ | |
576 | cc : 1, /* Error occurred | |
577 | * during cache-cache | |
578 | * transfer. | |
579 | */ | |
580 | type : 8, /* Bus xaction type*/ | |
581 | sev : 5, /* Bus error severity*/ | |
582 | hier : 2, /* Bus hierarchy level */ | |
323cbb09 | 583 | dp : 1, /* Data poisoned on MBE */ |
1da177e4 LT |
584 | bsi : 8, /* Bus error status |
585 | * info | |
586 | */ | |
587 | reserved2 : 22, | |
588 | ||
589 | is : 1, /* instruction set (1 == ia32) */ | |
590 | iv : 1, /* instruction set field valid */ | |
591 | pl : 2, /* privilege level */ | |
592 | pv : 1, /* privilege level field valid */ | |
593 | mcc : 1, /* Machine check corrected */ | |
594 | tv : 1, /* Target address | |
595 | * structure is valid | |
596 | */ | |
597 | rq : 1, /* Requester identifier | |
598 | * structure is valid | |
599 | */ | |
600 | rp : 1, /* Responder identifier | |
601 | * structure is valid | |
602 | */ | |
603 | pi : 1; /* Precise instruction pointer | |
604 | * structure is valid | |
605 | */ | |
606 | } pal_bus_check_info_t; | |
607 | ||
608 | typedef struct pal_reg_file_check_info_s { | |
609 | u64 id : 4, /* Register file identifier */ | |
610 | op : 4, /* Type of register | |
611 | * operation that | |
612 | * caused the machine | |
613 | * check. | |
614 | */ | |
615 | reg_num : 7, /* Register number */ | |
616 | rnv : 1, /* reg_num valid */ | |
617 | reserved2 : 38, | |
618 | ||
619 | is : 1, /* instruction set (1 == ia32) */ | |
620 | iv : 1, /* instruction set field valid */ | |
621 | pl : 2, /* privilege level */ | |
622 | pv : 1, /* privilege level field valid */ | |
623 | mcc : 1, /* Machine check corrected */ | |
624 | reserved3 : 3, | |
625 | pi : 1; /* Precise instruction pointer | |
626 | * structure is valid | |
627 | */ | |
628 | } pal_reg_file_check_info_t; | |
629 | ||
630 | typedef struct pal_uarch_check_info_s { | |
631 | u64 sid : 5, /* Structure identification */ | |
632 | level : 3, /* Level of failure */ | |
633 | array_id : 4, /* Array identification */ | |
634 | op : 4, /* Type of | |
635 | * operation that | |
636 | * caused the machine | |
637 | * check. | |
638 | */ | |
639 | way : 6, /* Way of structure */ | |
640 | wv : 1, /* way valid */ | |
641 | xv : 1, /* index valid */ | |
c19b2930 RA |
642 | reserved1 : 6, |
643 | hlth : 2, /* Health indicator */ | |
1da177e4 LT |
644 | index : 8, /* Index or set of the uarch |
645 | * structure that failed. | |
646 | */ | |
647 | reserved2 : 24, | |
648 | ||
649 | is : 1, /* instruction set (1 == ia32) */ | |
650 | iv : 1, /* instruction set field valid */ | |
651 | pl : 2, /* privilege level */ | |
652 | pv : 1, /* privilege level field valid */ | |
653 | mcc : 1, /* Machine check corrected */ | |
654 | tv : 1, /* Target address | |
655 | * structure is valid | |
656 | */ | |
657 | rq : 1, /* Requester identifier | |
658 | * structure is valid | |
659 | */ | |
660 | rp : 1, /* Responder identifier | |
661 | * structure is valid | |
662 | */ | |
663 | pi : 1; /* Precise instruction pointer | |
664 | * structure is valid | |
665 | */ | |
666 | } pal_uarch_check_info_t; | |
667 | ||
668 | typedef union pal_mc_error_info_u { | |
669 | u64 pmei_data; | |
670 | pal_processor_state_info_t pme_processor; | |
671 | pal_cache_check_info_t pme_cache; | |
672 | pal_tlb_check_info_t pme_tlb; | |
673 | pal_bus_check_info_t pme_bus; | |
674 | pal_reg_file_check_info_t pme_reg_file; | |
675 | pal_uarch_check_info_t pme_uarch; | |
676 | } pal_mc_error_info_t; | |
677 | ||
678 | #define pmci_proc_unknown_check pme_processor.uc | |
679 | #define pmci_proc_bus_check pme_processor.bc | |
680 | #define pmci_proc_tlb_check pme_processor.tc | |
681 | #define pmci_proc_cache_check pme_processor.cc | |
682 | #define pmci_proc_dynamic_state_size pme_processor.dsize | |
683 | #define pmci_proc_gpr_valid pme_processor.gr | |
684 | #define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0 | |
685 | #define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1 | |
686 | #define pmci_proc_fp_valid pme_processor.fp | |
687 | #define pmci_proc_predicate_regs_valid pme_processor.pr | |
688 | #define pmci_proc_branch_regs_valid pme_processor.br | |
689 | #define pmci_proc_app_regs_valid pme_processor.ar | |
690 | #define pmci_proc_region_regs_valid pme_processor.rr | |
691 | #define pmci_proc_translation_regs_valid pme_processor.tr | |
692 | #define pmci_proc_debug_regs_valid pme_processor.dr | |
693 | #define pmci_proc_perf_counters_valid pme_processor.pc | |
694 | #define pmci_proc_control_regs_valid pme_processor.cr | |
695 | #define pmci_proc_machine_check_expected pme_processor.ex | |
696 | #define pmci_proc_machine_check_corrected pme_processor.cm | |
697 | #define pmci_proc_rse_valid pme_processor.rs | |
698 | #define pmci_proc_machine_check_or_init pme_processor.in | |
699 | #define pmci_proc_dynamic_state_valid pme_processor.dy | |
700 | #define pmci_proc_operation pme_processor.op | |
701 | #define pmci_proc_trap_lost pme_processor.tl | |
702 | #define pmci_proc_hardware_damage pme_processor.hd | |
703 | #define pmci_proc_uncontained_storage_damage pme_processor.us | |
704 | #define pmci_proc_machine_check_isolated pme_processor.ci | |
705 | #define pmci_proc_continuable pme_processor.co | |
706 | #define pmci_proc_storage_intergrity_synced pme_processor.sy | |
707 | #define pmci_proc_min_state_save_area_regd pme_processor.mn | |
708 | #define pmci_proc_distinct_multiple_errors pme_processor.me | |
709 | #define pmci_proc_pal_attempted_rendezvous pme_processor.ra | |
710 | #define pmci_proc_pal_rendezvous_complete pme_processor.rz | |
711 | ||
712 | ||
713 | #define pmci_cache_level pme_cache.level | |
714 | #define pmci_cache_line_state pme_cache.mesi | |
715 | #define pmci_cache_line_state_valid pme_cache.mv | |
716 | #define pmci_cache_line_index pme_cache.index | |
717 | #define pmci_cache_instr_cache_fail pme_cache.ic | |
718 | #define pmci_cache_data_cache_fail pme_cache.dc | |
719 | #define pmci_cache_line_tag_fail pme_cache.tl | |
720 | #define pmci_cache_line_data_fail pme_cache.dl | |
721 | #define pmci_cache_operation pme_cache.op | |
722 | #define pmci_cache_way_valid pme_cache.wv | |
723 | #define pmci_cache_target_address_valid pme_cache.tv | |
724 | #define pmci_cache_way pme_cache.way | |
725 | #define pmci_cache_mc pme_cache.mc | |
726 | ||
727 | #define pmci_tlb_instr_translation_cache_fail pme_tlb.itc | |
728 | #define pmci_tlb_data_translation_cache_fail pme_tlb.dtc | |
729 | #define pmci_tlb_instr_translation_reg_fail pme_tlb.itr | |
730 | #define pmci_tlb_data_translation_reg_fail pme_tlb.dtr | |
731 | #define pmci_tlb_translation_reg_slot pme_tlb.tr_slot | |
732 | #define pmci_tlb_mc pme_tlb.mc | |
733 | ||
734 | #define pmci_bus_status_info pme_bus.bsi | |
735 | #define pmci_bus_req_address_valid pme_bus.rq | |
736 | #define pmci_bus_resp_address_valid pme_bus.rp | |
737 | #define pmci_bus_target_address_valid pme_bus.tv | |
738 | #define pmci_bus_error_severity pme_bus.sev | |
739 | #define pmci_bus_transaction_type pme_bus.type | |
740 | #define pmci_bus_cache_cache_transfer pme_bus.cc | |
741 | #define pmci_bus_transaction_size pme_bus.size | |
742 | #define pmci_bus_internal_error pme_bus.ib | |
743 | #define pmci_bus_external_error pme_bus.eb | |
744 | #define pmci_bus_mc pme_bus.mc | |
745 | ||
746 | /* | |
747 | * NOTE: this min_state_save area struct only includes the 1KB | |
748 | * architectural state save area. The other 3 KB is scratch space | |
749 | * for PAL. | |
750 | */ | |
751 | ||
752 | typedef struct pal_min_state_area_s { | |
753 | u64 pmsa_nat_bits; /* nat bits for saved GRs */ | |
754 | u64 pmsa_gr[15]; /* GR1 - GR15 */ | |
755 | u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */ | |
756 | u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */ | |
757 | u64 pmsa_pr; /* predicate registers */ | |
758 | u64 pmsa_br0; /* branch register 0 */ | |
759 | u64 pmsa_rsc; /* ar.rsc */ | |
760 | u64 pmsa_iip; /* cr.iip */ | |
761 | u64 pmsa_ipsr; /* cr.ipsr */ | |
762 | u64 pmsa_ifs; /* cr.ifs */ | |
763 | u64 pmsa_xip; /* previous iip */ | |
764 | u64 pmsa_xpsr; /* previous psr */ | |
765 | u64 pmsa_xfs; /* previous ifs */ | |
766 | u64 pmsa_br1; /* branch register 1 */ | |
767 | u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */ | |
768 | } pal_min_state_area_t; | |
769 | ||
770 | ||
771 | struct ia64_pal_retval { | |
772 | /* | |
773 | * A zero status value indicates call completed without error. | |
774 | * A negative status value indicates reason of call failure. | |
775 | * A positive status value indicates success but an | |
776 | * informational value should be printed (e.g., "reboot for | |
777 | * change to take effect"). | |
778 | */ | |
779 | s64 status; | |
780 | u64 v0; | |
781 | u64 v1; | |
782 | u64 v2; | |
783 | }; | |
784 | ||
785 | /* | |
786 | * Note: Currently unused PAL arguments are generally labeled | |
787 | * "reserved" so the value specified in the PAL documentation | |
788 | * (generally 0) MUST be passed. Reserved parameters are not optional | |
789 | * parameters. | |
790 | */ | |
c12fb188 | 791 | extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64); |
1da177e4 LT |
792 | extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64); |
793 | extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64); | |
794 | extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64); | |
795 | extern void ia64_save_scratch_fpregs (struct ia64_fpreg *); | |
796 | extern void ia64_load_scratch_fpregs (struct ia64_fpreg *); | |
797 | ||
798 | #define PAL_CALL(iprv,a0,a1,a2,a3) do { \ | |
799 | struct ia64_fpreg fr[6]; \ | |
800 | ia64_save_scratch_fpregs(fr); \ | |
c12fb188 | 801 | iprv = ia64_pal_call_static(a0, a1, a2, a3); \ |
1da177e4 LT |
802 | ia64_load_scratch_fpregs(fr); \ |
803 | } while (0) | |
804 | ||
805 | #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \ | |
806 | struct ia64_fpreg fr[6]; \ | |
807 | ia64_save_scratch_fpregs(fr); \ | |
808 | iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \ | |
809 | ia64_load_scratch_fpregs(fr); \ | |
810 | } while (0) | |
811 | ||
812 | #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \ | |
813 | struct ia64_fpreg fr[6]; \ | |
814 | ia64_save_scratch_fpregs(fr); \ | |
815 | iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \ | |
816 | ia64_load_scratch_fpregs(fr); \ | |
817 | } while (0) | |
818 | ||
819 | #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \ | |
820 | struct ia64_fpreg fr[6]; \ | |
821 | ia64_save_scratch_fpregs(fr); \ | |
822 | iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \ | |
823 | ia64_load_scratch_fpregs(fr); \ | |
824 | } while (0) | |
825 | ||
826 | typedef int (*ia64_pal_handler) (u64, ...); | |
827 | extern ia64_pal_handler ia64_pal; | |
828 | extern void ia64_pal_handler_init (void *); | |
829 | ||
830 | extern ia64_pal_handler ia64_pal; | |
831 | ||
832 | extern pal_cache_config_info_t l0d_cache_config_info; | |
833 | extern pal_cache_config_info_t l0i_cache_config_info; | |
834 | extern pal_cache_config_info_t l1_cache_config_info; | |
835 | extern pal_cache_config_info_t l2_cache_config_info; | |
836 | ||
837 | extern pal_cache_protection_info_t l0d_cache_protection_info; | |
838 | extern pal_cache_protection_info_t l0i_cache_protection_info; | |
839 | extern pal_cache_protection_info_t l1_cache_protection_info; | |
840 | extern pal_cache_protection_info_t l2_cache_protection_info; | |
841 | ||
842 | extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t, | |
843 | pal_cache_type_t); | |
844 | ||
845 | extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t, | |
846 | pal_cache_type_t); | |
847 | ||
848 | ||
849 | extern void pal_error(int); | |
850 | ||
851 | ||
852 | /* Useful wrappers for the current list of pal procedures */ | |
853 | ||
854 | typedef union pal_bus_features_u { | |
855 | u64 pal_bus_features_val; | |
856 | struct { | |
857 | u64 pbf_reserved1 : 29; | |
858 | u64 pbf_req_bus_parking : 1; | |
859 | u64 pbf_bus_lock_mask : 1; | |
860 | u64 pbf_enable_half_xfer_rate : 1; | |
5b4d5681 RA |
861 | u64 pbf_reserved2 : 20; |
862 | u64 pbf_enable_shared_line_replace : 1; | |
863 | u64 pbf_enable_exclusive_line_replace : 1; | |
1da177e4 LT |
864 | u64 pbf_disable_xaction_queueing : 1; |
865 | u64 pbf_disable_resp_err_check : 1; | |
866 | u64 pbf_disable_berr_check : 1; | |
867 | u64 pbf_disable_bus_req_internal_err_signal : 1; | |
868 | u64 pbf_disable_bus_req_berr_signal : 1; | |
869 | u64 pbf_disable_bus_init_event_check : 1; | |
870 | u64 pbf_disable_bus_init_event_signal : 1; | |
871 | u64 pbf_disable_bus_addr_err_check : 1; | |
872 | u64 pbf_disable_bus_addr_err_signal : 1; | |
873 | u64 pbf_disable_bus_data_err_check : 1; | |
874 | } pal_bus_features_s; | |
875 | } pal_bus_features_u_t; | |
876 | ||
877 | extern void pal_bus_features_print (u64); | |
878 | ||
879 | /* Provide information about configurable processor bus features */ | |
880 | static inline s64 | |
881 | ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail, | |
882 | pal_bus_features_u_t *features_status, | |
883 | pal_bus_features_u_t *features_control) | |
884 | { | |
885 | struct ia64_pal_retval iprv; | |
886 | PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0); | |
887 | if (features_avail) | |
888 | features_avail->pal_bus_features_val = iprv.v0; | |
889 | if (features_status) | |
890 | features_status->pal_bus_features_val = iprv.v1; | |
891 | if (features_control) | |
892 | features_control->pal_bus_features_val = iprv.v2; | |
893 | return iprv.status; | |
894 | } | |
895 | ||
896 | /* Enables/disables specific processor bus features */ | |
897 | static inline s64 | |
898 | ia64_pal_bus_set_features (pal_bus_features_u_t feature_select) | |
899 | { | |
900 | struct ia64_pal_retval iprv; | |
901 | PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0); | |
902 | return iprv.status; | |
903 | } | |
904 | ||
905 | /* Get detailed cache information */ | |
906 | static inline s64 | |
907 | ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf) | |
908 | { | |
909 | struct ia64_pal_retval iprv; | |
910 | ||
911 | PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0); | |
912 | ||
913 | if (iprv.status == 0) { | |
914 | conf->pcci_status = iprv.status; | |
915 | conf->pcci_info_1.pcci1_data = iprv.v0; | |
916 | conf->pcci_info_2.pcci2_data = iprv.v1; | |
917 | conf->pcci_reserved = iprv.v2; | |
918 | } | |
919 | return iprv.status; | |
920 | ||
921 | } | |
922 | ||
923 | /* Get detailed cche protection information */ | |
924 | static inline s64 | |
925 | ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot) | |
926 | { | |
927 | struct ia64_pal_retval iprv; | |
928 | ||
929 | PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0); | |
930 | ||
931 | if (iprv.status == 0) { | |
932 | prot->pcpi_status = iprv.status; | |
933 | prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; | |
934 | prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; | |
935 | prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; | |
936 | prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; | |
937 | prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; | |
938 | prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; | |
939 | } | |
940 | return iprv.status; | |
941 | } | |
942 | ||
943 | /* | |
944 | * Flush the processor instruction or data caches. *PROGRESS must be | |
945 | * initialized to zero before calling this for the first time.. | |
946 | */ | |
947 | static inline s64 | |
948 | ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) | |
949 | { | |
950 | struct ia64_pal_retval iprv; | |
f15ac580 | 951 | PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); |
1da177e4 LT |
952 | if (vector) |
953 | *vector = iprv.v0; | |
954 | *progress = iprv.v1; | |
955 | return iprv.status; | |
956 | } | |
957 | ||
958 | ||
959 | /* Initialize the processor controlled caches */ | |
960 | static inline s64 | |
961 | ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest) | |
962 | { | |
963 | struct ia64_pal_retval iprv; | |
964 | PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest); | |
965 | return iprv.status; | |
966 | } | |
967 | ||
968 | /* Initialize the tags and data of a data or unified cache line of | |
969 | * processor controlled cache to known values without the availability | |
970 | * of backing memory. | |
971 | */ | |
972 | static inline s64 | |
973 | ia64_pal_cache_line_init (u64 physical_addr, u64 data_value) | |
974 | { | |
975 | struct ia64_pal_retval iprv; | |
976 | PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0); | |
977 | return iprv.status; | |
978 | } | |
979 | ||
980 | ||
981 | /* Read the data and tag of a processor controlled cache line for diags */ | |
982 | static inline s64 | |
983 | ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) | |
984 | { | |
985 | struct ia64_pal_retval iprv; | |
b29e7132 RA |
986 | PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data, |
987 | physical_addr, 0); | |
1da177e4 LT |
988 | return iprv.status; |
989 | } | |
990 | ||
1b3c3714 | 991 | /* Return summary information about the hierarchy of caches controlled by the processor */ |
1da177e4 LT |
992 | static inline s64 |
993 | ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches) | |
994 | { | |
995 | struct ia64_pal_retval iprv; | |
996 | PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0); | |
997 | if (cache_levels) | |
998 | *cache_levels = iprv.v0; | |
999 | if (unique_caches) | |
1000 | *unique_caches = iprv.v1; | |
1001 | return iprv.status; | |
1002 | } | |
1003 | ||
1004 | /* Write the data and tag of a processor-controlled cache line for diags */ | |
1005 | static inline s64 | |
1006 | ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) | |
1007 | { | |
1008 | struct ia64_pal_retval iprv; | |
b29e7132 RA |
1009 | PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data, |
1010 | physical_addr, data); | |
1da177e4 LT |
1011 | return iprv.status; |
1012 | } | |
1013 | ||
1014 | ||
1015 | /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */ | |
1016 | static inline s64 | |
1017 | ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics, | |
1018 | u64 *buffer_size, u64 *buffer_align) | |
1019 | { | |
1020 | struct ia64_pal_retval iprv; | |
1021 | PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics); | |
1022 | if (buffer_size) | |
1023 | *buffer_size = iprv.v0; | |
1024 | if (buffer_align) | |
1025 | *buffer_align = iprv.v1; | |
1026 | return iprv.status; | |
1027 | } | |
1028 | ||
1029 | /* Copy relocatable PAL procedures from ROM to memory */ | |
1030 | static inline s64 | |
1031 | ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) | |
1032 | { | |
1033 | struct ia64_pal_retval iprv; | |
1034 | PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor); | |
1035 | if (pal_proc_offset) | |
1036 | *pal_proc_offset = iprv.v0; | |
1037 | return iprv.status; | |
1038 | } | |
1039 | ||
1040 | /* Return the number of instruction and data debug register pairs */ | |
1041 | static inline s64 | |
1042 | ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs) | |
1043 | { | |
1044 | struct ia64_pal_retval iprv; | |
1045 | PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0); | |
1046 | if (inst_regs) | |
1047 | *inst_regs = iprv.v0; | |
1048 | if (data_regs) | |
1049 | *data_regs = iprv.v1; | |
1050 | ||
1051 | return iprv.status; | |
1052 | } | |
1053 | ||
1054 | #ifdef TBD | |
1055 | /* Switch from IA64-system environment to IA-32 system environment */ | |
1056 | static inline s64 | |
1057 | ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3) | |
1058 | { | |
1059 | struct ia64_pal_retval iprv; | |
1060 | PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3); | |
1061 | return iprv.status; | |
1062 | } | |
1063 | #endif | |
1064 | ||
1065 | /* Get unique geographical address of this processor on its bus */ | |
1066 | static inline s64 | |
1067 | ia64_pal_fixed_addr (u64 *global_unique_addr) | |
1068 | { | |
1069 | struct ia64_pal_retval iprv; | |
1070 | PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0); | |
1071 | if (global_unique_addr) | |
1072 | *global_unique_addr = iprv.v0; | |
1073 | return iprv.status; | |
1074 | } | |
1075 | ||
1076 | /* Get base frequency of the platform if generated by the processor */ | |
1077 | static inline s64 | |
1078 | ia64_pal_freq_base (u64 *platform_base_freq) | |
1079 | { | |
1080 | struct ia64_pal_retval iprv; | |
1081 | PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0); | |
1082 | if (platform_base_freq) | |
1083 | *platform_base_freq = iprv.v0; | |
1084 | return iprv.status; | |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * Get the ratios for processor frequency, bus frequency and interval timer to | |
1089 | * to base frequency of the platform | |
1090 | */ | |
1091 | static inline s64 | |
1092 | ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio, | |
1093 | struct pal_freq_ratio *itc_ratio) | |
1094 | { | |
1095 | struct ia64_pal_retval iprv; | |
1096 | PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0); | |
1097 | if (proc_ratio) | |
1098 | *(u64 *)proc_ratio = iprv.v0; | |
1099 | if (bus_ratio) | |
1100 | *(u64 *)bus_ratio = iprv.v1; | |
1101 | if (itc_ratio) | |
1102 | *(u64 *)itc_ratio = iprv.v2; | |
1103 | return iprv.status; | |
1104 | } | |
1105 | ||
5b4d5681 RA |
1106 | /* |
1107 | * Get the current hardware resource sharing policy of the processor | |
1108 | */ | |
1109 | static inline s64 | |
1110 | ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted, | |
1111 | u64 *la) | |
1112 | { | |
1113 | struct ia64_pal_retval iprv; | |
1114 | PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0); | |
1115 | if (cur_policy) | |
1116 | *cur_policy = iprv.v0; | |
1117 | if (num_impacted) | |
1118 | *num_impacted = iprv.v1; | |
1119 | if (la) | |
1120 | *la = iprv.v2; | |
1121 | return iprv.status; | |
1122 | } | |
1123 | ||
1da177e4 LT |
1124 | /* Make the processor enter HALT or one of the implementation dependent low |
1125 | * power states where prefetching and execution are suspended and cache and | |
1126 | * TLB coherency is not maintained. | |
1127 | */ | |
1128 | static inline s64 | |
1129 | ia64_pal_halt (u64 halt_state) | |
1130 | { | |
1131 | struct ia64_pal_retval iprv; | |
1132 | PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0); | |
1133 | return iprv.status; | |
1134 | } | |
1135 | ||
1136 | typedef union pal_power_mgmt_info_u { | |
1137 | u64 ppmi_data; | |
1138 | struct { | |
1139 | u64 exit_latency : 16, | |
1140 | entry_latency : 16, | |
1141 | power_consumption : 28, | |
1142 | im : 1, | |
1143 | co : 1, | |
1144 | reserved : 2; | |
1145 | } pal_power_mgmt_info_s; | |
1146 | } pal_power_mgmt_info_u_t; | |
1147 | ||
1148 | /* Return information about processor's optional power management capabilities. */ | |
1149 | static inline s64 | |
1150 | ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) | |
1151 | { | |
1152 | struct ia64_pal_retval iprv; | |
1153 | PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0); | |
1154 | return iprv.status; | |
1155 | } | |
1156 | ||
4db8699b VP |
1157 | /* Get the current P-state information */ |
1158 | static inline s64 | |
17e77b1c | 1159 | ia64_pal_get_pstate (u64 *pstate_index, unsigned long type) |
4db8699b VP |
1160 | { |
1161 | struct ia64_pal_retval iprv; | |
17e77b1c | 1162 | PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0); |
4db8699b VP |
1163 | *pstate_index = iprv.v0; |
1164 | return iprv.status; | |
1165 | } | |
1166 | ||
1167 | /* Set the P-state */ | |
1168 | static inline s64 | |
1169 | ia64_pal_set_pstate (u64 pstate_index) | |
1170 | { | |
1171 | struct ia64_pal_retval iprv; | |
1172 | PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0); | |
1173 | return iprv.status; | |
1174 | } | |
1175 | ||
76d08bb3 TL |
1176 | /* Processor branding information*/ |
1177 | static inline s64 | |
1178 | ia64_pal_get_brand_info (char *brand_info) | |
1179 | { | |
1180 | struct ia64_pal_retval iprv; | |
1181 | PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0); | |
1182 | return iprv.status; | |
1183 | } | |
1184 | ||
1da177e4 LT |
1185 | /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are |
1186 | * suspended, but cache and TLB coherency is maintained. | |
1187 | */ | |
1188 | static inline s64 | |
1189 | ia64_pal_halt_light (void) | |
1190 | { | |
1191 | struct ia64_pal_retval iprv; | |
1192 | PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0); | |
1193 | return iprv.status; | |
1194 | } | |
1195 | ||
1196 | /* Clear all the processor error logging registers and reset the indicator that allows | |
1197 | * the error logging registers to be written. This procedure also checks the pending | |
1198 | * machine check bit and pending INIT bit and reports their states. | |
1199 | */ | |
1200 | static inline s64 | |
1201 | ia64_pal_mc_clear_log (u64 *pending_vector) | |
1202 | { | |
1203 | struct ia64_pal_retval iprv; | |
1204 | PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0); | |
1205 | if (pending_vector) | |
1206 | *pending_vector = iprv.v0; | |
1207 | return iprv.status; | |
1208 | } | |
1209 | ||
1210 | /* Ensure that all outstanding transactions in a processor are completed or that any | |
1211 | * MCA due to thes outstanding transaction is taken. | |
1212 | */ | |
1213 | static inline s64 | |
1214 | ia64_pal_mc_drain (void) | |
1215 | { | |
1216 | struct ia64_pal_retval iprv; | |
1217 | PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0); | |
1218 | return iprv.status; | |
1219 | } | |
1220 | ||
1221 | /* Return the machine check dynamic processor state */ | |
1222 | static inline s64 | |
c19b2930 | 1223 | ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size) |
1da177e4 LT |
1224 | { |
1225 | struct ia64_pal_retval iprv; | |
c19b2930 | 1226 | PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0); |
1da177e4 LT |
1227 | if (size) |
1228 | *size = iprv.v0; | |
1da177e4 LT |
1229 | return iprv.status; |
1230 | } | |
1231 | ||
1232 | /* Return processor machine check information */ | |
1233 | static inline s64 | |
1234 | ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info) | |
1235 | { | |
1236 | struct ia64_pal_retval iprv; | |
1237 | PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0); | |
1238 | if (size) | |
1239 | *size = iprv.v0; | |
1240 | if (error_info) | |
1241 | *error_info = iprv.v1; | |
1242 | return iprv.status; | |
1243 | } | |
1244 | ||
1138b7e2 FY |
1245 | /* Injects the requested processor error or returns info on |
1246 | * supported injection capabilities for current processor implementation | |
1247 | */ | |
1248 | static inline s64 | |
1249 | ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info, | |
1250 | u64 err_data_buffer, u64 *capabilities, u64 *resources) | |
1251 | { | |
1252 | struct ia64_pal_retval iprv; | |
1253 | PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info, | |
1254 | err_struct_info, err_data_buffer); | |
1255 | if (capabilities) | |
1256 | *capabilities= iprv.v0; | |
1257 | if (resources) | |
1258 | *resources= iprv.v1; | |
1259 | return iprv.status; | |
1260 | } | |
1261 | ||
1262 | static inline s64 | |
1263 | ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info, | |
1264 | u64 err_data_buffer, u64 *capabilities, u64 *resources) | |
1265 | { | |
1266 | struct ia64_pal_retval iprv; | |
1267 | PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info, | |
1268 | err_struct_info, err_data_buffer); | |
1269 | if (capabilities) | |
1270 | *capabilities= iprv.v0; | |
1271 | if (resources) | |
1272 | *resources= iprv.v1; | |
1273 | return iprv.status; | |
1274 | } | |
1275 | ||
1da177e4 LT |
1276 | /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot |
1277 | * attempt to correct any expected machine checks. | |
1278 | */ | |
1279 | static inline s64 | |
1280 | ia64_pal_mc_expected (u64 expected, u64 *previous) | |
1281 | { | |
1282 | struct ia64_pal_retval iprv; | |
1283 | PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0); | |
1284 | if (previous) | |
1285 | *previous = iprv.v0; | |
1286 | return iprv.status; | |
1287 | } | |
1288 | ||
c19b2930 RA |
1289 | typedef union pal_hw_tracking_u { |
1290 | u64 pht_data; | |
1291 | struct { | |
1292 | u64 itc :4, /* Instruction cache tracking */ | |
1293 | dct :4, /* Date cache tracking */ | |
1294 | itt :4, /* Instruction TLB tracking */ | |
1295 | ddt :4, /* Data TLB tracking */ | |
1296 | reserved:48; | |
1297 | } pal_hw_tracking_s; | |
1298 | } pal_hw_tracking_u_t; | |
1299 | ||
1300 | /* | |
1301 | * Hardware tracking status. | |
1302 | */ | |
1303 | static inline s64 | |
1304 | ia64_pal_mc_hw_tracking (u64 *status) | |
1305 | { | |
1306 | struct ia64_pal_retval iprv; | |
1307 | PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0); | |
1308 | if (status) | |
1309 | *status = iprv.v0; | |
1310 | return iprv.status; | |
1311 | } | |
1312 | ||
1da177e4 LT |
1313 | /* Register a platform dependent location with PAL to which it can save |
1314 | * minimal processor state in the event of a machine check or initialization | |
1315 | * event. | |
1316 | */ | |
1317 | static inline s64 | |
c19b2930 | 1318 | ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size) |
1da177e4 LT |
1319 | { |
1320 | struct ia64_pal_retval iprv; | |
c19b2930 RA |
1321 | PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0); |
1322 | if (req_size) | |
1323 | *req_size = iprv.v0; | |
1da177e4 LT |
1324 | return iprv.status; |
1325 | } | |
1326 | ||
1327 | /* Restore minimal architectural processor state, set CMC interrupt if necessary | |
1328 | * and resume execution | |
1329 | */ | |
1330 | static inline s64 | |
1331 | ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr) | |
1332 | { | |
1333 | struct ia64_pal_retval iprv; | |
1334 | PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0); | |
1335 | return iprv.status; | |
1336 | } | |
1337 | ||
1338 | /* Return the memory attributes implemented by the processor */ | |
1339 | static inline s64 | |
1340 | ia64_pal_mem_attrib (u64 *mem_attrib) | |
1341 | { | |
1342 | struct ia64_pal_retval iprv; | |
1343 | PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0); | |
1344 | if (mem_attrib) | |
1345 | *mem_attrib = iprv.v0 & 0xff; | |
1346 | return iprv.status; | |
1347 | } | |
1348 | ||
1349 | /* Return the amount of memory needed for second phase of processor | |
1350 | * self-test and the required alignment of memory. | |
1351 | */ | |
1352 | static inline s64 | |
1353 | ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment) | |
1354 | { | |
1355 | struct ia64_pal_retval iprv; | |
1356 | PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0); | |
1357 | if (bytes_needed) | |
1358 | *bytes_needed = iprv.v0; | |
1359 | if (alignment) | |
1360 | *alignment = iprv.v1; | |
1361 | return iprv.status; | |
1362 | } | |
1363 | ||
1364 | typedef union pal_perf_mon_info_u { | |
1365 | u64 ppmi_data; | |
1366 | struct { | |
1367 | u64 generic : 8, | |
1368 | width : 8, | |
1369 | cycles : 8, | |
1370 | retired : 8, | |
1371 | reserved : 32; | |
1372 | } pal_perf_mon_info_s; | |
1373 | } pal_perf_mon_info_u_t; | |
1374 | ||
1375 | /* Return the performance monitor information about what can be counted | |
1376 | * and how to configure the monitors to count the desired events. | |
1377 | */ | |
1378 | static inline s64 | |
1379 | ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info) | |
1380 | { | |
1381 | struct ia64_pal_retval iprv; | |
1382 | PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0); | |
1383 | if (pm_info) | |
1384 | pm_info->ppmi_data = iprv.v0; | |
1385 | return iprv.status; | |
1386 | } | |
1387 | ||
1388 | /* Specifies the physical address of the processor interrupt block | |
1389 | * and I/O port space. | |
1390 | */ | |
1391 | static inline s64 | |
1392 | ia64_pal_platform_addr (u64 type, u64 physical_addr) | |
1393 | { | |
1394 | struct ia64_pal_retval iprv; | |
1395 | PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0); | |
1396 | return iprv.status; | |
1397 | } | |
1398 | ||
1399 | /* Set the SAL PMI entrypoint in memory */ | |
1400 | static inline s64 | |
1401 | ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr) | |
1402 | { | |
1403 | struct ia64_pal_retval iprv; | |
1404 | PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0); | |
1405 | return iprv.status; | |
1406 | } | |
1407 | ||
1408 | struct pal_features_s; | |
1409 | /* Provide information about configurable processor features */ | |
1410 | static inline s64 | |
1411 | ia64_pal_proc_get_features (u64 *features_avail, | |
1412 | u64 *features_status, | |
b8de471f RA |
1413 | u64 *features_control, |
1414 | u64 features_set) | |
1da177e4 LT |
1415 | { |
1416 | struct ia64_pal_retval iprv; | |
b8de471f | 1417 | PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0); |
1da177e4 LT |
1418 | if (iprv.status == 0) { |
1419 | *features_avail = iprv.v0; | |
1420 | *features_status = iprv.v1; | |
1421 | *features_control = iprv.v2; | |
1422 | } | |
1423 | return iprv.status; | |
1424 | } | |
1425 | ||
1426 | /* Enable/disable processor dependent features */ | |
1427 | static inline s64 | |
1428 | ia64_pal_proc_set_features (u64 feature_select) | |
1429 | { | |
1430 | struct ia64_pal_retval iprv; | |
1431 | PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0); | |
1432 | return iprv.status; | |
1433 | } | |
1434 | ||
1435 | /* | |
1436 | * Put everything in a struct so we avoid the global offset table whenever | |
1437 | * possible. | |
1438 | */ | |
1439 | typedef struct ia64_ptce_info_s { | |
1440 | u64 base; | |
1441 | u32 count[2]; | |
1442 | u32 stride[2]; | |
1443 | } ia64_ptce_info_t; | |
1444 | ||
1445 | /* Return the information required for the architected loop used to purge | |
1446 | * (initialize) the entire TC | |
1447 | */ | |
1448 | static inline s64 | |
1449 | ia64_get_ptce (ia64_ptce_info_t *ptce) | |
1450 | { | |
1451 | struct ia64_pal_retval iprv; | |
1452 | ||
1453 | if (!ptce) | |
1454 | return -1; | |
1455 | ||
1456 | PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0); | |
1457 | if (iprv.status == 0) { | |
1458 | ptce->base = iprv.v0; | |
1459 | ptce->count[0] = iprv.v1 >> 32; | |
1460 | ptce->count[1] = iprv.v1 & 0xffffffff; | |
1461 | ptce->stride[0] = iprv.v2 >> 32; | |
1462 | ptce->stride[1] = iprv.v2 & 0xffffffff; | |
1463 | } | |
1464 | return iprv.status; | |
1465 | } | |
1466 | ||
1467 | /* Return info about implemented application and control registers. */ | |
1468 | static inline s64 | |
1469 | ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2) | |
1470 | { | |
1471 | struct ia64_pal_retval iprv; | |
1472 | PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0); | |
1473 | if (reg_info_1) | |
1474 | *reg_info_1 = iprv.v0; | |
1475 | if (reg_info_2) | |
1476 | *reg_info_2 = iprv.v1; | |
1477 | return iprv.status; | |
1478 | } | |
1479 | ||
1480 | typedef union pal_hints_u { | |
1481 | u64 ph_data; | |
1482 | struct { | |
1483 | u64 si : 1, | |
1484 | li : 1, | |
1485 | reserved : 62; | |
1486 | } pal_hints_s; | |
1487 | } pal_hints_u_t; | |
1488 | ||
1489 | /* Return information about the register stack and RSE for this processor | |
1490 | * implementation. | |
1491 | */ | |
1492 | static inline s64 | |
1493 | ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints) | |
1494 | { | |
1495 | struct ia64_pal_retval iprv; | |
1496 | PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0); | |
1497 | if (num_phys_stacked) | |
1498 | *num_phys_stacked = iprv.v0; | |
1499 | if (hints) | |
1500 | hints->ph_data = iprv.v1; | |
1501 | return iprv.status; | |
1502 | } | |
1503 | ||
5b4d5681 RA |
1504 | /* |
1505 | * Set the current hardware resource sharing policy of the processor | |
1506 | */ | |
1507 | static inline s64 | |
1508 | ia64_pal_set_hw_policy (u64 policy) | |
1509 | { | |
1510 | struct ia64_pal_retval iprv; | |
1511 | PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0); | |
1512 | return iprv.status; | |
1513 | } | |
1514 | ||
1da177e4 LT |
1515 | /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are |
1516 | * suspended, but cause cache and TLB coherency to be maintained. | |
1517 | * This is usually called in IA-32 mode. | |
1518 | */ | |
1519 | static inline s64 | |
1520 | ia64_pal_shutdown (void) | |
1521 | { | |
1522 | struct ia64_pal_retval iprv; | |
1523 | PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0); | |
1524 | return iprv.status; | |
1525 | } | |
1526 | ||
1527 | /* Perform the second phase of processor self-test. */ | |
1528 | static inline s64 | |
1529 | ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state) | |
1530 | { | |
1531 | struct ia64_pal_retval iprv; | |
1532 | PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes); | |
1533 | if (self_test_state) | |
1534 | *self_test_state = iprv.v0; | |
1535 | return iprv.status; | |
1536 | } | |
1537 | ||
1538 | typedef union pal_version_u { | |
1539 | u64 pal_version_val; | |
1540 | struct { | |
1541 | u64 pv_pal_b_rev : 8; | |
1542 | u64 pv_pal_b_model : 8; | |
1543 | u64 pv_reserved1 : 8; | |
1544 | u64 pv_pal_vendor : 8; | |
1545 | u64 pv_pal_a_rev : 8; | |
1546 | u64 pv_pal_a_model : 8; | |
1547 | u64 pv_reserved2 : 16; | |
1548 | } pal_version_s; | |
1549 | } pal_version_u_t; | |
1550 | ||
1551 | ||
1bf1eba7 MW |
1552 | /* |
1553 | * Return PAL version information. While the documentation states that | |
1554 | * PAL_VERSION can be called in either physical or virtual mode, some | |
1555 | * implementations only allow physical calls. We don't call it very often, | |
1556 | * so the overhead isn't worth eliminating. | |
1557 | */ | |
1da177e4 LT |
1558 | static inline s64 |
1559 | ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version) | |
1560 | { | |
1561 | struct ia64_pal_retval iprv; | |
1562 | PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0); | |
1563 | if (pal_min_version) | |
1564 | pal_min_version->pal_version_val = iprv.v0; | |
1565 | ||
1566 | if (pal_cur_version) | |
1567 | pal_cur_version->pal_version_val = iprv.v1; | |
1568 | ||
1569 | return iprv.status; | |
1570 | } | |
1571 | ||
1572 | typedef union pal_tc_info_u { | |
1573 | u64 pti_val; | |
1574 | struct { | |
1575 | u64 num_sets : 8, | |
1576 | associativity : 8, | |
1577 | num_entries : 16, | |
1578 | pf : 1, | |
1579 | unified : 1, | |
1580 | reduce_tr : 1, | |
1581 | reserved : 29; | |
1582 | } pal_tc_info_s; | |
1583 | } pal_tc_info_u_t; | |
1584 | ||
1585 | #define tc_reduce_tr pal_tc_info_s.reduce_tr | |
1586 | #define tc_unified pal_tc_info_s.unified | |
1587 | #define tc_pf pal_tc_info_s.pf | |
1588 | #define tc_num_entries pal_tc_info_s.num_entries | |
1589 | #define tc_associativity pal_tc_info_s.associativity | |
1590 | #define tc_num_sets pal_tc_info_s.num_sets | |
1591 | ||
1592 | ||
1593 | /* Return information about the virtual memory characteristics of the processor | |
1594 | * implementation. | |
1595 | */ | |
1596 | static inline s64 | |
1597 | ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages) | |
1598 | { | |
1599 | struct ia64_pal_retval iprv; | |
1600 | PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0); | |
1601 | if (tc_info) | |
1602 | tc_info->pti_val = iprv.v0; | |
1603 | if (tc_pages) | |
1604 | *tc_pages = iprv.v1; | |
1605 | return iprv.status; | |
1606 | } | |
1607 | ||
1608 | /* Get page size information about the virtual memory characteristics of the processor | |
1609 | * implementation. | |
1610 | */ | |
1611 | static inline s64 | |
1612 | ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages) | |
1613 | { | |
1614 | struct ia64_pal_retval iprv; | |
1615 | PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0); | |
1616 | if (tr_pages) | |
1617 | *tr_pages = iprv.v0; | |
1618 | if (vw_pages) | |
1619 | *vw_pages = iprv.v1; | |
1620 | return iprv.status; | |
1621 | } | |
1622 | ||
1623 | typedef union pal_vm_info_1_u { | |
1624 | u64 pvi1_val; | |
1625 | struct { | |
1626 | u64 vw : 1, | |
1627 | phys_add_size : 7, | |
1628 | key_size : 8, | |
1629 | max_pkr : 8, | |
1630 | hash_tag_id : 8, | |
1631 | max_dtr_entry : 8, | |
1632 | max_itr_entry : 8, | |
1633 | max_unique_tcs : 8, | |
1634 | num_tc_levels : 8; | |
1635 | } pal_vm_info_1_s; | |
1636 | } pal_vm_info_1_u_t; | |
1637 | ||
5b4d5681 RA |
1638 | #define PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */ |
1639 | ||
1da177e4 LT |
1640 | typedef union pal_vm_info_2_u { |
1641 | u64 pvi2_val; | |
1642 | struct { | |
1643 | u64 impl_va_msb : 8, | |
1644 | rid_size : 8, | |
5b4d5681 RA |
1645 | max_purges : 16, |
1646 | reserved : 32; | |
1da177e4 LT |
1647 | } pal_vm_info_2_s; |
1648 | } pal_vm_info_2_u_t; | |
1649 | ||
1650 | /* Get summary information about the virtual memory characteristics of the processor | |
1651 | * implementation. | |
1652 | */ | |
1653 | static inline s64 | |
1654 | ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2) | |
1655 | { | |
1656 | struct ia64_pal_retval iprv; | |
1657 | PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0); | |
1658 | if (vm_info_1) | |
1659 | vm_info_1->pvi1_val = iprv.v0; | |
1660 | if (vm_info_2) | |
1661 | vm_info_2->pvi2_val = iprv.v1; | |
1662 | return iprv.status; | |
1663 | } | |
1664 | ||
c19b2930 RA |
1665 | typedef union pal_vp_info_u { |
1666 | u64 pvi_val; | |
1667 | struct { | |
1668 | u64 index: 48, /* virtual feature set info */ | |
1669 | vmm_id: 16; /* feature set id */ | |
1670 | } pal_vp_info_s; | |
1671 | } pal_vp_info_u_t; | |
1672 | ||
1673 | /* | |
1674 | * Returns infomation about virtual processor features | |
1675 | */ | |
1676 | static inline s64 | |
1677 | ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id) | |
1678 | { | |
1679 | struct ia64_pal_retval iprv; | |
1680 | PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0); | |
1681 | if (vp_info) | |
1682 | *vp_info = iprv.v0; | |
1683 | if (vmm_id) | |
1684 | *vmm_id = iprv.v1; | |
1685 | return iprv.status; | |
1686 | } | |
1687 | ||
1da177e4 LT |
1688 | typedef union pal_itr_valid_u { |
1689 | u64 piv_val; | |
1690 | struct { | |
1691 | u64 access_rights_valid : 1, | |
1692 | priv_level_valid : 1, | |
1693 | dirty_bit_valid : 1, | |
1694 | mem_attr_valid : 1, | |
1695 | reserved : 60; | |
1696 | } pal_tr_valid_s; | |
1697 | } pal_tr_valid_u_t; | |
1698 | ||
1699 | /* Read a translation register */ | |
1700 | static inline s64 | |
1701 | ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid) | |
1702 | { | |
1703 | struct ia64_pal_retval iprv; | |
1704 | PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer)); | |
1705 | if (tr_valid) | |
1706 | tr_valid->piv_val = iprv.v0; | |
1707 | return iprv.status; | |
1708 | } | |
1709 | ||
1710 | /* | |
1711 | * PAL_PREFETCH_VISIBILITY transaction types | |
1712 | */ | |
1713 | #define PAL_VISIBILITY_VIRTUAL 0 | |
1714 | #define PAL_VISIBILITY_PHYSICAL 1 | |
1715 | ||
1716 | /* | |
1717 | * PAL_PREFETCH_VISIBILITY return codes | |
1718 | */ | |
1719 | #define PAL_VISIBILITY_OK 1 | |
1720 | #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0 | |
1721 | #define PAL_VISIBILITY_INVAL_ARG -2 | |
1722 | #define PAL_VISIBILITY_ERROR -3 | |
1723 | ||
1724 | static inline s64 | |
1725 | ia64_pal_prefetch_visibility (s64 trans_type) | |
1726 | { | |
1727 | struct ia64_pal_retval iprv; | |
1728 | PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0); | |
1729 | return iprv.status; | |
1730 | } | |
1731 | ||
e927ecb0 SS |
1732 | /* data structure for getting information on logical to physical mappings */ |
1733 | typedef union pal_log_overview_u { | |
1734 | struct { | |
1735 | u64 num_log :16, /* Total number of logical | |
1736 | * processors on this die | |
1737 | */ | |
1738 | tpc :8, /* Threads per core */ | |
1739 | reserved3 :8, /* Reserved */ | |
1740 | cpp :8, /* Cores per processor */ | |
1741 | reserved2 :8, /* Reserved */ | |
1742 | ppid :8, /* Physical processor ID */ | |
1743 | reserved1 :8; /* Reserved */ | |
1744 | } overview_bits; | |
1745 | u64 overview_data; | |
1746 | } pal_log_overview_t; | |
1747 | ||
1748 | typedef union pal_proc_n_log_info1_u{ | |
1749 | struct { | |
1750 | u64 tid :16, /* Thread id */ | |
1751 | reserved2 :16, /* Reserved */ | |
1752 | cid :16, /* Core id */ | |
1753 | reserved1 :16; /* Reserved */ | |
1754 | } ppli1_bits; | |
1755 | u64 ppli1_data; | |
1756 | } pal_proc_n_log_info1_t; | |
1757 | ||
1758 | typedef union pal_proc_n_log_info2_u { | |
1759 | struct { | |
1760 | u64 la :16, /* Logical address */ | |
1761 | reserved :48; /* Reserved */ | |
1762 | } ppli2_bits; | |
1763 | u64 ppli2_data; | |
1764 | } pal_proc_n_log_info2_t; | |
1765 | ||
1766 | typedef struct pal_logical_to_physical_s | |
1767 | { | |
1768 | pal_log_overview_t overview; | |
1769 | pal_proc_n_log_info1_t ppli1; | |
1770 | pal_proc_n_log_info2_t ppli2; | |
1771 | } pal_logical_to_physical_t; | |
1772 | ||
1773 | #define overview_num_log overview.overview_bits.num_log | |
1774 | #define overview_tpc overview.overview_bits.tpc | |
1775 | #define overview_cpp overview.overview_bits.cpp | |
1776 | #define overview_ppid overview.overview_bits.ppid | |
1777 | #define log1_tid ppli1.ppli1_bits.tid | |
1778 | #define log1_cid ppli1.ppli1_bits.cid | |
1779 | #define log2_la ppli2.ppli2_bits.la | |
1780 | ||
1781 | /* Get information on logical to physical processor mappings. */ | |
1782 | static inline s64 | |
1783 | ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping) | |
1784 | { | |
1785 | struct ia64_pal_retval iprv; | |
1786 | ||
1787 | PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0); | |
1788 | ||
1789 | if (iprv.status == PAL_STATUS_SUCCESS) | |
1790 | { | |
4129a953 | 1791 | mapping->overview.overview_data = iprv.v0; |
e927ecb0 SS |
1792 | mapping->ppli1.ppli1_data = iprv.v1; |
1793 | mapping->ppli2.ppli2_data = iprv.v2; | |
1794 | } | |
1795 | ||
1796 | return iprv.status; | |
1797 | } | |
f1918005 ZY |
1798 | |
1799 | typedef struct pal_cache_shared_info_s | |
1800 | { | |
1801 | u64 num_shared; | |
1802 | pal_proc_n_log_info1_t ppli1; | |
1803 | pal_proc_n_log_info2_t ppli2; | |
1804 | } pal_cache_shared_info_t; | |
1805 | ||
1806 | /* Get information on logical to physical processor mappings. */ | |
1807 | static inline s64 | |
1808 | ia64_pal_cache_shared_info(u64 level, | |
1809 | u64 type, | |
1810 | u64 proc_number, | |
1811 | pal_cache_shared_info_t *info) | |
1812 | { | |
1813 | struct ia64_pal_retval iprv; | |
1814 | ||
1815 | PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number); | |
1816 | ||
1817 | if (iprv.status == PAL_STATUS_SUCCESS) { | |
1818 | info->num_shared = iprv.v0; | |
1819 | info->ppli1.ppli1_data = iprv.v1; | |
1820 | info->ppli2.ppli2_data = iprv.v2; | |
1821 | } | |
1822 | ||
1823 | return iprv.status; | |
1824 | } | |
1da177e4 LT |
1825 | #endif /* __ASSEMBLY__ */ |
1826 | ||
1827 | #endif /* _ASM_IA64_PAL_H */ |