[deliverable/linux.git] / include / asm-ia64 / sn / addrs.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef _ASM_IA64_SN_ADDRS_H
#define _ASM_IA64_SN_ADDRS_H

#include <asm/percpu.h>
#include <asm/sn/types.h>
#include <asm/sn/arch.h>
#include <asm/sn/pda.h>

/*
 *  Memory/SHUB Address Format:
 *  +-+---------+--+--------------+
 *  |0|  NASID  |AS| NodeOffset   |
 *  +-+---------+--+--------------+
 *
 *  NASID: (low NASID bit is 0) Memory and SHUB MMRs
 *   AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
 *     00: Local Resources and MMR space
 *           Top bit of NodeOffset
 *               0: Local resources space
 *                  node id:
 *                        0: IA64/NT compatibility space
 *                        2: Local MMR Space
 *                        4: Local memory, regardless of local node id
 *               1: Global MMR space
 *     01: GET space.
 *     10: AMO space.
 *     11: Cacheable memory space.
 *
 *   NodeOffset: byte offset
 *
 *
 *  TIO address format:
 *  +-+----------+--+--------------+
 *  |0|  NASID   |AS| Nodeoffset   |
 *  +-+----------+--+--------------+
 *
 *  NASID: (low NASID bit is 1) TIO
 *   AS: 2-bit Chiplet Identifier
 *     00: TIO LB (Indicates TIO MMR access.)
 *     01: TIO ICE (indicates coretalk space access.)
 * 
 *   NodeOffset: top bit must be set.
 *
 *
 * Note that in both of the above address formats, the low
 * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
 */


/*
 * Define basic shift & mask constants for manipulating NASIDs and AS values.
 */
#define NASID_BITMASK		(sn_hub_info->nasid_bitmask)
#define NASID_SHIFT		(sn_hub_info->nasid_shift)
#define AS_SHIFT		(sn_hub_info->as_shift)
#define AS_BITMASK		0x3UL

#define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
#define AS_MASK			((u64)AS_BITMASK << AS_SHIFT)


/*
 * AS values. These are the same on both SHUB1 & SHUB2.
 */
#define AS_GET_VAL		1UL
#define AS_AMO_VAL		2UL
#define AS_CAC_VAL		3UL
#define AS_GET_SPACE		(AS_GET_VAL << AS_SHIFT)
#define AS_AMO_SPACE		(AS_AMO_VAL << AS_SHIFT)
#define AS_CAC_SPACE		(AS_CAC_VAL << AS_SHIFT)


/* 
 * Virtual Mode Local & Global MMR space.  
 */
#define SH1_LOCAL_MMR_OFFSET	0x8000000000UL
#define SH2_LOCAL_MMR_OFFSET	0x0200000000UL
#define LOCAL_MMR_OFFSET	(is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
#define LOCAL_MMR_SPACE		(__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
#define LOCAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)

#define SH1_GLOBAL_MMR_OFFSET	0x0800000000UL
#define SH2_GLOBAL_MMR_OFFSET	0x0300000000UL
#define GLOBAL_MMR_OFFSET	(is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
#define GLOBAL_MMR_SPACE	(__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)

/*
 * Physical mode addresses
 */
#define GLOBAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)


/*
 * Clear region & AS bits.
 */
#define TO_PHYS_MASK		(~(RGN_BITS | AS_MASK))


/*
 * Misc NASID manipulation.
 */
#define NASID_SPACE(n)		((u64)(n) << NASID_SHIFT)
#define REMOTE_ADDR(n,a)	(NASID_SPACE(n) | (a))
#define NODE_OFFSET(x)		((x) & (NODE_ADDRSPACE_SIZE - 1))
#define NODE_ADDRSPACE_SIZE     (1UL << AS_SHIFT)
#define NASID_GET(x)		(int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
#define LOCAL_MMR_ADDR(a)	(LOCAL_MMR_SPACE | (a))
#define GLOBAL_MMR_ADDR(n,a)	(GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
#define GLOBAL_CAC_ADDR(n,a)	(CAC_BASE | REMOTE_ADDR(n,a))
#define CHANGE_NASID(n,x)	((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
#define IS_TIO_NASID(n)		((n) & 1)


/* non-II mmr's start at top of big window space (4G) */
#define BWIN_TOP		0x0000000100000000UL

/*
 * general address defines
 */
#define CAC_BASE		(PAGE_OFFSET | AS_CAC_SPACE)
#define AMO_BASE		(__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
#define AMO_PHYS_BASE		(RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
#define GET_BASE		(PAGE_OFFSET | AS_GET_SPACE)

/*
 * Convert Memory addresses between various addressing modes.
 */
#define TO_PHYS(x)		(TO_PHYS_MASK & (x))
#define TO_CAC(x)		(CAC_BASE     | TO_PHYS(x))
#ifdef CONFIG_SGI_SN
#define TO_AMO(x)		(AMO_BASE     | TO_PHYS(x))
#define TO_GET(x)		(GET_BASE     | TO_PHYS(x))
#else
#define TO_AMO(x)		({ BUG(); x; })
#define TO_GET(x)		({ BUG(); x; })
#endif

/*
 * Covert from processor physical address to II/TIO physical address:
 *	II - squeeze out the AS bits
 *	TIO- requires a chiplet id in bits 38-39.  For DMA to memory,
 *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
 *           to insert a chiplet id into this macro.  However, it is our belief
 *           right now that this chiplet id will be ICE, which is also zero.
 */
#define SH1_TIO_PHYS_TO_DMA(x) 						\
	((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))

#define SH2_NETWORK_BANK_OFFSET(x) 					\
        ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))

#define SH2_NETWORK_BANK_SELECT(x) 					\
        ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4)))	\
        	>> (sn_hub_info->nasid_shift - 4)) << 36)

#define SH2_NETWORK_ADDRESS(x) 						\
	(SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))

#define SH2_TIO_PHYS_TO_DMA(x) 						\
        (((u64)(NASID_GET(x)) << 40) | 	SH2_NETWORK_ADDRESS(x))

#define PHYS_TO_TIODMA(x)						\
	(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))

#define PHYS_TO_DMA(x)							\
	((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))


/*
 * Macros to test for address type.
 */
#define IS_AMO_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
#define IS_AMO_PHYS_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)


/*
 * The following definitions pertain to the IO special address
 * space.  They define the location of the big and little windows
 * of any given node.
 */
#define BWIN_SIZE_BITS			29	/* big window size: 512M */
#define TIO_BWIN_SIZE_BITS		30	/* big window size: 1G */
#define NODE_SWIN_BASE(n, w)		((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
		: RAW_NODE_SWIN_BASE(n, w))
#define TIO_SWIN_BASE(n, w) 		(TIO_IO_BASE(n) + \
					    ((u64) (w) << TIO_SWIN_SIZE_BITS))
#define NODE_IO_BASE(n)			(GLOBAL_MMR_SPACE | NASID_SPACE(n))
#define TIO_IO_BASE(n)                  (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
#define BWIN_SIZE			(1UL << BWIN_SIZE_BITS)
#define NODE_BWIN_BASE0(n)		(NODE_IO_BASE(n) + BWIN_SIZE)
#define NODE_BWIN_BASE(n, w)		(NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
#define RAW_NODE_SWIN_BASE(n, w)	(NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
#define BWIN_WIDGET_MASK		0x7
#define BWIN_WINDOWNUM(x)		(((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
#define SH1_IS_BIG_WINDOW_ADDR(x)	((x) & BWIN_TOP)

#define TIO_BWIN_WINDOW_SELECT_MASK	0x7
#define TIO_BWIN_WINDOWNUM(x)		(((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)

#define TIO_HWIN_SHIFT_BITS		33
#define TIO_HWIN(x)			(NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)

/*
 * The following definitions pertain to the IO special address
 * space.  They define the location of the big and little windows
 * of any given node.
 */

#define SWIN_SIZE_BITS			24
#define	SWIN_WIDGET_MASK		0xF

#define TIO_SWIN_SIZE_BITS		28
#define TIO_SWIN_SIZE			(1UL << TIO_SWIN_SIZE_BITS)
#define TIO_SWIN_WIDGET_MASK		0x3

/*
 * Convert smallwindow address to xtalk address.
 *
 * 'addr' can be physical or virtual address, but will be converted
 * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
 */
#define	SWIN_WIDGETNUM(x)		(((x)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
#define TIO_SWIN_WIDGETNUM(x)		(((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)


/*
 * The following macros produce the correct base virtual address for
 * the hub registers. The REMOTE_HUB_* macro produce
 * the address for the specified hub's registers.  The intent is
 * that the appropriate PI, MD, NI, or II register would be substituted
 * for x.
 *
 *   WARNING:
 *	When certain Hub chip workaround are defined, it's not sufficient
 *	to dereference the *_HUB_ADDR() macros.  You should instead use
 *	HUB_L() and HUB_S() if you must deal with pointers to hub registers.
 *	Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
 *	They're always safe.
 */
/* Shub1 TIO & MMR addressing macros */
#define SH1_TIO_IOSPACE_ADDR(n,x)					\
	GLOBAL_MMR_ADDR(n,x)

#define SH1_REMOTE_BWIN_MMR(n,x)					\
	GLOBAL_MMR_ADDR(n,x)

#define SH1_REMOTE_SWIN_MMR(n,x)					\
	(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))

#define SH1_REMOTE_MMR(n,x)						\
	(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) :		\
	 	SH1_REMOTE_SWIN_MMR(n,x))

/* Shub1 TIO & MMR addressing macros */
#define SH2_TIO_IOSPACE_ADDR(n,x)					\
	((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))

#define SH2_REMOTE_MMR(n,x)						\
	GLOBAL_MMR_ADDR(n,x)


/* TIO & MMR addressing macros that work on both shub1 & shub2 */
#define TIO_IOSPACE_ADDR(n,x)						\
	((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) :		\
		 SH2_TIO_IOSPACE_ADDR(n,x)))

#define SH_REMOTE_MMR(n,x)						\
	(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))

#define REMOTE_HUB_ADDR(n,x)						\
	(IS_TIO_NASID(n) ?  ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) :	\
	 ((volatile u64*)SH_REMOTE_MMR(n,x)))


#define HUB_L(x)			(*((volatile typeof(*x) *)x))
#define	HUB_S(x,d)			(*((volatile typeof(*x) *)x) = (d))

#define REMOTE_HUB_L(n, a)		HUB_L(REMOTE_HUB_ADDR((n), (a)))
#define REMOTE_HUB_S(n, a, d)		HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))

/*
 * Coretalk address breakdown
 */
#define CTALK_NASID_SHFT		40
#define CTALK_NASID_MASK		(0x3FFFULL << CTALK_NASID_SHFT)
#define CTALK_CID_SHFT			38
#define CTALK_CID_MASK			(0x3ULL << CTALK_CID_SHFT)
#define CTALK_NODE_OFFSET		0x3FFFFFFFFF

#endif /* _ASM_IA64_SN_ADDRS_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
5b53ed1f	6	* Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
1da177e4 LT	7	*/
	8
	9	#ifndef _ASM_IA64_SN_ADDRS_H
	10	#define _ASM_IA64_SN_ADDRS_H
	11
	12	#include <asm/percpu.h>
	13	#include <asm/sn/types.h>
	14	#include <asm/sn/arch.h>
	15	#include <asm/sn/pda.h>
	16
	17	/*
	18	* Memory/SHUB Address Format:
	19	* +-+---------+--+--------------+
	20	* \|0\| NASID \|AS\| NodeOffset \|
	21	* +-+---------+--+--------------+
	22	*
	23	* NASID: (low NASID bit is 0) Memory and SHUB MMRs
	24	* AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
	25	* 00: Local Resources and MMR space
	26	* Top bit of NodeOffset
	27	* 0: Local resources space
	28	* node id:
	29	* 0: IA64/NT compatibility space
	30	* 2: Local MMR Space
	31	* 4: Local memory, regardless of local node id
	32	* 1: Global MMR space
	33	* 01: GET space.
	34	* 10: AMO space.
	35	* 11: Cacheable memory space.
	36	*
	37	* NodeOffset: byte offset
	38	*
	39	*
	40	* TIO address format:
	41	* +-+----------+--+--------------+
	42	* \|0\| NASID \|AS\| Nodeoffset \|
	43	* +-+----------+--+--------------+
	44	*
	45	* NASID: (low NASID bit is 1) TIO
	46	* AS: 2-bit Chiplet Identifier
	47	* 00: TIO LB (Indicates TIO MMR access.)
	48	* 01: TIO ICE (indicates coretalk space access.)
	49	*
	50	* NodeOffset: top bit must be set.
	51	*
	52	*
	53	* Note that in both of the above address formats, the low
	54	* NASID bit indicates if the reference is to the SHUB or TIO MMRs.
	55	*/
	56
	57
	58	/*
	59	* Define basic shift & mask constants for manipulating NASIDs and AS values.
	60	*/
	61	#define NASID_BITMASK (sn_hub_info->nasid_bitmask)
	62	#define NASID_SHIFT (sn_hub_info->nasid_shift)
	63	#define AS_SHIFT (sn_hub_info->as_shift)
	64	#define AS_BITMASK 0x3UL
	65
	66	#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
	67	#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
1da177e4 LT	68
	69
	70	/*
	71	* AS values. These are the same on both SHUB1 & SHUB2.
	72	*/
	73	#define AS_GET_VAL 1UL
	74	#define AS_AMO_VAL 2UL
	75	#define AS_CAC_VAL 3UL
	76	#define AS_GET_SPACE (AS_GET_VAL << AS_SHIFT)
	77	#define AS_AMO_SPACE (AS_AMO_VAL << AS_SHIFT)
	78	#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
	79
	80
1da177e4 LT	81	/*
	82	* Virtual Mode Local & Global MMR space.
	83	*/
	84	#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
	85	#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
	86	#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
1b66776d GE	87	#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET \| LOCAL_MMR_OFFSET)
1b66776d GE	88	#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) \| LOCAL_MMR_OFFSET)
1da177e4 LT	89
	90	#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
	91	#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
	92	#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
1b66776d	93	#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET \| GLOBAL_MMR_OFFSET)
1da177e4 LT	94
	95	/*
	96	* Physical mode addresses
	97	*/
1b66776d	98	#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) \| GLOBAL_MMR_OFFSET)
1da177e4 LT	99
	100
	101	/*
	102	* Clear region & AS bits.
	103	*/
1b66776d	104	#define TO_PHYS_MASK (~(RGN_BITS \| AS_MASK))
1da177e4 LT	105
	106
	107	/*
	108	* Misc NASID manipulation.
	109	*/
	110	#define NASID_SPACE(n) ((u64)(n) << NASID_SHIFT)
	111	#define REMOTE_ADDR(n,a) (NASID_SPACE(n) \| (a))
	112	#define NODE_OFFSET(x) ((x) & (NODE_ADDRSPACE_SIZE - 1))
	113	#define NODE_ADDRSPACE_SIZE (1UL << AS_SHIFT)
	114	#define NASID_GET(x) (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
	115	#define LOCAL_MMR_ADDR(a) (LOCAL_MMR_SPACE \| (a))
	116	#define GLOBAL_MMR_ADDR(n,a) (GLOBAL_MMR_SPACE \| REMOTE_ADDR(n,a))
	117	#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE \| REMOTE_ADDR(n,a))
	118	#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE \| REMOTE_ADDR(n,a))
	119	#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) \| NASID_SPACE(n)))
3d14487b	120	#define IS_TIO_NASID(n) ((n) & 1)
1da177e4 LT	121
	122
	123	/* non-II mmr's start at top of big window space (4G) */
	124	#define BWIN_TOP 0x0000000100000000UL
	125
	126	/*
	127	* general address defines
	128	*/
1b66776d GE	129	#define CAC_BASE (PAGE_OFFSET \| AS_CAC_SPACE)
	130	#define AMO_BASE (__IA64_UNCACHED_OFFSET \| AS_AMO_SPACE)
	131	#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) \| AS_AMO_SPACE)
	132	#define GET_BASE (PAGE_OFFSET \| AS_GET_SPACE)
1da177e4 LT	133
	134	/*
	135	* Convert Memory addresses between various addressing modes.
	136	*/
	137	#define TO_PHYS(x) (TO_PHYS_MASK & (x))
	138	#define TO_CAC(x) (CAC_BASE \| TO_PHYS(x))
1a4b0fc5	139	#ifdef CONFIG_SGI_SN
1da177e4 LT	140	#define TO_AMO(x) (AMO_BASE \| TO_PHYS(x))
1da177e4 LT	141	#define TO_GET(x) (GET_BASE \| TO_PHYS(x))
1a4b0fc5 JS	142	#else
	143	#define TO_AMO(x) ({ BUG(); x; })
	144	#define TO_GET(x) ({ BUG(); x; })
	145	#endif
1da177e4 LT	146
	147	/*
	148	* Covert from processor physical address to II/TIO physical address:
	149	* II - squeeze out the AS bits
	150	* TIO- requires a chiplet id in bits 38-39. For DMA to memory,
	151	* the chiplet id is zero. If we implement TIO-TIO dma, we might need
	152	* to insert a chiplet id into this macro. However, it is our belief
	153	* right now that this chiplet id will be ICE, which is also zero.
	154	*/
3d14487b JS	155	#define SH1_TIO_PHYS_TO_DMA(x) \
	156	((((u64)(NASID_GET(x))) << 40) \| NODE_OFFSET(x))
	157
	158	#define SH2_NETWORK_BANK_OFFSET(x) \
	159	((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
	160
	161	#define SH2_NETWORK_BANK_SELECT(x) \
	162	((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
	163	>> (sn_hub_info->nasid_shift - 4)) << 36)
	164
	165	#define SH2_NETWORK_ADDRESS(x) \
	166	(SH2_NETWORK_BANK_OFFSET(x) \| SH2_NETWORK_BANK_SELECT(x))
	167
	168	#define SH2_TIO_PHYS_TO_DMA(x) \
	169	(((u64)(NASID_GET(x)) << 40) \| SH2_NETWORK_ADDRESS(x))
	170
	171	#define PHYS_TO_TIODMA(x) \
	172	(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
	173
	174	#define PHYS_TO_DMA(x) \
	175	((((u64)(x) & NASID_MASK) >> 2) \| NODE_OFFSET(x))
1da177e4 LT	176
1da177e4 LT	177
3a7d555b DN	178	/*
	179	* Macros to test for address type.
	180	*/
1b66776d GE	181	#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS \| AS_MASK)) == AMO_BASE)
1b66776d GE	182	#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS \| AS_MASK)) == AMO_PHYS_BASE)
3a7d555b DN	183
3a7d555b DN	184
1da177e4 LT	185	/*
	186	* The following definitions pertain to the IO special address
	187	* space. They define the location of the big and little windows
	188	* of any given node.
	189	*/
	190	#define BWIN_SIZE_BITS 29 /* big window size: 512M */
	191	#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
	192	#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
	193	: RAW_NODE_SWIN_BASE(n, w))
e1e19747 BL	194	#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
e1e19747 BL	195	((u64) (w) << TIO_SWIN_SIZE_BITS))
1da177e4	196	#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE \| NASID_SPACE(n))
1b66776d	197	#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET \| NASID_SPACE(n))
1da177e4 LT	198	#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
	199	#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
	200	#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
	201	#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
	202	#define BWIN_WIDGET_MASK 0x7
	203	#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
3d14487b	204	#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
1da177e4 LT	205
	206	#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
	207	#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
	208
5b53ed1f MM	209	#define TIO_HWIN_SHIFT_BITS 33
5b53ed1f MM	210	#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
1da177e4 LT	211
	212	/*
	213	* The following definitions pertain to the IO special address
	214	* space. They define the location of the big and little windows
	215	* of any given node.
	216	*/
	217
	218	#define SWIN_SIZE_BITS 24
	219	#define SWIN_WIDGET_MASK 0xF
	220
	221	#define TIO_SWIN_SIZE_BITS 28
	222	#define TIO_SWIN_SIZE (1UL << TIO_SWIN_SIZE_BITS)
	223	#define TIO_SWIN_WIDGET_MASK 0x3
	224
	225	/*
	226	* Convert smallwindow address to xtalk address.
	227	*
	228	* 'addr' can be physical or virtual address, but will be converted
	229	* to Xtalk address in the range 0 -> SWINZ_SIZEMASK
	230	*/
	231	#define SWIN_WIDGETNUM(x) (((x) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
	232	#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
	233
	234
	235	/*
	236	* The following macros produce the correct base virtual address for
	237	* the hub registers. The REMOTE_HUB_* macro produce
	238	* the address for the specified hub's registers. The intent is
	239	* that the appropriate PI, MD, NI, or II register would be substituted
	240	* for x.
	241	*
	242	* WARNING:
	243	* When certain Hub chip workaround are defined, it's not sufficient
	244	* to dereference the *_HUB_ADDR() macros. You should instead use
	245	* HUB_L() and HUB_S() if you must deal with pointers to hub registers.
	246	* Otherwise, the recommended approach is to use _HUB_L() and _HUB_S().
	247	* They're always safe.
	248	*/
3d14487b JS	249	/* Shub1 TIO & MMR addressing macros */
	250	#define SH1_TIO_IOSPACE_ADDR(n,x) \
	251	GLOBAL_MMR_ADDR(n,x)
	252
	253	#define SH1_REMOTE_BWIN_MMR(n,x) \
	254	GLOBAL_MMR_ADDR(n,x)
	255
	256	#define SH1_REMOTE_SWIN_MMR(n,x) \
	257	(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
	258
	259	#define SH1_REMOTE_MMR(n,x) \
	260	(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
	261	SH1_REMOTE_SWIN_MMR(n,x))
	262
	263	/* Shub1 TIO & MMR addressing macros */
	264	#define SH2_TIO_IOSPACE_ADDR(n,x) \
e438befd	265	((__IA64_UNCACHED_OFFSET \| REMOTE_ADDR(n,x) \| 1UL << (NASID_SHIFT - 2)))
3d14487b JS	266
	267	#define SH2_REMOTE_MMR(n,x) \
	268	GLOBAL_MMR_ADDR(n,x)
	269
	270
	271	/* TIO & MMR addressing macros that work on both shub1 & shub2 */
	272	#define TIO_IOSPACE_ADDR(n,x) \
	273	((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
	274	SH2_TIO_IOSPACE_ADDR(n,x)))
	275
	276	#define SH_REMOTE_MMR(n,x) \
	277	(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
	278
1da177e4	279	#define REMOTE_HUB_ADDR(n,x) \
3d14487b JS	280	(IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
	281	((volatile u64*)SH_REMOTE_MMR(n,x)))
	282
1da177e4	283
1da177e4 LT	284	#define HUB_L(x) (((volatile typeof(x) *)x))
	285	#define HUB_S(x,d) (((volatile typeof(x) *)x) = (d))
	286
	287	#define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
	288	#define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
	289
13938ca7 MM	290	/*
	291	* Coretalk address breakdown
	292	*/
	293	#define CTALK_NASID_SHFT 40
	294	#define CTALK_NASID_MASK (0x3FFFULL << CTALK_NASID_SHFT)
	295	#define CTALK_CID_SHFT 38
	296	#define CTALK_CID_MASK (0x3ULL << CTALK_CID_SHFT)
	297	#define CTALK_NODE_OFFSET 0x3FFFFFFFFF
1da177e4 LT	298
1da177e4 LT	299	#endif /* _ASM_IA64_SN_ADDRS_H */