[deliverable/linux.git] / include / asm-ia64 / topology.h

/*
 * linux/include/asm-ia64/topology.h
 *
 * Copyright (C) 2002, Erich Focht, NEC
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#ifndef _ASM_IA64_TOPOLOGY_H
#define _ASM_IA64_TOPOLOGY_H

#include <asm/acpi.h>
#include <asm/numa.h>
#include <asm/smp.h>

#ifdef CONFIG_NUMA

/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
#define PENALTY_FOR_NODE_WITH_CPUS 255

/*
 * Returns the number of the node containing CPU 'cpu'
 */
#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])

/*
 * Returns a bitmask of CPUs on Node 'node'.
 */
#define node_to_cpumask(node) (node_to_cpu_mask[node])

/*
 * Returns the number of the node containing Node 'nid'.
 * Not implemented here. Multi-level hierarchies detected with
 * the help of node_distance().
 */
#define parent_node(nid) (nid)

/*
 * Returns the number of the first CPU on Node 'node'.
 */
#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))

/*
 * Determines the node for a given pci bus
 */
#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node

void build_cpu_to_node_map(void);

#define SD_CPU_INIT (struct sched_domain) {		\
	.span			= CPU_MASK_NONE,	\
	.parent			= NULL,			\
	.groups			= NULL,			\
	.min_interval		= 1,			\
	.max_interval		= 4,			\
	.busy_factor		= 64,			\
	.imbalance_pct		= 125,			\
	.per_cpu_gain		= 100,			\
	.cache_nice_tries	= 2,			\
	.busy_idx		= 2,			\
	.idle_idx		= 1,			\
	.newidle_idx		= 2,			\
	.wake_idx		= 1,			\
	.forkexec_idx		= 1,			\
	.flags			= SD_LOAD_BALANCE	\
				| SD_BALANCE_NEWIDLE	\
				| SD_BALANCE_EXEC	\
				| SD_WAKE_AFFINE,	\
	.last_balance		= jiffies,		\
	.balance_interval	= 1,			\
	.nr_balance_failed	= 0,			\
}

/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
#define SD_NODE_INIT (struct sched_domain) {		\
	.span			= CPU_MASK_NONE,	\
	.parent			= NULL,			\
	.groups			= NULL,			\
	.min_interval		= 8,			\
	.max_interval		= 8*(min(num_online_cpus(), 32)), \
	.busy_factor		= 64,			\
	.imbalance_pct		= 125,			\
	.cache_nice_tries	= 2,			\
	.busy_idx		= 3,			\
	.idle_idx		= 2,			\
	.newidle_idx		= 0, /* unused */	\
	.wake_idx		= 1,			\
	.forkexec_idx		= 1,			\
	.per_cpu_gain		= 100,			\
	.flags			= SD_LOAD_BALANCE	\
				| SD_BALANCE_EXEC	\
				| SD_BALANCE_FORK	\
				| SD_WAKE_BALANCE,	\
	.last_balance		= jiffies,		\
	.balance_interval	= 64,			\
	.nr_balance_failed	= 0,			\
}

#endif /* CONFIG_NUMA */

#ifdef CONFIG_SMP
#define topology_physical_package_id(cpu)	(cpu_data(cpu)->socket_id)
#define topology_core_id(cpu)			(cpu_data(cpu)->core_id)
#define topology_core_siblings(cpu)		(cpu_core_map[cpu])
#define topology_thread_siblings(cpu)		(cpu_sibling_map[cpu])
#endif

#include <asm-generic/topology.h>

#endif /* _ASM_IA64_TOPOLOGY_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-ia64/topology.h
	3	*
	4	* Copyright (C) 2002, Erich Focht, NEC
	5	*
	6	* All rights reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13	#ifndef _ASM_IA64_TOPOLOGY_H
	14	#define _ASM_IA64_TOPOLOGY_H
	15
	16	#include <asm/acpi.h>
	17	#include <asm/numa.h>
	18	#include <asm/smp.h>
	19
	20	#ifdef CONFIG_NUMA
8d08aed8 JS	21
	22	/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
	23	#define PENALTY_FOR_NODE_WITH_CPUS 255
	24
1da177e4 LT	25	/*
	26	* Returns the number of the node containing CPU 'cpu'
	27	*/
	28	#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
	29
	30	/*
	31	* Returns a bitmask of CPUs on Node 'node'.
	32	*/
	33	#define node_to_cpumask(node) (node_to_cpu_mask[node])
	34
	35	/*
	36	* Returns the number of the node containing Node 'nid'.
	37	* Not implemented here. Multi-level hierarchies detected with
	38	* the help of node_distance().
	39	*/
	40	#define parent_node(nid) (nid)
	41
	42	/*
	43	* Returns the number of the first CPU on Node 'node'.
	44	*/
c660439b	45	#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
1da177e4	46
514604c6 CL	47	/*
	48	* Determines the node for a given pci bus
	49	*/
	50	#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
	51
1da177e4 LT	52	void build_cpu_to_node_map(void);
1da177e4 LT	53
687f1661 NP	54	#define SD_CPU_INIT (struct sched_domain) { \
	55	.span = CPU_MASK_NONE, \
	56	.parent = NULL, \
	57	.groups = NULL, \
	58	.min_interval = 1, \
	59	.max_interval = 4, \
	60	.busy_factor = 64, \
	61	.imbalance_pct = 125, \
687f1661 NP	62	.per_cpu_gain = 100, \
	63	.cache_nice_tries = 2, \
	64	.busy_idx = 2, \
	65	.idle_idx = 1, \
	66	.newidle_idx = 2, \
	67	.wake_idx = 1, \
	68	.forkexec_idx = 1, \
	69	.flags = SD_LOAD_BALANCE \
	70	\| SD_BALANCE_NEWIDLE \
	71	\| SD_BALANCE_EXEC \
	72	\| SD_WAKE_AFFINE, \
	73	.last_balance = jiffies, \
	74	.balance_interval = 1, \
	75	.nr_balance_failed = 0, \
	76	}
	77
1da177e4 LT	78	/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
	79	#define SD_NODE_INIT (struct sched_domain) { \
	80	.span = CPU_MASK_NONE, \
	81	.parent = NULL, \
	82	.groups = NULL, \
687f1661 NP	83	.min_interval = 8, \
	84	.max_interval = 8*(min(num_online_cpus(), 32)), \
	85	.busy_factor = 64, \
1da177e4	86	.imbalance_pct = 125, \
687f1661 NP	87	.cache_nice_tries = 2, \
	88	.busy_idx = 3, \
	89	.idle_idx = 2, \
	90	.newidle_idx = 0, /* unused */ \
	91	.wake_idx = 1, \
	92	.forkexec_idx = 1, \
1da177e4 LT	93	.per_cpu_gain = 100, \
	94	.flags = SD_LOAD_BALANCE \
	95	\| SD_BALANCE_EXEC \
687f1661	96	\| SD_BALANCE_FORK \
1da177e4 LT	97	\| SD_WAKE_BALANCE, \
1da177e4 LT	98	.last_balance = jiffies, \
687f1661	99	.balance_interval = 64, \
1da177e4 LT	100	.nr_balance_failed = 0, \
	101	}
	102
1da177e4 LT	103	#endif /* CONFIG_NUMA */
1da177e4 LT	104
69dcc991 ZY	105	#ifdef CONFIG_SMP
	106	#define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id)
	107	#define topology_core_id(cpu) (cpu_data(cpu)->core_id)
	108	#define topology_core_siblings(cpu) (cpu_core_map[cpu])
	109	#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu])
	110	#endif
	111
1da177e4 LT	112	#include <asm-generic/topology.h>
	113
	114	#endif /* _ASM_IA64_TOPOLOGY_H */