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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
102fa15c | 6 | * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org) |
1da177e4 LT |
7 | * Copyright (c) 1999, 2000 Silicon Graphics, Inc. |
8 | */ | |
9 | #ifndef _ASM_BITOPS_H | |
10 | #define _ASM_BITOPS_H | |
11 | ||
1da177e4 | 12 | #include <linux/compiler.h> |
4ffd8b38 | 13 | #include <linux/irqflags.h> |
1da177e4 | 14 | #include <linux/types.h> |
0004a9df | 15 | #include <asm/barrier.h> |
ec917c2c | 16 | #include <asm/bug.h> |
1da177e4 LT |
17 | #include <asm/byteorder.h> /* sigh ... */ |
18 | #include <asm/cpu-features.h> | |
4ffd8b38 RB |
19 | #include <asm/sgidefs.h> |
20 | #include <asm/war.h> | |
1da177e4 | 21 | |
49a89efb | 22 | #if _MIPS_SZLONG == 32 |
1da177e4 LT |
23 | #define SZLONG_LOG 5 |
24 | #define SZLONG_MASK 31UL | |
aac8aa77 MR |
25 | #define __LL "ll " |
26 | #define __SC "sc " | |
102fa15c RB |
27 | #define __INS "ins " |
28 | #define __EXT "ext " | |
49a89efb | 29 | #elif _MIPS_SZLONG == 64 |
1da177e4 LT |
30 | #define SZLONG_LOG 6 |
31 | #define SZLONG_MASK 63UL | |
aac8aa77 MR |
32 | #define __LL "lld " |
33 | #define __SC "scd " | |
102fa15c RB |
34 | #define __INS "dins " |
35 | #define __EXT "dext " | |
1da177e4 LT |
36 | #endif |
37 | ||
1da177e4 LT |
38 | /* |
39 | * clear_bit() doesn't provide any barrier for the compiler. | |
40 | */ | |
17099b11 RB |
41 | #define smp_mb__before_clear_bit() smp_llsc_mb() |
42 | #define smp_mb__after_clear_bit() smp_llsc_mb() | |
1da177e4 | 43 | |
1da177e4 LT |
44 | /* |
45 | * set_bit - Atomically set a bit in memory | |
46 | * @nr: the bit to set | |
47 | * @addr: the address to start counting from | |
48 | * | |
49 | * This function is atomic and may not be reordered. See __set_bit() | |
50 | * if you do not require the atomic guarantees. | |
51 | * Note that @nr may be almost arbitrarily large; this function is not | |
52 | * restricted to acting on a single-word quantity. | |
53 | */ | |
54 | static inline void set_bit(unsigned long nr, volatile unsigned long *addr) | |
55 | { | |
56 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
b961153b | 57 | unsigned short bit = nr & SZLONG_MASK; |
1da177e4 LT |
58 | unsigned long temp; |
59 | ||
60 | if (cpu_has_llsc && R10000_LLSC_WAR) { | |
61 | __asm__ __volatile__( | |
c4559f67 | 62 | " .set mips3 \n" |
1da177e4 LT |
63 | "1: " __LL "%0, %1 # set_bit \n" |
64 | " or %0, %2 \n" | |
aac8aa77 | 65 | " " __SC "%0, %1 \n" |
1da177e4 | 66 | " beqzl %0, 1b \n" |
aac8aa77 | 67 | " .set mips0 \n" |
1da177e4 | 68 | : "=&r" (temp), "=m" (*m) |
b961153b | 69 | : "ir" (1UL << bit), "m" (*m)); |
102fa15c | 70 | #ifdef CONFIG_CPU_MIPSR2 |
b961153b | 71 | } else if (__builtin_constant_p(bit)) { |
102fa15c RB |
72 | __asm__ __volatile__( |
73 | "1: " __LL "%0, %1 # set_bit \n" | |
74 | " " __INS "%0, %4, %2, 1 \n" | |
75 | " " __SC "%0, %1 \n" | |
76 | " beqz %0, 2f \n" | |
77 | " .subsection 2 \n" | |
78 | "2: b 1b \n" | |
79 | " .previous \n" | |
80 | : "=&r" (temp), "=m" (*m) | |
b961153b | 81 | : "ir" (bit), "m" (*m), "r" (~0)); |
102fa15c | 82 | #endif /* CONFIG_CPU_MIPSR2 */ |
1da177e4 LT |
83 | } else if (cpu_has_llsc) { |
84 | __asm__ __volatile__( | |
c4559f67 | 85 | " .set mips3 \n" |
1da177e4 LT |
86 | "1: " __LL "%0, %1 # set_bit \n" |
87 | " or %0, %2 \n" | |
aac8aa77 | 88 | " " __SC "%0, %1 \n" |
f65e4fa8 RB |
89 | " beqz %0, 2f \n" |
90 | " .subsection 2 \n" | |
91 | "2: b 1b \n" | |
92 | " .previous \n" | |
aac8aa77 | 93 | " .set mips0 \n" |
1da177e4 | 94 | : "=&r" (temp), "=m" (*m) |
b961153b | 95 | : "ir" (1UL << bit), "m" (*m)); |
1da177e4 LT |
96 | } else { |
97 | volatile unsigned long *a = addr; | |
98 | unsigned long mask; | |
4ffd8b38 | 99 | unsigned long flags; |
1da177e4 LT |
100 | |
101 | a += nr >> SZLONG_LOG; | |
b961153b | 102 | mask = 1UL << bit; |
49edd098 | 103 | raw_local_irq_save(flags); |
1da177e4 | 104 | *a |= mask; |
49edd098 | 105 | raw_local_irq_restore(flags); |
1da177e4 LT |
106 | } |
107 | } | |
108 | ||
1da177e4 LT |
109 | /* |
110 | * clear_bit - Clears a bit in memory | |
111 | * @nr: Bit to clear | |
112 | * @addr: Address to start counting from | |
113 | * | |
114 | * clear_bit() is atomic and may not be reordered. However, it does | |
115 | * not contain a memory barrier, so if it is used for locking purposes, | |
116 | * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() | |
117 | * in order to ensure changes are visible on other processors. | |
118 | */ | |
119 | static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) | |
120 | { | |
121 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
b961153b | 122 | unsigned short bit = nr & SZLONG_MASK; |
1da177e4 LT |
123 | unsigned long temp; |
124 | ||
125 | if (cpu_has_llsc && R10000_LLSC_WAR) { | |
126 | __asm__ __volatile__( | |
c4559f67 | 127 | " .set mips3 \n" |
1da177e4 LT |
128 | "1: " __LL "%0, %1 # clear_bit \n" |
129 | " and %0, %2 \n" | |
130 | " " __SC "%0, %1 \n" | |
131 | " beqzl %0, 1b \n" | |
aac8aa77 | 132 | " .set mips0 \n" |
1da177e4 | 133 | : "=&r" (temp), "=m" (*m) |
b961153b | 134 | : "ir" (~(1UL << bit)), "m" (*m)); |
102fa15c | 135 | #ifdef CONFIG_CPU_MIPSR2 |
b961153b | 136 | } else if (__builtin_constant_p(bit)) { |
102fa15c RB |
137 | __asm__ __volatile__( |
138 | "1: " __LL "%0, %1 # clear_bit \n" | |
139 | " " __INS "%0, $0, %2, 1 \n" | |
140 | " " __SC "%0, %1 \n" | |
141 | " beqz %0, 2f \n" | |
142 | " .subsection 2 \n" | |
143 | "2: b 1b \n" | |
144 | " .previous \n" | |
145 | : "=&r" (temp), "=m" (*m) | |
b961153b | 146 | : "ir" (bit), "m" (*m)); |
102fa15c | 147 | #endif /* CONFIG_CPU_MIPSR2 */ |
1da177e4 LT |
148 | } else if (cpu_has_llsc) { |
149 | __asm__ __volatile__( | |
c4559f67 | 150 | " .set mips3 \n" |
1da177e4 LT |
151 | "1: " __LL "%0, %1 # clear_bit \n" |
152 | " and %0, %2 \n" | |
153 | " " __SC "%0, %1 \n" | |
f65e4fa8 RB |
154 | " beqz %0, 2f \n" |
155 | " .subsection 2 \n" | |
156 | "2: b 1b \n" | |
157 | " .previous \n" | |
aac8aa77 | 158 | " .set mips0 \n" |
1da177e4 | 159 | : "=&r" (temp), "=m" (*m) |
b961153b | 160 | : "ir" (~(1UL << bit)), "m" (*m)); |
1da177e4 LT |
161 | } else { |
162 | volatile unsigned long *a = addr; | |
163 | unsigned long mask; | |
4ffd8b38 | 164 | unsigned long flags; |
1da177e4 LT |
165 | |
166 | a += nr >> SZLONG_LOG; | |
b961153b | 167 | mask = 1UL << bit; |
49edd098 | 168 | raw_local_irq_save(flags); |
1da177e4 | 169 | *a &= ~mask; |
49edd098 | 170 | raw_local_irq_restore(flags); |
1da177e4 LT |
171 | } |
172 | } | |
173 | ||
1da177e4 LT |
174 | /* |
175 | * change_bit - Toggle a bit in memory | |
176 | * @nr: Bit to change | |
177 | * @addr: Address to start counting from | |
178 | * | |
179 | * change_bit() is atomic and may not be reordered. | |
180 | * Note that @nr may be almost arbitrarily large; this function is not | |
181 | * restricted to acting on a single-word quantity. | |
182 | */ | |
183 | static inline void change_bit(unsigned long nr, volatile unsigned long *addr) | |
184 | { | |
b961153b RB |
185 | unsigned short bit = nr & SZLONG_MASK; |
186 | ||
1da177e4 LT |
187 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
188 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
189 | unsigned long temp; | |
190 | ||
191 | __asm__ __volatile__( | |
c4559f67 | 192 | " .set mips3 \n" |
1da177e4 LT |
193 | "1: " __LL "%0, %1 # change_bit \n" |
194 | " xor %0, %2 \n" | |
aac8aa77 | 195 | " " __SC "%0, %1 \n" |
1da177e4 | 196 | " beqzl %0, 1b \n" |
aac8aa77 | 197 | " .set mips0 \n" |
1da177e4 | 198 | : "=&r" (temp), "=m" (*m) |
b961153b | 199 | : "ir" (1UL << bit), "m" (*m)); |
1da177e4 LT |
200 | } else if (cpu_has_llsc) { |
201 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
202 | unsigned long temp; | |
203 | ||
204 | __asm__ __volatile__( | |
c4559f67 | 205 | " .set mips3 \n" |
1da177e4 LT |
206 | "1: " __LL "%0, %1 # change_bit \n" |
207 | " xor %0, %2 \n" | |
aac8aa77 | 208 | " " __SC "%0, %1 \n" |
f65e4fa8 RB |
209 | " beqz %0, 2f \n" |
210 | " .subsection 2 \n" | |
211 | "2: b 1b \n" | |
212 | " .previous \n" | |
aac8aa77 | 213 | " .set mips0 \n" |
1da177e4 | 214 | : "=&r" (temp), "=m" (*m) |
b961153b | 215 | : "ir" (1UL << bit), "m" (*m)); |
1da177e4 LT |
216 | } else { |
217 | volatile unsigned long *a = addr; | |
218 | unsigned long mask; | |
4ffd8b38 | 219 | unsigned long flags; |
1da177e4 LT |
220 | |
221 | a += nr >> SZLONG_LOG; | |
b961153b | 222 | mask = 1UL << bit; |
49edd098 | 223 | raw_local_irq_save(flags); |
1da177e4 | 224 | *a ^= mask; |
49edd098 | 225 | raw_local_irq_restore(flags); |
1da177e4 LT |
226 | } |
227 | } | |
228 | ||
1da177e4 LT |
229 | /* |
230 | * test_and_set_bit - Set a bit and return its old value | |
231 | * @nr: Bit to set | |
232 | * @addr: Address to count from | |
233 | * | |
234 | * This operation is atomic and cannot be reordered. | |
235 | * It also implies a memory barrier. | |
236 | */ | |
237 | static inline int test_and_set_bit(unsigned long nr, | |
238 | volatile unsigned long *addr) | |
239 | { | |
b961153b | 240 | unsigned short bit = nr & SZLONG_MASK; |
ff72b7a6 | 241 | unsigned long res; |
b961153b | 242 | |
c8f30ae5 NP |
243 | smp_llsc_mb(); |
244 | ||
1da177e4 LT |
245 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
246 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
ff72b7a6 | 247 | unsigned long temp; |
1da177e4 LT |
248 | |
249 | __asm__ __volatile__( | |
c4559f67 | 250 | " .set mips3 \n" |
1da177e4 LT |
251 | "1: " __LL "%0, %1 # test_and_set_bit \n" |
252 | " or %2, %0, %3 \n" | |
253 | " " __SC "%2, %1 \n" | |
254 | " beqzl %2, 1b \n" | |
255 | " and %2, %0, %3 \n" | |
aac8aa77 | 256 | " .set mips0 \n" |
1da177e4 | 257 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
b961153b | 258 | : "r" (1UL << bit), "m" (*m) |
1da177e4 | 259 | : "memory"); |
1da177e4 LT |
260 | } else if (cpu_has_llsc) { |
261 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
ff72b7a6 | 262 | unsigned long temp; |
1da177e4 LT |
263 | |
264 | __asm__ __volatile__( | |
aac8aa77 MR |
265 | " .set push \n" |
266 | " .set noreorder \n" | |
c4559f67 | 267 | " .set mips3 \n" |
aac8aa77 | 268 | "1: " __LL "%0, %1 # test_and_set_bit \n" |
1da177e4 LT |
269 | " or %2, %0, %3 \n" |
270 | " " __SC "%2, %1 \n" | |
f65e4fa8 | 271 | " beqz %2, 2f \n" |
1da177e4 | 272 | " and %2, %0, %3 \n" |
f65e4fa8 RB |
273 | " .subsection 2 \n" |
274 | "2: b 1b \n" | |
275 | " nop \n" | |
276 | " .previous \n" | |
aac8aa77 | 277 | " .set pop \n" |
1da177e4 | 278 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
b961153b | 279 | : "r" (1UL << bit), "m" (*m) |
1da177e4 | 280 | : "memory"); |
1da177e4 LT |
281 | } else { |
282 | volatile unsigned long *a = addr; | |
283 | unsigned long mask; | |
4ffd8b38 | 284 | unsigned long flags; |
1da177e4 LT |
285 | |
286 | a += nr >> SZLONG_LOG; | |
b961153b | 287 | mask = 1UL << bit; |
49edd098 | 288 | raw_local_irq_save(flags); |
ff72b7a6 | 289 | res = (mask & *a); |
1da177e4 | 290 | *a |= mask; |
49edd098 | 291 | raw_local_irq_restore(flags); |
1da177e4 | 292 | } |
0004a9df | 293 | |
17099b11 | 294 | smp_llsc_mb(); |
ff72b7a6 RB |
295 | |
296 | return res != 0; | |
1da177e4 LT |
297 | } |
298 | ||
1da177e4 LT |
299 | /* |
300 | * test_and_clear_bit - Clear a bit and return its old value | |
301 | * @nr: Bit to clear | |
302 | * @addr: Address to count from | |
303 | * | |
304 | * This operation is atomic and cannot be reordered. | |
305 | * It also implies a memory barrier. | |
306 | */ | |
307 | static inline int test_and_clear_bit(unsigned long nr, | |
308 | volatile unsigned long *addr) | |
309 | { | |
b961153b | 310 | unsigned short bit = nr & SZLONG_MASK; |
ff72b7a6 | 311 | unsigned long res; |
b961153b | 312 | |
c8f30ae5 NP |
313 | smp_llsc_mb(); |
314 | ||
1da177e4 LT |
315 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
316 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
8e09ffb6 | 317 | unsigned long temp; |
1da177e4 LT |
318 | |
319 | __asm__ __volatile__( | |
c4559f67 | 320 | " .set mips3 \n" |
1da177e4 LT |
321 | "1: " __LL "%0, %1 # test_and_clear_bit \n" |
322 | " or %2, %0, %3 \n" | |
323 | " xor %2, %3 \n" | |
aac8aa77 | 324 | " " __SC "%2, %1 \n" |
1da177e4 LT |
325 | " beqzl %2, 1b \n" |
326 | " and %2, %0, %3 \n" | |
aac8aa77 | 327 | " .set mips0 \n" |
1da177e4 | 328 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
b961153b | 329 | : "r" (1UL << bit), "m" (*m) |
1da177e4 | 330 | : "memory"); |
102fa15c RB |
331 | #ifdef CONFIG_CPU_MIPSR2 |
332 | } else if (__builtin_constant_p(nr)) { | |
333 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
ff72b7a6 | 334 | unsigned long temp; |
102fa15c RB |
335 | |
336 | __asm__ __volatile__( | |
337 | "1: " __LL "%0, %1 # test_and_clear_bit \n" | |
338 | " " __EXT "%2, %0, %3, 1 \n" | |
339 | " " __INS "%0, $0, %3, 1 \n" | |
340 | " " __SC "%0, %1 \n" | |
341 | " beqz %0, 2f \n" | |
342 | " .subsection 2 \n" | |
343 | "2: b 1b \n" | |
344 | " .previous \n" | |
345 | : "=&r" (temp), "=m" (*m), "=&r" (res) | |
b961153b | 346 | : "ri" (bit), "m" (*m) |
102fa15c | 347 | : "memory"); |
102fa15c | 348 | #endif |
1da177e4 LT |
349 | } else if (cpu_has_llsc) { |
350 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
ff72b7a6 | 351 | unsigned long temp; |
1da177e4 LT |
352 | |
353 | __asm__ __volatile__( | |
aac8aa77 MR |
354 | " .set push \n" |
355 | " .set noreorder \n" | |
c4559f67 | 356 | " .set mips3 \n" |
aac8aa77 | 357 | "1: " __LL "%0, %1 # test_and_clear_bit \n" |
1da177e4 LT |
358 | " or %2, %0, %3 \n" |
359 | " xor %2, %3 \n" | |
aac8aa77 | 360 | " " __SC "%2, %1 \n" |
f65e4fa8 | 361 | " beqz %2, 2f \n" |
1da177e4 | 362 | " and %2, %0, %3 \n" |
f65e4fa8 RB |
363 | " .subsection 2 \n" |
364 | "2: b 1b \n" | |
365 | " nop \n" | |
366 | " .previous \n" | |
aac8aa77 | 367 | " .set pop \n" |
1da177e4 | 368 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
b961153b | 369 | : "r" (1UL << bit), "m" (*m) |
1da177e4 | 370 | : "memory"); |
1da177e4 LT |
371 | } else { |
372 | volatile unsigned long *a = addr; | |
373 | unsigned long mask; | |
4ffd8b38 | 374 | unsigned long flags; |
1da177e4 LT |
375 | |
376 | a += nr >> SZLONG_LOG; | |
b961153b | 377 | mask = 1UL << bit; |
49edd098 | 378 | raw_local_irq_save(flags); |
ff72b7a6 | 379 | res = (mask & *a); |
1da177e4 | 380 | *a &= ~mask; |
49edd098 | 381 | raw_local_irq_restore(flags); |
1da177e4 | 382 | } |
0004a9df | 383 | |
17099b11 | 384 | smp_llsc_mb(); |
ff72b7a6 RB |
385 | |
386 | return res != 0; | |
1da177e4 LT |
387 | } |
388 | ||
1da177e4 LT |
389 | /* |
390 | * test_and_change_bit - Change a bit and return its old value | |
391 | * @nr: Bit to change | |
392 | * @addr: Address to count from | |
393 | * | |
394 | * This operation is atomic and cannot be reordered. | |
395 | * It also implies a memory barrier. | |
396 | */ | |
397 | static inline int test_and_change_bit(unsigned long nr, | |
398 | volatile unsigned long *addr) | |
399 | { | |
b961153b | 400 | unsigned short bit = nr & SZLONG_MASK; |
ff72b7a6 | 401 | unsigned long res; |
b961153b | 402 | |
c8f30ae5 NP |
403 | smp_llsc_mb(); |
404 | ||
1da177e4 LT |
405 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
406 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
ff72b7a6 | 407 | unsigned long temp; |
1da177e4 LT |
408 | |
409 | __asm__ __volatile__( | |
c4559f67 | 410 | " .set mips3 \n" |
aac8aa77 | 411 | "1: " __LL "%0, %1 # test_and_change_bit \n" |
1da177e4 | 412 | " xor %2, %0, %3 \n" |
aac8aa77 | 413 | " " __SC "%2, %1 \n" |
1da177e4 LT |
414 | " beqzl %2, 1b \n" |
415 | " and %2, %0, %3 \n" | |
aac8aa77 | 416 | " .set mips0 \n" |
1da177e4 | 417 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
b961153b | 418 | : "r" (1UL << bit), "m" (*m) |
1da177e4 | 419 | : "memory"); |
1da177e4 LT |
420 | } else if (cpu_has_llsc) { |
421 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | |
ff72b7a6 | 422 | unsigned long temp; |
1da177e4 LT |
423 | |
424 | __asm__ __volatile__( | |
aac8aa77 MR |
425 | " .set push \n" |
426 | " .set noreorder \n" | |
c4559f67 | 427 | " .set mips3 \n" |
aac8aa77 | 428 | "1: " __LL "%0, %1 # test_and_change_bit \n" |
1da177e4 | 429 | " xor %2, %0, %3 \n" |
aac8aa77 | 430 | " " __SC "\t%2, %1 \n" |
f65e4fa8 | 431 | " beqz %2, 2f \n" |
1da177e4 | 432 | " and %2, %0, %3 \n" |
f65e4fa8 RB |
433 | " .subsection 2 \n" |
434 | "2: b 1b \n" | |
435 | " nop \n" | |
436 | " .previous \n" | |
aac8aa77 | 437 | " .set pop \n" |
1da177e4 | 438 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
b961153b | 439 | : "r" (1UL << bit), "m" (*m) |
1da177e4 | 440 | : "memory"); |
1da177e4 LT |
441 | } else { |
442 | volatile unsigned long *a = addr; | |
ff72b7a6 | 443 | unsigned long mask; |
4ffd8b38 | 444 | unsigned long flags; |
1da177e4 LT |
445 | |
446 | a += nr >> SZLONG_LOG; | |
b961153b | 447 | mask = 1UL << bit; |
49edd098 | 448 | raw_local_irq_save(flags); |
ff72b7a6 | 449 | res = (mask & *a); |
1da177e4 | 450 | *a ^= mask; |
49edd098 | 451 | raw_local_irq_restore(flags); |
1da177e4 | 452 | } |
0004a9df | 453 | |
17099b11 | 454 | smp_llsc_mb(); |
ff72b7a6 RB |
455 | |
456 | return res != 0; | |
1da177e4 LT |
457 | } |
458 | ||
3c9ee7ef | 459 | #include <asm-generic/bitops/non-atomic.h> |
1da177e4 LT |
460 | |
461 | /* | |
ec917c2c | 462 | * Return the bit position (0..63) of the most significant 1 bit in a word |
65903265 RB |
463 | * Returns -1 if no 1 bit exists |
464 | */ | |
ec917c2c | 465 | static inline int __ilog2(unsigned long x) |
65903265 RB |
466 | { |
467 | int lz; | |
468 | ||
ec917c2c | 469 | if (sizeof(x) == 4) { |
49a89efb | 470 | __asm__( |
ec917c2c RB |
471 | " .set push \n" |
472 | " .set mips32 \n" | |
473 | " clz %0, %1 \n" | |
474 | " .set pop \n" | |
475 | : "=r" (lz) | |
476 | : "r" (x)); | |
65903265 | 477 | |
ec917c2c RB |
478 | return 31 - lz; |
479 | } | |
480 | ||
481 | BUG_ON(sizeof(x) != 8); | |
65903265 | 482 | |
49a89efb | 483 | __asm__( |
65903265 RB |
484 | " .set push \n" |
485 | " .set mips64 \n" | |
486 | " dclz %0, %1 \n" | |
487 | " .set pop \n" | |
488 | : "=r" (lz) | |
489 | : "r" (x)); | |
490 | ||
491 | return 63 - lz; | |
492 | } | |
65903265 | 493 | |
3c9ee7ef AM |
494 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
495 | ||
65903265 RB |
496 | /* |
497 | * __ffs - find first bit in word. | |
1da177e4 LT |
498 | * @word: The word to search |
499 | * | |
65903265 RB |
500 | * Returns 0..SZLONG-1 |
501 | * Undefined if no bit exists, so code should check against 0 first. | |
1da177e4 | 502 | */ |
65903265 | 503 | static inline unsigned long __ffs(unsigned long word) |
1da177e4 | 504 | { |
65903265 | 505 | return __ilog2(word & -word); |
1da177e4 LT |
506 | } |
507 | ||
508 | /* | |
bc818247 | 509 | * fls - find last bit set. |
1da177e4 LT |
510 | * @word: The word to search |
511 | * | |
bc818247 AN |
512 | * This is defined the same way as ffs. |
513 | * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. | |
1da177e4 | 514 | */ |
bc818247 | 515 | static inline int fls(int word) |
1da177e4 | 516 | { |
49a89efb | 517 | __asm__("clz %0, %1" : "=r" (word) : "r" (word)); |
65903265 | 518 | |
bc818247 | 519 | return 32 - word; |
1da177e4 LT |
520 | } |
521 | ||
bc818247 AN |
522 | #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) |
523 | static inline int fls64(__u64 word) | |
65903265 | 524 | { |
49a89efb | 525 | __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); |
bc818247 AN |
526 | |
527 | return 64 - word; | |
65903265 | 528 | } |
bc818247 AN |
529 | #else |
530 | #include <asm-generic/bitops/fls64.h> | |
531 | #endif | |
65903265 RB |
532 | |
533 | /* | |
bc818247 | 534 | * ffs - find first bit set. |
65903265 RB |
535 | * @word: The word to search |
536 | * | |
bc818247 AN |
537 | * This is defined the same way as |
538 | * the libc and compiler builtin ffs routines, therefore | |
539 | * differs in spirit from the above ffz (man ffs). | |
65903265 | 540 | */ |
bc818247 | 541 | static inline int ffs(int word) |
65903265 | 542 | { |
bc818247 AN |
543 | if (!word) |
544 | return 0; | |
2caf1900 | 545 | |
bc818247 | 546 | return fls(word & -word); |
65903265 RB |
547 | } |
548 | ||
3c9ee7ef | 549 | #else |
1da177e4 | 550 | |
3c9ee7ef AM |
551 | #include <asm-generic/bitops/__ffs.h> |
552 | #include <asm-generic/bitops/ffs.h> | |
3c9ee7ef | 553 | #include <asm-generic/bitops/fls.h> |
bc818247 | 554 | #include <asm-generic/bitops/fls64.h> |
1da177e4 | 555 | |
3c9ee7ef | 556 | #endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ |
1da177e4 | 557 | |
bc818247 | 558 | #include <asm-generic/bitops/ffz.h> |
3c9ee7ef | 559 | #include <asm-generic/bitops/find.h> |
1da177e4 LT |
560 | |
561 | #ifdef __KERNEL__ | |
562 | ||
3c9ee7ef AM |
563 | #include <asm-generic/bitops/sched.h> |
564 | #include <asm-generic/bitops/hweight.h> | |
26333576 | 565 | #include <asm-generic/bitops/lock.h> |
3c9ee7ef AM |
566 | #include <asm-generic/bitops/ext2-non-atomic.h> |
567 | #include <asm-generic/bitops/ext2-atomic.h> | |
568 | #include <asm-generic/bitops/minix.h> | |
1da177e4 LT |
569 | |
570 | #endif /* __KERNEL__ */ | |
571 | ||
572 | #endif /* _ASM_BITOPS_H */ |