[deliverable/linux.git] / include / asm-mips / cpu.h

/*
 * cpu.h: Values of the PRId register used to match up
 *        various MIPS cpu types.
 *
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef _ASM_CPU_H
#define _ASM_CPU_H

/* Assigned Company values for bits 23:16 of the PRId Register
   (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
   MTI, the PRId register is defined in this (backwards compatible)
   way:

  +----------------+----------------+----------------+----------------+
  | Company Options| Company ID     | Processor ID   | Revision       |
  +----------------+----------------+----------------+----------------+
   31            24 23            16 15             8 7

   I don't have docs for all the previous processors, but my impression is
   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
   spec.
*/

#define PRID_COMP_LEGACY	0x000000
#define PRID_COMP_MIPS		0x010000
#define PRID_COMP_BROADCOM	0x020000
#define PRID_COMP_ALCHEMY	0x030000
#define PRID_COMP_SIBYTE	0x040000
#define PRID_COMP_SANDCRAFT	0x050000
#define PRID_COMP_PHILIPS	0x060000
#define PRID_COMP_TOSHIBA	0x070000
#define PRID_COMP_LSI		0x080000
#define PRID_COMP_LEXRA		0x0b0000


/*
 * Assigned values for the product ID register.  In order to detect a
 * certain CPU type exactly eventually additional registers may need to
 * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
 */
#define PRID_IMP_R2000		0x0100
#define PRID_IMP_AU1_REV1	0x0100
#define PRID_IMP_AU1_REV2	0x0200
#define PRID_IMP_R3000		0x0200		/* Same as R2000A  */
#define PRID_IMP_R6000		0x0300		/* Same as R3000A  */
#define PRID_IMP_R4000		0x0400
#define PRID_IMP_R6000A		0x0600
#define PRID_IMP_R10000		0x0900
#define PRID_IMP_R4300		0x0b00
#define PRID_IMP_VR41XX		0x0c00
#define PRID_IMP_R12000		0x0e00
#define PRID_IMP_R14000		0x0f00
#define PRID_IMP_R8000		0x1000
#define PRID_IMP_PR4450		0x1200
#define PRID_IMP_R4600		0x2000
#define PRID_IMP_R4700		0x2100
#define PRID_IMP_TX39		0x2200
#define PRID_IMP_R4640		0x2200
#define PRID_IMP_R4650		0x2200		/* Same as R4640 */
#define PRID_IMP_R5000		0x2300
#define PRID_IMP_TX49		0x2d00
#define PRID_IMP_SONIC		0x2400
#define PRID_IMP_MAGIC		0x2500
#define PRID_IMP_RM7000		0x2700
#define PRID_IMP_NEVADA		0x2800		/* RM5260 ??? */
#define PRID_IMP_RM9000		0x3400
#define PRID_IMP_R5432		0x5400
#define PRID_IMP_R5500		0x5500

#define PRID_IMP_UNKNOWN	0xff00

/*
 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
 */

#define PRID_IMP_4KC		0x8000
#define PRID_IMP_5KC		0x8100
#define PRID_IMP_20KC		0x8200
#define PRID_IMP_4KEC		0x8400
#define PRID_IMP_4KSC		0x8600
#define PRID_IMP_25KF		0x8800
#define PRID_IMP_5KE		0x8900
#define PRID_IMP_4KECR2		0x9000
#define PRID_IMP_4KEMPR2	0x9100
#define PRID_IMP_4KSD		0x9200
#define PRID_IMP_24K		0x9300
#define PRID_IMP_34K		0x9500
#define PRID_IMP_24KE		0x9600
#define PRID_IMP_74K		0x9700
#define PRID_IMP_LOONGSON1      0x4200
#define PRID_IMP_LOONGSON2      0x6300

/*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 */

#define PRID_IMP_SB1            0x0100
#define PRID_IMP_SB1A           0x1100

/*
 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
 */

#define PRID_IMP_SR71000        0x0400

/*
 * Definitions for 7:0 on legacy processors
 */


#define PRID_REV_TX4927		0x0022
#define PRID_REV_TX4937		0x0030
#define PRID_REV_R4400		0x0040
#define PRID_REV_R3000A		0x0030
#define PRID_REV_R3000		0x0020
#define PRID_REV_R2000A		0x0010
#define PRID_REV_TX3912 	0x0010
#define PRID_REV_TX3922 	0x0030
#define PRID_REV_TX3927 	0x0040
#define PRID_REV_VR4111		0x0050
#define PRID_REV_VR4181		0x0050	/* Same as VR4111 */
#define PRID_REV_VR4121		0x0060
#define PRID_REV_VR4122		0x0070
#define PRID_REV_VR4181A	0x0070	/* Same as VR4122 */
#define PRID_REV_VR4130		0x0080

/*
 * Older processors used to encode processor version and revision in two
 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
 * the patch number.  *ARGH*
 */
#define PRID_REV_ENCODE_44(ver, rev)					\
	((ver) << 4 | (rev))
#define PRID_REV_ENCODE_332(ver, rev, patch)				\
	((ver) << 5 | (rev) << 2 | (patch))

/*
 * FPU implementation/revision register (CP1 control register 0).
 *
 * +---------------------------------+----------------+----------------+
 * | 0                               | Implementation | Revision       |
 * +---------------------------------+----------------+----------------+
 *  31                             16 15             8 7              0
 */

#define FPIR_IMP_NONE		0x0000

#define CPU_UNKNOWN		 0
#define CPU_R2000		 1
#define CPU_R3000		 2
#define CPU_R3000A		 3
#define CPU_R3041		 4
#define CPU_R3051		 5
#define CPU_R3052		 6
#define CPU_R3081		 7
#define CPU_R3081E		 8
#define CPU_R4000PC		 9
#define CPU_R4000SC		10
#define CPU_R4000MC		11
#define CPU_R4200		12
#define CPU_R4400PC		13
#define CPU_R4400SC		14
#define CPU_R4400MC		15
#define CPU_R4600		16
#define CPU_R6000		17
#define CPU_R6000A		18
#define CPU_R8000		19
#define CPU_R10000		20
#define CPU_R12000		21
#define CPU_R4300		22
#define CPU_R4650		23
#define CPU_R4700		24
#define CPU_R5000		25
#define CPU_R5000A		26
#define CPU_R4640		27
#define CPU_NEVADA		28
#define CPU_RM7000		29
#define CPU_R5432		30
#define CPU_4KC			31
#define CPU_5KC			32
#define CPU_R4310		33
#define CPU_SB1			34
#define CPU_TX3912		35
#define CPU_TX3922		36
#define CPU_TX3927		37
#define CPU_AU1000		38
#define CPU_4KEC		39
#define CPU_4KSC		40
#define CPU_VR41XX		41
#define CPU_R5500		42
#define CPU_TX49XX		43
#define CPU_AU1500		44
#define CPU_20KC		45
#define CPU_VR4111		46
#define CPU_VR4121		47
#define CPU_VR4122		48
#define CPU_VR4131		49
#define CPU_VR4181		50
#define CPU_VR4181A		51
#define CPU_AU1100		52
#define CPU_SR71000		53
#define CPU_RM9000		54
#define CPU_25KF		55
#define CPU_VR4133		56
#define CPU_AU1550		57
#define CPU_24K			58
#define CPU_AU1200		59
#define CPU_34K			60
#define CPU_PR4450		61
#define CPU_SB1A		62
#define CPU_74K			63
#define CPU_R14000		64
#define CPU_LOONGSON1           65
#define CPU_LOONGSON2           66

#define CPU_LAST		66

/*
 * ISA Level encodings
 *
 */
#define MIPS_CPU_ISA_I		0x00000001
#define MIPS_CPU_ISA_II		0x00000002
#define MIPS_CPU_ISA_III	0x00000004
#define MIPS_CPU_ISA_IV		0x00000008
#define MIPS_CPU_ISA_V		0x00000010
#define MIPS_CPU_ISA_M32R1	0x00000020
#define MIPS_CPU_ISA_M32R2	0x00000040
#define MIPS_CPU_ISA_M64R1	0x00000080
#define MIPS_CPU_ISA_M64R2	0x00000100

#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
	MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
	MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)

/*
 * CPU Option encodings
 */
#define MIPS_CPU_TLB		0x00000001 /* CPU has TLB */
#define MIPS_CPU_4KEX		0x00000002 /* "R4K" exception model */
#define MIPS_CPU_3K_CACHE	0x00000004 /* R3000-style caches */
#define MIPS_CPU_4K_CACHE	0x00000008 /* R4000-style caches */
#define MIPS_CPU_TX39_CACHE	0x00000010 /* TX3900-style caches */
#define MIPS_CPU_SB1_CACHE	0x00000020 /* SB1-style caches */
#define MIPS_CPU_FPU		0x00000040 /* CPU has FPU */
#define MIPS_CPU_32FPR		0x00000080 /* 32 dbl. prec. FP registers */
#define MIPS_CPU_COUNTER	0x00000100 /* Cycle count/compare */
#define MIPS_CPU_WATCH		0x00000200 /* watchpoint registers */
#define MIPS_CPU_DIVEC		0x00000400 /* dedicated interrupt vector */
#define MIPS_CPU_VCE		0x00000800 /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX_P	0x00001000 /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_CACHE_CDEX_S	0x00002000 /* ... same for seconary cache ... */
#define MIPS_CPU_MCHECK		0x00004000 /* Machine check exception */
#define MIPS_CPU_EJTAG		0x00008000 /* EJTAG exception */
#define MIPS_CPU_NOFPUEX	0x00010000 /* no FPU exception */
#define MIPS_CPU_LLSC		0x00020000 /* CPU has ll/sc instructions */
#define MIPS_CPU_INCLUSIVE_CACHES	0x00040000 /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH	0x00080000 /* CPU has usable prefetch */
#define MIPS_CPU_VINT		0x00100000 /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC		0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_ULRI		0x00400000 /* CPU has ULRI feature */

/*
 * CPU ASE encodings
 */
#define MIPS_ASE_MIPS16		0x00000001 /* code compression */
#define MIPS_ASE_MDMX		0x00000002 /* MIPS digital media extension */
#define MIPS_ASE_MIPS3D		0x00000004 /* MIPS-3D */
#define MIPS_ASE_SMARTMIPS	0x00000008 /* SmartMIPS */
#define MIPS_ASE_DSP		0x00000010 /* Signal Processing ASE */
#define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */


#endif /* _ASM_CPU_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* cpu.h: Values of the PRId register used to match up
	3	* various MIPS cpu types.
	4	*
	5	* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
4194318c	6	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	7	*/
	8	#ifndef _ASM_CPU_H
	9	#define _ASM_CPU_H
	10
	11	/* Assigned Company values for bits 23:16 of the PRId Register
	12	(CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
	13	MTI, the PRId register is defined in this (backwards compatible)
	14	way:
	15
	16	+----------------+----------------+----------------+----------------+
	17	\| Company Options\| Company ID \| Processor ID \| Revision \|
	18	+----------------+----------------+----------------+----------------+
	19	31 24 23 16 15 8 7
	20
	21	I don't have docs for all the previous processors, but my impression is
	22	that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
	23	spec.
	24	*/
	25
55a6feb6 RB	26	#define PRID_COMP_LEGACY 0x000000
	27	#define PRID_COMP_MIPS 0x010000
	28	#define PRID_COMP_BROADCOM 0x020000
	29	#define PRID_COMP_ALCHEMY 0x030000
	30	#define PRID_COMP_SIBYTE 0x040000
	31	#define PRID_COMP_SANDCRAFT 0x050000
	32	#define PRID_COMP_PHILIPS 0x060000
	33	#define PRID_COMP_TOSHIBA 0x070000
	34	#define PRID_COMP_LSI 0x080000
	35	#define PRID_COMP_LEXRA 0x0b0000
	36
1da177e4 LT	37
	38	/*
	39	* Assigned values for the product ID register. In order to detect a
	40	* certain CPU type exactly eventually additional registers may need to
	41	* be examined. These are valid when 23:16 == PRID_COMP_LEGACY
	42	*/
	43	#define PRID_IMP_R2000 0x0100
	44	#define PRID_IMP_AU1_REV1 0x0100
	45	#define PRID_IMP_AU1_REV2 0x0200
	46	#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
	47	#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
	48	#define PRID_IMP_R4000 0x0400
	49	#define PRID_IMP_R6000A 0x0600
	50	#define PRID_IMP_R10000 0x0900
	51	#define PRID_IMP_R4300 0x0b00
	52	#define PRID_IMP_VR41XX 0x0c00
	53	#define PRID_IMP_R12000 0x0e00
44d921b2	54	#define PRID_IMP_R14000 0x0f00
1da177e4	55	#define PRID_IMP_R8000 0x1000
bdf21b18	56	#define PRID_IMP_PR4450 0x1200
1da177e4 LT	57	#define PRID_IMP_R4600 0x2000
	58	#define PRID_IMP_R4700 0x2100
	59	#define PRID_IMP_TX39 0x2200
	60	#define PRID_IMP_R4640 0x2200
	61	#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
	62	#define PRID_IMP_R5000 0x2300
	63	#define PRID_IMP_TX49 0x2d00
	64	#define PRID_IMP_SONIC 0x2400
	65	#define PRID_IMP_MAGIC 0x2500
	66	#define PRID_IMP_RM7000 0x2700
	67	#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
	68	#define PRID_IMP_RM9000 0x3400
	69	#define PRID_IMP_R5432 0x5400
	70	#define PRID_IMP_R5500 0x5500
98e316d4 MR	71
	72	#define PRID_IMP_UNKNOWN 0xff00
	73
	74	/*
	75	* These are the PRID's for when 23:16 == PRID_COMP_MIPS
	76	*/
	77
1da177e4 LT	78	#define PRID_IMP_4KC 0x8000
	79	#define PRID_IMP_5KC 0x8100
	80	#define PRID_IMP_20KC 0x8200
	81	#define PRID_IMP_4KEC 0x8400
	82	#define PRID_IMP_4KSC 0x8600
	83	#define PRID_IMP_25KF 0x8800
	84	#define PRID_IMP_5KE 0x8900
	85	#define PRID_IMP_4KECR2 0x9000
	86	#define PRID_IMP_4KEMPR2 0x9100
	87	#define PRID_IMP_4KSD 0x9200
	88	#define PRID_IMP_24K 0x9300
bbc7f22f	89	#define PRID_IMP_34K 0x9500
e50c0a8f	90	#define PRID_IMP_24KE 0x9600
c620953c	91	#define PRID_IMP_74K 0x9700
2a21c730 FZ	92	#define PRID_IMP_LOONGSON1 0x4200
2a21c730 FZ	93	#define PRID_IMP_LOONGSON2 0x6300
1da177e4	94
1da177e4 LT	95	/*
	96	* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
	97	*/
	98
	99	#define PRID_IMP_SB1 0x0100
93ce2f52	100	#define PRID_IMP_SB1A 0x1100
1da177e4 LT	101
	102	/*
	103	* These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
	104	*/
	105
	106	#define PRID_IMP_SR71000 0x0400
	107
	108	/*
	109	* Definitions for 7:0 on legacy processors
	110	*/
	111
	112
	113	#define PRID_REV_TX4927 0x0022
	114	#define PRID_REV_TX4937 0x0030
	115	#define PRID_REV_R4400 0x0040
	116	#define PRID_REV_R3000A 0x0030
	117	#define PRID_REV_R3000 0x0020
	118	#define PRID_REV_R2000A 0x0010
	119	#define PRID_REV_TX3912 0x0010
	120	#define PRID_REV_TX3922 0x0030
	121	#define PRID_REV_TX3927 0x0040
	122	#define PRID_REV_VR4111 0x0050
	123	#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
	124	#define PRID_REV_VR4121 0x0060
	125	#define PRID_REV_VR4122 0x0070
	126	#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
	127	#define PRID_REV_VR4130 0x0080
	128
fde97822 RB	129	/*
	130	* Older processors used to encode processor version and revision in two
	131	* 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
	132	* have switched to use the 8-bits as 3:3:2 bitfield with the last field as
	133	* the patch number. ARGH
	134	*/
	135	#define PRID_REV_ENCODE_44(ver, rev) \
	136	((ver) << 4 \| (rev))
	137	#define PRID_REV_ENCODE_332(ver, rev, patch) \
	138	((ver) << 5 \| (rev) << 2 \| (patch))
	139
1da177e4 LT	140	/*
	141	* FPU implementation/revision register (CP1 control register 0).
	142	*
	143	* +---------------------------------+----------------+----------------+
	144	* \| 0 \| Implementation \| Revision \|
	145	* +---------------------------------+----------------+----------------+
	146	* 31 16 15 8 7 0
	147	*/
	148
	149	#define FPIR_IMP_NONE 0x0000
	150
	151	#define CPU_UNKNOWN 0
	152	#define CPU_R2000 1
	153	#define CPU_R3000 2
	154	#define CPU_R3000A 3
	155	#define CPU_R3041 4
	156	#define CPU_R3051 5
	157	#define CPU_R3052 6
	158	#define CPU_R3081 7
	159	#define CPU_R3081E 8
	160	#define CPU_R4000PC 9
	161	#define CPU_R4000SC 10
	162	#define CPU_R4000MC 11
	163	#define CPU_R4200 12
	164	#define CPU_R4400PC 13
	165	#define CPU_R4400SC 14
	166	#define CPU_R4400MC 15
	167	#define CPU_R4600 16
	168	#define CPU_R6000 17
	169	#define CPU_R6000A 18
	170	#define CPU_R8000 19
	171	#define CPU_R10000 20
	172	#define CPU_R12000 21
	173	#define CPU_R4300 22
	174	#define CPU_R4650 23
	175	#define CPU_R4700 24
	176	#define CPU_R5000 25
	177	#define CPU_R5000A 26
	178	#define CPU_R4640 27
	179	#define CPU_NEVADA 28
	180	#define CPU_RM7000 29
	181	#define CPU_R5432 30
	182	#define CPU_4KC 31
	183	#define CPU_5KC 32
	184	#define CPU_R4310 33
	185	#define CPU_SB1 34
	186	#define CPU_TX3912 35
	187	#define CPU_TX3922 36
	188	#define CPU_TX3927 37
	189	#define CPU_AU1000 38
	190	#define CPU_4KEC 39
	191	#define CPU_4KSC 40
	192	#define CPU_VR41XX 41
	193	#define CPU_R5500 42
	194	#define CPU_TX49XX 43
	195	#define CPU_AU1500 44
	196	#define CPU_20KC 45
	197	#define CPU_VR4111 46
	198	#define CPU_VR4121 47
	199	#define CPU_VR4122 48
	200	#define CPU_VR4131 49
	201	#define CPU_VR4181 50
	202	#define CPU_VR4181A 51
	203	#define CPU_AU1100 52
204	#define CPU_SR71000 53
205	#define CPU_RM9000 54
206	#define CPU_25KF 55
207	#define CPU_VR4133 56
208	#define CPU_AU1550 57
209	#define CPU_24K 58
e3ad1c23	210	#define CPU_AU1200 59
bbc7f22f	211	#define CPU_34K 60
bdf21b18	212	#define CPU_PR4450 61
93ce2f52	213	#define CPU_SB1A 62
c620953c	214	#define CPU_74K 63
44d921b2	215	#define CPU_R14000 64
2a21c730 FZ	216	#define CPU_LOONGSON1 65
	217	#define CPU_LOONGSON2 66
	218
	219	#define CPU_LAST 66
1da177e4 LT	220
	221	/*
	222	* ISA Level encodings
	223	*
	224	*/
	225	#define MIPS_CPU_ISA_I 0x00000001
	226	#define MIPS_CPU_ISA_II 0x00000002
9cf8ff96 MR	227	#define MIPS_CPU_ISA_III 0x00000004
	228	#define MIPS_CPU_ISA_IV 0x00000008
	229	#define MIPS_CPU_ISA_V 0x00000010
e7958bb9	230	#define MIPS_CPU_ISA_M32R1 0x00000020
b4672d37	231	#define MIPS_CPU_ISA_M32R2 0x00000040
0401572a RB	232	#define MIPS_CPU_ISA_M64R1 0x00000080
	233	#define MIPS_CPU_ISA_M64R2 0x00000100
	234
	235	#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I \| MIPS_CPU_ISA_II \| \
	236	MIPS_CPU_ISA_M32R1 \| MIPS_CPU_ISA_M32R2 )
	237	#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III \| MIPS_CPU_ISA_IV \| \
	238	MIPS_CPU_ISA_V \| MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2)
1da177e4 LT	239
	240	/*
	241	* CPU Option encodings
	242	*/
	243	#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
02cf2119 RB	244	#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
	245	#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
	246	#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
	247	#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
	248	#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */
	249	#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */
	250	#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */
	251	#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */
	252	#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */
	253	#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */
	254	#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */
	255	#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */
	256	#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */
	257	#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */
	258	#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */
	259	#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */
	260	#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */
fc5d2d27	261	#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */
02cf2119 RB	262	#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
	263	#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
	264	#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
a3692020	265	#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */
1da177e4	266
4194318c RB	267	/*
	268	* CPU ASE encodings
	269	*/
	270	#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
	271	#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
	272	#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
	273	#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
e50c0a8f	274	#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
8f40611d RB	275	#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
8f40611d RB	276
4194318c	277
1da177e4	278	#endif /* _ASM_CPU_H */