[deliverable/linux.git] / include / asm-mips / hazards.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle
 */
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H

#include <linux/config.h>

#ifdef __ASSEMBLY__

	.macro	_ssnop
	sll	$0, $0, 1
	.endm

	.macro	_ehb
	sll	$0, $0, 3
	.endm

/*
 * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
 * for data translations should not occur for 3 cpu cycles.
 */
#ifdef CONFIG_CPU_RM9000

	.macro	mtc0_tlbw_hazard
	.set	push
	.set	mips32
	_ssnop; _ssnop; _ssnop; _ssnop
	.set	pop
	.endm

	.macro	tlbw_eret_hazard
	.set	push
	.set	mips32
	_ssnop; _ssnop; _ssnop; _ssnop
	.set	pop
	.endm

#else

/*
 * The taken branch will result in a two cycle penalty for the two killed
 * instructions on R4000 / R4400.  Other processors only have a single cycle
 * hazard so this is nice trick to have an optimal code for a range of
 * processors.
 */
	.macro	mtc0_tlbw_hazard
	b	. + 8
	.endm

	.macro	tlbw_eret_hazard
	.endm
#endif

/*
 * mtc0->mfc0 hazard
 * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
 * It is a MIPS32R2 processor so ehb will clear the hazard.
 */

#ifdef CONFIG_CPU_MIPSR2
/*
 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
 */

#define irq_enable_hazard
	_ehb

#define irq_disable_hazard
	_ehb

#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
      defined(CONFIG_CPU_SB1)

/*
 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
 */

#define irq_enable_hazard

#define irq_disable_hazard

#else

/*
 * Classic MIPS needs 1 - 3 nops or ssnops
 */
#define irq_enable_hazard
#define irq_disable_hazard						\
	_ssnop; _ssnop; _ssnop

#endif

#else /* __ASSEMBLY__ */

__asm__(
	"	.macro	_ssnop					\n\t"
	"	sll	$0, $0, 1				\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro	_ehb					\n\t"
	"	sll	$0, $0, 3				\n\t"
	"	.endm						\n\t");

#ifdef CONFIG_CPU_RM9000

/*
 * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
 * for data translations should not occur for 3 cpu cycles.
 */

#define mtc0_tlbw_hazard()						\
	__asm__ __volatile__(						\
		".set\tmips32\n\t"					\
		"_ssnop; _ssnop; _ssnop; _ssnop\n\t"			\
		".set\tmips0")

#define tlbw_use_hazard()						\
	__asm__ __volatile__(						\
		".set\tmips32\n\t"					\
		"_ssnop; _ssnop; _ssnop; _ssnop\n\t"			\
		".set\tmips0")

#define back_to_back_c0_hazard()	do { } while (0)

#else

/*
 * Overkill warning ...
 */
#define mtc0_tlbw_hazard()						\
	__asm__ __volatile__(						\
		".set noreorder\n\t"					\
		"nop; nop; nop; nop; nop; nop;\n\t"			\
		".set reorder\n\t")

#define tlbw_use_hazard()						\
	__asm__ __volatile__(						\
		".set noreorder\n\t"					\
		"nop; nop; nop; nop; nop; nop;\n\t"			\
		".set reorder\n\t")

#endif

/*
 * Interrupt enable/disable hazards
 * Some processors have hazards when modifying
 * the status register to change the interrupt state
 */

#ifdef CONFIG_CPU_MIPSR2

__asm__(
	"	.macro\tirq_enable_hazard			\n\t"
	"	_ehb						\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro\tirq_disable_hazard			\n\t"
	"	_ehb						\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro\tback_to_back_c0_hazard			\n\t"
	"	_ehb						\n\t"
	"	.endm");

#define irq_enable_hazard()						\
	__asm__ __volatile__(						\
	"irq_enable_hazard")

#define irq_disable_hazard()						\
	__asm__ __volatile__(						\
	"irq_disable_hazard")

#define back_to_back_c0_hazard()					\
	__asm__ __volatile__(						\
	"back_to_back_c0_hazard")

#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
      defined(CONFIG_CPU_SB1)

/*
 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
 */

__asm__(
	"	.macro\tirq_enable_hazard			\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro\tirq_disable_hazard			\n\t"
	"	.endm");

#define irq_enable_hazard()	do { } while (0)
#define irq_disable_hazard()	do { } while (0)

#define back_to_back_c0_hazard()	do { } while (0)

#else

/*
 * Default for classic MIPS processors.  Assume worst case hazards but don't
 * care about the irq_enable_hazard - sooner or later the hardware will
 * enable it and we don't care when exactly.
 */

__asm__(
	"	#						\n\t"
	"	# There is a hazard but we do not care		\n\t"
	"	#						\n\t"
	"	.macro\tirq_enable_hazard			\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro\tirq_disable_hazard			\n\t"
	"	_ssnop; _ssnop; _ssnop				\n\t"
	"	.endm");

#define irq_enable_hazard()	do { } while (0)
#define irq_disable_hazard()						\
	__asm__ __volatile__(						\
	"irq_disable_hazard")

#define back_to_back_c0_hazard()					\
	__asm__ __volatile__(						\
	"	.set noreorder				\n"		\
	"	nop; nop; nop				\n"		\
	"	.set reorder				\n")

#endif

#ifdef CONFIG_CPU_MIPSR2
/*
 * gcc has a tradition of misscompiling the previous construct using the
 * address of a label as argument to inline assembler.  Gas otoh has the
 * annoying difference between la and dla which are only usable for 32-bit
 * rsp. 64-bit code, so can't be used without conditional compilation.
 * The alterantive is switching the assembler to 64-bit code which happens
 * to work right even for 32-bit code ...
 */
#define instruction_hazard()						\
do {									\
	unsigned long tmp;						\
									\
	__asm__ __volatile__(						\
	"	.set	mips64r2				\n"	\
	"	dla	%0, 1f					\n"	\
	"	jr.hb	%0					\n"	\
	"	.set	mips0					\n"	\
	"1:							\n"	\
	: "=r" (tmp));							\
} while (0)

#else
#define instruction_hazard() do { } while (0)
#endif

#endif /* __ASSEMBLY__ */

#endif /* _ASM_HAZARDS_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003, 2004 Ralf Baechle
	7	*/
	8	#ifndef _ASM_HAZARDS_H
	9	#define _ASM_HAZARDS_H
	10
	11	#include <linux/config.h>
	12
	13	#ifdef __ASSEMBLY__
	14
	15	.macro _ssnop
	16	sll $0, $0, 1
	17	.endm
	18
	19	.macro _ehb
	20	sll $0, $0, 3
	21	.endm
	22
	23	/*
	24	* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
	25	* use of the JTLB for instructions should not occur for 4 cpu cycles and use
	26	* for data translations should not occur for 3 cpu cycles.
	27	*/
	28	#ifdef CONFIG_CPU_RM9000
	29
	30	.macro mtc0_tlbw_hazard
	31	.set push
	32	.set mips32
	33	_ssnop; _ssnop; _ssnop; _ssnop
	34	.set pop
	35	.endm
	36
	37	.macro tlbw_eret_hazard
	38	.set push
	39	.set mips32
	40	_ssnop; _ssnop; _ssnop; _ssnop
	41	.set pop
	42	.endm
	43
	44	#else
	45
	46	/*
	47	* The taken branch will result in a two cycle penalty for the two killed
	48	* instructions on R4000 / R4400. Other processors only have a single cycle
	49	* hazard so this is nice trick to have an optimal code for a range of
	50	* processors.
	51	*/
	52	.macro mtc0_tlbw_hazard
	53	b . + 8
	54	.endm
	55
	56	.macro tlbw_eret_hazard
	57	.endm
	58	#endif
	59
	60	/*
	61	* mtc0->mfc0 hazard
	62	* The 24K has a 2 cycle mtc0/mfc0 execution hazard.
	63	* It is a MIPS32R2 processor so ehb will clear the hazard.
	64	*/
65
66	#ifdef CONFIG_CPU_MIPSR2
67	/*
68	* Use a macro for ehb unless explicit support for MIPSR2 is enabled
69	*/
70
71	#define irq_enable_hazard
72	_ehb
73
74	#define irq_disable_hazard
75	_ehb
76
f5cfa980 RB	77	#elif defined(CONFIG_CPU_R10000) \|\| defined(CONFIG_CPU_RM9000) \|\| \
f5cfa980 RB	78	defined(CONFIG_CPU_SB1)
1da177e4 LT	79
	80	/*
	81	* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
	82	*/
	83
	84	#define irq_enable_hazard
	85
	86	#define irq_disable_hazard
	87
	88	#else
	89
	90	/*
	91	* Classic MIPS needs 1 - 3 nops or ssnops
	92	*/
	93	#define irq_enable_hazard
	94	#define irq_disable_hazard \
	95	_ssnop; _ssnop; _ssnop
	96
	97	#endif
	98
	99	#else /* __ASSEMBLY__ */
	100
	101	__asm__(
	102	" .macro _ssnop \n\t"
05faa7b7	103	" sll $0, $0, 1 \n\t"
1da177e4 LT	104	" .endm \n\t"
	105	" \n\t"
	106	" .macro _ehb \n\t"
	107	" sll $0, $0, 3 \n\t"
	108	" .endm \n\t");
	109
	110	#ifdef CONFIG_CPU_RM9000
88d535b6	111
1da177e4 LT	112	/*
	113	* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
	114	* use of the JTLB for instructions should not occur for 4 cpu cycles and use
	115	* for data translations should not occur for 3 cpu cycles.
	116	*/
	117
	118	#define mtc0_tlbw_hazard() \
	119	__asm__ __volatile__( \
	120	".set\tmips32\n\t" \
	121	"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
	122	".set\tmips0")
	123
	124	#define tlbw_use_hazard() \
	125	__asm__ __volatile__( \
	126	".set\tmips32\n\t" \
	127	"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
	128	".set\tmips0")
5068debf RB	129
	130	#define back_to_back_c0_hazard() do { } while (0)
	131
1da177e4 LT	132	#else
	133
	134	/*
	135	* Overkill warning ...
	136	*/
	137	#define mtc0_tlbw_hazard() \
	138	__asm__ __volatile__( \
	139	".set noreorder\n\t" \
	140	"nop; nop; nop; nop; nop; nop;\n\t" \
	141	".set reorder\n\t")
	142
	143	#define tlbw_use_hazard() \
	144	__asm__ __volatile__( \
	145	".set noreorder\n\t" \
	146	"nop; nop; nop; nop; nop; nop;\n\t" \
	147	".set reorder\n\t")
	148
	149	#endif
	150
	151	/*
86071b63 RB	152	* Interrupt enable/disable hazards
	153	* Some processors have hazards when modifying
	154	* the status register to change the interrupt state
1da177e4 LT	155	*/
	156
	157	#ifdef CONFIG_CPU_MIPSR2
86071b63	158
1da177e4 LT	159	__asm__(
	160	" .macro\tirq_enable_hazard \n\t"
	161	" _ehb \n\t"
	162	" .endm \n\t"
	163	" \n\t"
	164	" .macro\tirq_disable_hazard \n\t"
	165	" _ehb \n\t"
86071b63 RB	166	" .endm \n\t"
	167	" \n\t"
	168	" .macro\tback_to_back_c0_hazard \n\t"
	169	" _ehb \n\t"
1da177e4 LT	170	" .endm");
	171
	172	#define irq_enable_hazard() \
	173	__asm__ __volatile__( \
86071b63	174	"irq_enable_hazard")
1da177e4 LT	175
	176	#define irq_disable_hazard() \
	177	__asm__ __volatile__( \
86071b63	178	"irq_disable_hazard")
1da177e4	179
5068debf RB	180	#define back_to_back_c0_hazard() \
5068debf RB	181	__asm__ __volatile__( \
86071b63	182	"back_to_back_c0_hazard")
5068debf	183
f5cfa980 RB	184	#elif defined(CONFIG_CPU_R10000) \|\| defined(CONFIG_CPU_RM9000) \|\| \
f5cfa980 RB	185	defined(CONFIG_CPU_SB1)
1da177e4 LT	186
	187	/*
	188	* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
	189	*/
	190
	191	__asm__(
	192	" .macro\tirq_enable_hazard \n\t"
	193	" .endm \n\t"
	194	" \n\t"
	195	" .macro\tirq_disable_hazard \n\t"
	196	" .endm");
	197
	198	#define irq_enable_hazard() do { } while (0)
	199	#define irq_disable_hazard() do { } while (0)
	200
5068debf RB	201	#define back_to_back_c0_hazard() do { } while (0)
5068debf RB	202
1da177e4 LT	203	#else
	204
	205	/*
	206	* Default for classic MIPS processors. Assume worst case hazards but don't
	207	* care about the irq_enable_hazard - sooner or later the hardware will
	208	* enable it and we don't care when exactly.
	209	*/
	210
	211	__asm__(
	212	" # \n\t"
	213	" # There is a hazard but we do not care \n\t"
	214	" # \n\t"
	215	" .macro\tirq_enable_hazard \n\t"
	216	" .endm \n\t"
	217	" \n\t"
	218	" .macro\tirq_disable_hazard \n\t"
	219	" _ssnop; _ssnop; _ssnop \n\t"
	220	" .endm");
	221
	222	#define irq_enable_hazard() do { } while (0)
	223	#define irq_disable_hazard() \
	224	__asm__ __volatile__( \
86071b63	225	"irq_disable_hazard")
1da177e4	226
5068debf RB	227	#define back_to_back_c0_hazard() \
	228	__asm__ __volatile__( \
	229	" .set noreorder \n" \
	230	" nop; nop; nop \n" \
	231	" .set reorder \n")
	232
1da177e4 LT	233	#endif
1da177e4 LT	234
ec917c2c	235	#ifdef CONFIG_CPU_MIPSR2
7043ad4f RB	236	/*
	237	* gcc has a tradition of misscompiling the previous construct using the
	238	* address of a label as argument to inline assembler. Gas otoh has the
	239	* annoying difference between la and dla which are only usable for 32-bit
	240	* rsp. 64-bit code, so can't be used without conditional compilation.
	241	* The alterantive is switching the assembler to 64-bit code which happens
	242	* to work right even for 32-bit code ...
	243	*/
cc61c1fe RB	244	#define instruction_hazard() \
cc61c1fe RB	245	do { \
7043ad4f RB	246	unsigned long tmp; \
7043ad4f RB	247	\
cc61c1fe	248	__asm__ __volatile__( \
7043ad4f RB	249	" .set mips64r2 \n" \
7043ad4f RB	250	" dla %0, 1f \n" \
cc61c1fe	251	" jr.hb %0 \n" \
7043ad4f RB	252	" .set mips0 \n" \
	253	"1: \n" \
	254	: "=r" (tmp)); \
cc61c1fe RB	255	} while (0)
	256
	257	#else
	258	#define instruction_hazard() do { } while (0)
	259	#endif
	260
1da177e4 LT	261	#endif /* __ASSEMBLY__ */
	262
	263	#endif /* _ASM_HAZARDS_H */