projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | * License. See the file "COPYING" in the main directory of this archive | |
| 4 | * for more details. | |
| 5 | * | |
| 6 | * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle | |
| 7 | * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle | |
| 8 | */ | |
| 9 | #ifndef _ASM_IRQ_H | |
| 10 | #define _ASM_IRQ_H | |
| 11 | ||
| 1da177e4 | 12 | #include <linux/linkage.h> |
| 41c594ab RB |
13 | |
| 14 | #include <asm/mipsmtregs.h> | |
| 15 | ||
| 1da177e4 LT |
16 | #include <irq.h> |
| 17 | ||
| 18 | #ifdef CONFIG_I8259 | |
| 19 | static inline int irq_canonicalize(int irq) | |
| 20 | { | |
| 2fa7937b | 21 | return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); |
| 1da177e4 LT |
22 | } |
| 23 | #else | |
| 24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ | |
| 25 | #endif | |
| 26 | ||
| 1146fe30 RB |
27 | #ifdef CONFIG_MIPS_MT_SMTC |
| 28 | ||
| 29 | struct irqaction; | |
| 30 | ||
| 31 | extern unsigned long irq_hwmask[]; | |
| 32 | extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, | |
| 33 | unsigned long hwmask); | |
| 34 | ||
| 35 | static inline void smtc_im_ack_irq(unsigned int irq) | |
| 36 | { | |
| 37 | if (irq_hwmask[irq] & ST0_IM) | |
| 38 | set_c0_status(irq_hwmask[irq] & ST0_IM); | |
| 39 | } | |
| 40 | ||
| 41 | #else | |
| 42 | ||
| 43 | static inline void smtc_im_ack_irq(unsigned int irq) | |
| 44 | { | |
| 45 | } | |
| 46 | ||
| 47 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
| 48 | ||
| 0db34215 | 49 | #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP |
| 1146fe30 | 50 | |
| 41c594ab RB |
51 | /* |
| 52 | * Clear interrupt mask handling "backstop" if irq_hwmask | |
| 53 | * entry so indicates. This implies that the ack() or end() | |
| 54 | * functions will take over re-enabling the low-level mask. | |
| 55 | * Otherwise it will be done on return from exception. | |
| 56 | */ | |
| f9bba75e | 57 | #define __DO_IRQ_SMTC_HOOK(irq) \ |
| 41c594ab RB |
58 | do { \ |
| 59 | if (irq_hwmask[irq] & 0x0000ff00) \ | |
| 60 | write_c0_tccontext(read_c0_tccontext() & \ | |
| 61 | ~(irq_hwmask[irq] & 0x0000ff00)); \ | |
| 62 | } while (0) | |
| 63 | #else | |
| 1146fe30 | 64 | |
| f9bba75e | 65 | #define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) |
| 41c594ab RB |
66 | #endif |
| 67 | ||
| 1da177e4 LT |
68 | /* |
| 69 | * do_IRQ handles all normal device IRQ's (the special | |
| 70 | * SMP cross-CPU interrupts have their own specific | |
| 71 | * handlers). | |
| 72 | * | |
| 73 | * Ideally there should be away to get this into kernel/irq/handle.c to | |
| 74 | * avoid the overhead of a call for just a tiny function ... | |
| 75 | */ | |
| 937a8015 | 76 | #define do_IRQ(irq) \ |
| 1da177e4 LT |
77 | do { \ |
| 78 | irq_enter(); \ | |
| f9bba75e | 79 | __DO_IRQ_SMTC_HOOK(irq); \ |
| 1417836e | 80 | generic_handle_irq(irq); \ |
| 1da177e4 LT |
81 | irq_exit(); \ |
| 82 | } while (0) | |
| 83 | ||
| 1da177e4 | 84 | extern void arch_init_irq(void); |
| 937a8015 | 85 | extern void spurious_interrupt(void); |
| 1da177e4 | 86 | |
| 4a4cf779 RB |
87 | extern int allocate_irqno(void); |
| 88 | extern void alloc_legacy_irqno(void); | |
| 89 | extern void free_irqno(unsigned int irq); | |
| 90 | ||
| 3b1d4ed5 RB |
91 | /* |
| 92 | * Before R2 the timer and performance counter interrupts were both fixed to | |
| 93 | * IE7. Since R2 their number has to be read from the c0_intctl register. | |
| 94 | */ | |
| 95 | #define CP0_LEGACY_COMPARE_IRQ 7 | |
| 96 | ||
| 97 | extern int cp0_compare_irq; | |
| 98 | extern int cp0_perfcount_irq; | |
| 99 | ||
| 1da177e4 | 100 | #endif /* _ASM_IRQ_H */ |