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26a940e2 PP |
1 | /* |
2 | * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005 | |
3 | * | |
4 | * BRIEF MODULE DESCRIPTION | |
5 | * AMD Alchemy Au1xxx IDE interface routines over the Static Bus | |
6 | * | |
7 | * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it under | |
10 | * the terms of the GNU General Public License as published by the Free Software | |
11 | * Foundation; either version 2 of the License, or (at your option) any later | |
12 | * version. | |
13 | * | |
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, | |
15 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND | |
16 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR | |
17 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
18 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
19 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
20 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
21 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
22 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
23 | * POSSIBILITY OF SUCH DAMAGE. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License along with | |
26 | * this program; if not, write to the Free Software Foundation, Inc., | |
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | * | |
29 | * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE | |
30 | * Interface and Linux Device Driver" Application Note. | |
31 | */ | |
26a940e2 PP |
32 | |
33 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
34 | #define DMA_WAIT_TIMEOUT 100 | |
35 | #define NUM_DESCRIPTORS PRD_ENTRIES | |
36 | #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ | |
37 | #define NUM_DESCRIPTORS 2 | |
38 | #endif | |
39 | ||
40 | #ifndef AU1XXX_ATA_RQSIZE | |
41 | #define AU1XXX_ATA_RQSIZE 128 | |
42 | #endif | |
43 | ||
44 | /* Disable Burstable-Support for DBDMA */ | |
45 | #ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON | |
46 | #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 | |
47 | #endif | |
48 | ||
49 | #ifdef CONFIG_PM | |
50 | /* | |
51 | * This will enable the device to be powered up when write() or read() | |
52 | * is called. If this is not defined, the driver will return -EBUSY. | |
53 | */ | |
54 | #define WAKE_ON_ACCESS 1 | |
55 | ||
56 | typedef struct | |
57 | { | |
58 | spinlock_t lock; /* Used to block on state transitions */ | |
59 | au1xxx_power_dev_t *dev; /* Power Managers device structure */ | |
60 | unsigned stopped; /* USed to signaling device is stopped */ | |
61 | } pm_state; | |
62 | #endif | |
63 | ||
64 | ||
65 | typedef struct | |
66 | { | |
67 | u32 tx_dev_id, rx_dev_id, target_dev_id; | |
68 | u32 tx_chan, rx_chan; | |
69 | void *tx_desc_head, *rx_desc_head; | |
70 | ide_hwif_t *hwif; | |
71 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
72 | ide_drive_t *drive; | |
73 | u8 white_list, black_list; | |
74 | struct dbdma_cmd *dma_table_cpu; | |
75 | dma_addr_t dma_table_dma; | |
26a940e2 PP |
76 | #endif |
77 | struct device *dev; | |
78 | int irq; | |
79 | u32 regbase; | |
80 | #ifdef CONFIG_PM | |
81 | pm_state pm; | |
82 | #endif | |
83 | } _auide_hwif; | |
84 | ||
85 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
26a940e2 PP |
86 | /* HD white list */ |
87 | static const struct drive_list_entry dma_white_list [] = { | |
88 | /* | |
89 | * Hitachi | |
90 | */ | |
91 | { "HITACHI_DK14FA-20" , "ALL" }, | |
92 | { "HTS726060M9AT00" , "ALL" }, | |
93 | /* | |
94 | * Maxtor | |
95 | */ | |
96 | { "Maxtor 6E040L0" , "ALL" }, | |
97 | { "Maxtor 6Y080P0" , "ALL" }, | |
98 | { "Maxtor 6Y160P0" , "ALL" }, | |
99 | /* | |
100 | * Seagate | |
101 | */ | |
102 | { "ST3120026A" , "ALL" }, | |
103 | { "ST320014A" , "ALL" }, | |
104 | { "ST94011A" , "ALL" }, | |
105 | { "ST340016A" , "ALL" }, | |
106 | /* | |
107 | * Western Digital | |
108 | */ | |
109 | { "WDC WD400UE-00HCT0" , "ALL" }, | |
110 | { "WDC WD400JB-00JJC0" , "ALL" }, | |
111 | { NULL , NULL } | |
112 | }; | |
113 | ||
114 | /* HD black list */ | |
115 | static const struct drive_list_entry dma_black_list [] = { | |
116 | /* | |
117 | * Western Digital | |
118 | */ | |
119 | { "WDC WD100EB-00CGH0" , "ALL" }, | |
120 | { "WDC WD200BB-00AUA1" , "ALL" }, | |
121 | { "WDC AC24300L" , "ALL" }, | |
122 | { NULL , NULL } | |
123 | }; | |
124 | #endif | |
125 | ||
126 | /* function prototyping */ | |
127 | u8 auide_inb(unsigned long port); | |
128 | u16 auide_inw(unsigned long port); | |
129 | u32 auide_inl(unsigned long port); | |
130 | void auide_insw(unsigned long port, void *addr, u32 count); | |
131 | void auide_insl(unsigned long port, void *addr, u32 count); | |
132 | void auide_outb(u8 addr, unsigned long port); | |
133 | void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port); | |
134 | void auide_outw(u16 addr, unsigned long port); | |
135 | void auide_outl(u32 addr, unsigned long port); | |
136 | void auide_outsw(unsigned long port, void *addr, u32 count); | |
137 | void auide_outsl(unsigned long port, void *addr, u32 count); | |
138 | static void auide_tune_drive(ide_drive_t *drive, byte pio); | |
139 | static int auide_tune_chipset (ide_drive_t *drive, u8 speed); | |
140 | static int auide_ddma_init( _auide_hwif *auide ); | |
141 | static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif); | |
142 | int __init auide_probe(void); | |
143 | ||
144 | #ifdef CONFIG_PM | |
145 | int au1200ide_pm_callback( au1xxx_power_dev_t *dev, | |
146 | au1xxx_request_t request, void *data); | |
147 | static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev ); | |
148 | static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev ); | |
149 | static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev ); | |
150 | static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev ); | |
151 | static int au1xxxide_pm_access( au1xxx_power_dev_t *dev ); | |
152 | static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev ); | |
153 | static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev ); | |
154 | #endif | |
155 | ||
156 | ||
157 | /* | |
158 | * Multi-Word DMA + DbDMA functions | |
159 | */ | |
160 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
26a940e2 PP |
161 | static int auide_build_sglist(ide_drive_t *drive, struct request *rq); |
162 | static int auide_build_dmatable(ide_drive_t *drive); | |
163 | static int auide_dma_end(ide_drive_t *drive); | |
26a940e2 PP |
164 | ide_startstop_t auide_dma_intr (ide_drive_t *drive); |
165 | static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command); | |
166 | static int auide_dma_setup(ide_drive_t *drive); | |
167 | static int auide_dma_check(ide_drive_t *drive); | |
168 | static int auide_dma_test_irq(ide_drive_t *drive); | |
169 | static int auide_dma_host_off(ide_drive_t *drive); | |
170 | static int auide_dma_host_on(ide_drive_t *drive); | |
171 | static int auide_dma_lostirq(ide_drive_t *drive); | |
172 | static int auide_dma_on(ide_drive_t *drive); | |
ec7080d1 ML |
173 | static void auide_ddma_tx_callback(int irq, void *param); |
174 | static void auide_ddma_rx_callback(int irq, void *param); | |
26a940e2 | 175 | static int auide_dma_off_quietly(ide_drive_t *drive); |
26a940e2 PP |
176 | #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ |
177 | ||
178 | /******************************************************************************* | |
179 | * PIO Mode timing calculation : * | |
180 | * * | |
181 | * Static Bus Spec ATA Spec * | |
182 | * Tcsoe = t1 * | |
183 | * Toecs = t9 * | |
184 | * Twcs = t9 * | |
185 | * Tcsh = t2i | t2 * | |
186 | * Tcsoff = t2i | t2 * | |
187 | * Twp = t2 * | |
188 | * Tcsw = t1 * | |
189 | * Tpm = 0 * | |
190 | * Ta = t1+t2 * | |
191 | *******************************************************************************/ | |
192 | ||
193 | #define TCSOE_MASK (0x07<<29) | |
194 | #define TOECS_MASK (0x07<<26) | |
195 | #define TWCS_MASK (0x07<<28) | |
196 | #define TCSH_MASK (0x0F<<24) | |
197 | #define TCSOFF_MASK (0x07<<20) | |
198 | #define TWP_MASK (0x3F<<14) | |
199 | #define TCSW_MASK (0x0F<<10) | |
200 | #define TPM_MASK (0x0F<<6) | |
201 | #define TA_MASK (0x3F<<0) | |
202 | #define TS_MASK (1<<8) | |
203 | ||
204 | /* Timing parameters PIO mode 0 */ | |
205 | #define SBC_IDE_PIO0_TCSOE (0x04<<29) | |
206 | #define SBC_IDE_PIO0_TOECS (0x01<<26) | |
207 | #define SBC_IDE_PIO0_TWCS (0x02<<28) | |
208 | #define SBC_IDE_PIO0_TCSH (0x08<<24) | |
209 | #define SBC_IDE_PIO0_TCSOFF (0x07<<20) | |
210 | #define SBC_IDE_PIO0_TWP (0x10<<14) | |
211 | #define SBC_IDE_PIO0_TCSW (0x04<<10) | |
212 | #define SBC_IDE_PIO0_TPM (0x0<<6) | |
213 | #define SBC_IDE_PIO0_TA (0x15<<0) | |
214 | /* Timing parameters PIO mode 1 */ | |
215 | #define SBC_IDE_PIO1_TCSOE (0x03<<29) | |
216 | #define SBC_IDE_PIO1_TOECS (0x01<<26) | |
217 | #define SBC_IDE_PIO1_TWCS (0x01<<28) | |
218 | #define SBC_IDE_PIO1_TCSH (0x06<<24) | |
219 | #define SBC_IDE_PIO1_TCSOFF (0x06<<20) | |
220 | #define SBC_IDE_PIO1_TWP (0x08<<14) | |
221 | #define SBC_IDE_PIO1_TCSW (0x03<<10) | |
222 | #define SBC_IDE_PIO1_TPM (0x00<<6) | |
223 | #define SBC_IDE_PIO1_TA (0x0B<<0) | |
224 | /* Timing parameters PIO mode 2 */ | |
225 | #define SBC_IDE_PIO2_TCSOE (0x05<<29) | |
226 | #define SBC_IDE_PIO2_TOECS (0x01<<26) | |
227 | #define SBC_IDE_PIO2_TWCS (0x01<<28) | |
228 | #define SBC_IDE_PIO2_TCSH (0x07<<24) | |
229 | #define SBC_IDE_PIO2_TCSOFF (0x07<<20) | |
230 | #define SBC_IDE_PIO2_TWP (0x1F<<14) | |
231 | #define SBC_IDE_PIO2_TCSW (0x05<<10) | |
232 | #define SBC_IDE_PIO2_TPM (0x00<<6) | |
233 | #define SBC_IDE_PIO2_TA (0x22<<0) | |
234 | /* Timing parameters PIO mode 3 */ | |
235 | #define SBC_IDE_PIO3_TCSOE (0x05<<29) | |
236 | #define SBC_IDE_PIO3_TOECS (0x01<<26) | |
237 | #define SBC_IDE_PIO3_TWCS (0x01<<28) | |
238 | #define SBC_IDE_PIO3_TCSH (0x0D<<24) | |
239 | #define SBC_IDE_PIO3_TCSOFF (0x0D<<20) | |
240 | #define SBC_IDE_PIO3_TWP (0x15<<14) | |
241 | #define SBC_IDE_PIO3_TCSW (0x05<<10) | |
242 | #define SBC_IDE_PIO3_TPM (0x00<<6) | |
243 | #define SBC_IDE_PIO3_TA (0x1A<<0) | |
244 | /* Timing parameters PIO mode 4 */ | |
245 | #define SBC_IDE_PIO4_TCSOE (0x04<<29) | |
246 | #define SBC_IDE_PIO4_TOECS (0x01<<26) | |
247 | #define SBC_IDE_PIO4_TWCS (0x01<<28) | |
248 | #define SBC_IDE_PIO4_TCSH (0x04<<24) | |
249 | #define SBC_IDE_PIO4_TCSOFF (0x04<<20) | |
250 | #define SBC_IDE_PIO4_TWP (0x0D<<14) | |
251 | #define SBC_IDE_PIO4_TCSW (0x03<<10) | |
252 | #define SBC_IDE_PIO4_TPM (0x00<<6) | |
253 | #define SBC_IDE_PIO4_TA (0x12<<0) | |
254 | /* Timing parameters MDMA mode 0 */ | |
255 | #define SBC_IDE_MDMA0_TCSOE (0x03<<29) | |
256 | #define SBC_IDE_MDMA0_TOECS (0x01<<26) | |
257 | #define SBC_IDE_MDMA0_TWCS (0x01<<28) | |
258 | #define SBC_IDE_MDMA0_TCSH (0x07<<24) | |
259 | #define SBC_IDE_MDMA0_TCSOFF (0x07<<20) | |
260 | #define SBC_IDE_MDMA0_TWP (0x0C<<14) | |
261 | #define SBC_IDE_MDMA0_TCSW (0x03<<10) | |
262 | #define SBC_IDE_MDMA0_TPM (0x00<<6) | |
263 | #define SBC_IDE_MDMA0_TA (0x0F<<0) | |
264 | /* Timing parameters MDMA mode 1 */ | |
265 | #define SBC_IDE_MDMA1_TCSOE (0x05<<29) | |
266 | #define SBC_IDE_MDMA1_TOECS (0x01<<26) | |
267 | #define SBC_IDE_MDMA1_TWCS (0x01<<28) | |
268 | #define SBC_IDE_MDMA1_TCSH (0x05<<24) | |
269 | #define SBC_IDE_MDMA1_TCSOFF (0x05<<20) | |
270 | #define SBC_IDE_MDMA1_TWP (0x0F<<14) | |
271 | #define SBC_IDE_MDMA1_TCSW (0x05<<10) | |
272 | #define SBC_IDE_MDMA1_TPM (0x00<<6) | |
273 | #define SBC_IDE_MDMA1_TA (0x15<<0) | |
274 | /* Timing parameters MDMA mode 2 */ | |
275 | #define SBC_IDE_MDMA2_TCSOE (0x04<<29) | |
276 | #define SBC_IDE_MDMA2_TOECS (0x01<<26) | |
277 | #define SBC_IDE_MDMA2_TWCS (0x01<<28) | |
278 | #define SBC_IDE_MDMA2_TCSH (0x04<<24) | |
279 | #define SBC_IDE_MDMA2_TCSOFF (0x04<<20) | |
280 | #define SBC_IDE_MDMA2_TWP (0x0D<<14) | |
281 | #define SBC_IDE_MDMA2_TCSW (0x04<<10) | |
282 | #define SBC_IDE_MDMA2_TPM (0x00<<6) | |
283 | #define SBC_IDE_MDMA2_TA (0x12<<0) | |
284 | ||
8f29e650 JC |
285 | #define SBC_IDE_TIMING(mode) \ |
286 | SBC_IDE_##mode##_TWCS | \ | |
287 | SBC_IDE_##mode##_TCSH | \ | |
288 | SBC_IDE_##mode##_TCSOFF | \ | |
289 | SBC_IDE_##mode##_TWP | \ | |
290 | SBC_IDE_##mode##_TCSW | \ | |
291 | SBC_IDE_##mode##_TPM | \ | |
292 | SBC_IDE_##mode##_TA |