[deliverable/linux.git] / include / asm-mips / mach-db1x00 / db1x00.h

/*
 * AMD Alchemy DBAu1x00 Reference Boards
 *
 * Copyright 2001, 2008 MontaVista Software Inc.
 * Author: MontaVista Software, Inc. <source@mvista.com>
 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 *
 */
#ifndef __ASM_DB1X00_H
#define __ASM_DB1X00_H

#include <asm/mach-au1x00/au1xxx_psc.h>

#ifdef CONFIG_MIPS_DB1550

#define DBDMA_AC97_TX_CHAN	DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN	DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN	DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN	DSCR_CMD0_PSC3_RX

#define SPI_PSC_BASE		PSC0_BASE_ADDR
#define AC97_PSC_BASE		PSC1_BASE_ADDR
#define SMBUS_PSC_BASE		PSC2_BASE_ADDR
#define I2S_PSC_BASE		PSC3_BASE_ADDR

#define BCSR_KSEG1_ADDR 	0xAF000000
#define NAND_PHYS_ADDR		0x20000000

#else
#define BCSR_KSEG1_ADDR 0xAE000000
#endif

/*
 * Overlay data structure of the DBAu1x00 board registers.
 * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
 */
typedef volatile struct
{
	/*00*/	unsigned short whoami;
	unsigned short reserved0;
	/*04*/	unsigned short status;
	unsigned short reserved1;
	/*08*/	unsigned short switches;
	unsigned short reserved2;
	/*0C*/	unsigned short resets;
	unsigned short reserved3;
	/*10*/	unsigned short pcmcia;
	unsigned short reserved4;
	/*14*/	unsigned short specific;
	unsigned short reserved5;
	/*18*/	unsigned short leds;
	unsigned short reserved6;
	/*1C*/	unsigned short swreset;
	unsigned short reserved7;

} BCSR;


/*
 * Register/mask bit definitions for the BCSRs
 */
#define BCSR_WHOAMI_DCID		0x000F
#define BCSR_WHOAMI_CPLD		0x00F0
#define BCSR_WHOAMI_BOARD		0x0F00

#define BCSR_STATUS_PC0VS		0x0003
#define BCSR_STATUS_PC1VS		0x000C
#define BCSR_STATUS_PC0FI		0x0010
#define BCSR_STATUS_PC1FI		0x0020
#define BCSR_STATUS_FLASHBUSY		0x0100
#define BCSR_STATUS_ROMBUSY		0x0400
#define BCSR_STATUS_SWAPBOOT		0x2000
#define BCSR_STATUS_FLASHDEN		0xC000

#define BCSR_SWITCHES_DIP		0x00FF
#define BCSR_SWITCHES_DIP_1		0x0080
#define BCSR_SWITCHES_DIP_2		0x0040
#define BCSR_SWITCHES_DIP_3		0x0020
#define BCSR_SWITCHES_DIP_4		0x0010
#define BCSR_SWITCHES_DIP_5		0x0008
#define BCSR_SWITCHES_DIP_6		0x0004
#define BCSR_SWITCHES_DIP_7		0x0002
#define BCSR_SWITCHES_DIP_8		0x0001
#define BCSR_SWITCHES_ROTARY		0x0F00

#define BCSR_RESETS_PHY0		0x0001
#define BCSR_RESETS_PHY1		0x0002
#define BCSR_RESETS_DC			0x0004
#define BCSR_RESETS_FIR_SEL		0x2000
#define BCSR_RESETS_IRDA_MODE_MASK	0xC000
#define BCSR_RESETS_IRDA_MODE_FULL	0x0000
#define BCSR_RESETS_IRDA_MODE_OFF	0x4000
#define BCSR_RESETS_IRDA_MODE_2_3	0x8000
#define BCSR_RESETS_IRDA_MODE_1_3	0xC000

#define BCSR_PCMCIA_PC0VPP		0x0003
#define BCSR_PCMCIA_PC0VCC		0x000C
#define BCSR_PCMCIA_PC0DRVEN		0x0010
#define BCSR_PCMCIA_PC0RST		0x0080
#define BCSR_PCMCIA_PC1VPP		0x0300
#define BCSR_PCMCIA_PC1VCC		0x0C00
#define BCSR_PCMCIA_PC1DRVEN		0x1000
#define BCSR_PCMCIA_PC1RST		0x8000

#define BCSR_BOARD_PCIM66EN		0x0001
#define BCSR_BOARD_SD0_PWR		0x0040
#define BCSR_BOARD_SD1_PWR		0x0080
#define BCSR_BOARD_PCIM33		0x0100
#define BCSR_BOARD_GPIO200RST		0x0400
#define BCSR_BOARD_PCICFG		0x1000
#define BCSR_BOARD_SD0_WP		0x4000
#define BCSR_BOARD_SD1_WP		0x8000

#define BCSR_LEDS_DECIMALS		0x0003
#define BCSR_LEDS_LED0			0x0100
#define BCSR_LEDS_LED1			0x0200
#define BCSR_LEDS_LED2			0x0400
#define BCSR_LEDS_LED3			0x0800

#define BCSR_SWRESET_RESET		0x0080

/* PCMCIA DBAu1x00 specific defines */
#define PCMCIA_MAX_SOCK  1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)

/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
	((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))

/*
 * SD controller macros
 */

/* Detect card. */
#define mmc_card_inserted(_n_, _res_) \
	do { \
		BCSR * const bcsr = (BCSR *)0xAE000000; \
		unsigned long mmc_wp, board_specific; \
		if ((_n_)) { \
			mmc_wp = BCSR_BOARD_SD1_WP; \
		} else { \
			mmc_wp = BCSR_BOARD_SD0_WP; \
		} \
		board_specific = au_readl((unsigned long)(&bcsr->specific)); \
		if (!(board_specific & mmc_wp)) {/* low means card present */ \
			*(int *)(_res_) = 1; \
		} else { \
			*(int *)(_res_) = 0; \
		} \
	} while (0)

/*
 * Apply power to card slot(s).
 */
#define mmc_power_on(_n_) \
	do { \
		BCSR * const bcsr = (BCSR *)0xAE000000; \
		unsigned long mmc_pwr, mmc_wp, board_specific; \
		if ((_n_)) { \
			mmc_pwr = BCSR_BOARD_SD1_PWR; \
			mmc_wp	= BCSR_BOARD_SD1_WP; \
		} else { \
			mmc_pwr = BCSR_BOARD_SD0_PWR; \
			mmc_wp	= BCSR_BOARD_SD0_WP; \
		} \
		board_specific = au_readl((unsigned long)(&bcsr->specific)); \
		if (!(board_specific & mmc_wp)) {/* low means card present */ \
			board_specific |= mmc_pwr; \
			au_writel(board_specific, (int)(&bcsr->specific)); \
			au_sync(); \
		} \
	} while (0)


/*
 * NAND defines
 *
 * Timing values as described in databook, * ns value stripped of the
 * lower 2 bits.
 * These defines are here rather than an Au1550 generic file because
 * the parts chosen on another board may be different and may require
 * different timings.
 */
#define NAND_T_H		(18 >> 2)
#define NAND_T_PUL		(30 >> 2)
#define NAND_T_SU		(30 >> 2)
#define NAND_T_WH		(30 >> 2)

/* Bitfield shift amounts */
#define NAND_T_H_SHIFT		0
#define NAND_T_PUL_SHIFT	4
#define NAND_T_SU_SHIFT		8
#define NAND_T_WH_SHIFT		12

#define NAND_TIMING	(((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
			 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
			 ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
			 ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
#define NAND_CS 	1

/* Should be done by YAMON */
#define NAND_STCFG	0x00400005 /* 8-bit NAND */
#define NAND_STTIME	0x00007774 /* valid for 396 MHz SD=2 only */
#define NAND_STADDR	0x12000FFF /* physical address 0x20000000 */

#endif /* __ASM_DB1X00_H */
Commit	Line	Data
1da177e4	1	/*
abd14cc0	2	* AMD Alchemy DBAu1x00 Reference Boards
1da177e4	3	*
abd14cc0 SS	4	* Copyright 2001, 2008 MontaVista Software Inc.
abd14cc0 SS	5	* Author: MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	6	* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
	7	*
	8	* ########################################################################
	9	*
	10	* This program is free software; you can distribute it and/or modify it
	11	* under the terms of the GNU General Public License (Version 2) as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	17	* for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, write to the Free Software Foundation, Inc.,
	21	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	22	*
	23	* ########################################################################
	24	*
42a3b4f2	25	*
1da177e4 LT	26	*/
	27	#ifndef __ASM_DB1X00_H
	28	#define __ASM_DB1X00_H
	29
9e39ffef	30	#include <asm/mach-au1x00/au1xxx_psc.h>
1da177e4 LT	31
1da177e4 LT	32	#ifdef CONFIG_MIPS_DB1550
f2c780c1	33
abd14cc0 SS	34	#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
	35	#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
	36	#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
	37	#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
f2c780c1	38
abd14cc0 SS	39	#define SPI_PSC_BASE PSC0_BASE_ADDR
	40	#define AC97_PSC_BASE PSC1_BASE_ADDR
	41	#define SMBUS_PSC_BASE PSC2_BASE_ADDR
	42	#define I2S_PSC_BASE PSC3_BASE_ADDR
f2c780c1	43
abd14cc0 SS	44	#define BCSR_KSEG1_ADDR 0xAF000000
abd14cc0 SS	45	#define NAND_PHYS_ADDR 0x20000000
f2c780c1	46
1da177e4 LT	47	#else
	48	#define BCSR_KSEG1_ADDR 0xAE000000
	49	#endif
	50
	51	/*
abd14cc0 SS	52	* Overlay data structure of the DBAu1x00 board registers.
abd14cc0 SS	53	* Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
1da177e4 LT	54	*/
	55	typedef volatile struct
	56	{
	57	/00/ unsigned short whoami;
	58	unsigned short reserved0;
	59	/04/ unsigned short status;
	60	unsigned short reserved1;
	61	/08/ unsigned short switches;
	62	unsigned short reserved2;
	63	/0C/ unsigned short resets;
	64	unsigned short reserved3;
	65	/10/ unsigned short pcmcia;
	66	unsigned short reserved4;
	67	/14/ unsigned short specific;
	68	unsigned short reserved5;
	69	/18/ unsigned short leds;
	70	unsigned short reserved6;
	71	/1C/ unsigned short swreset;
	72	unsigned short reserved7;
	73
	74	} BCSR;
	75
	76
	77	/*
	78	* Register/mask bit definitions for the BCSRs
	79	*/
	80	#define BCSR_WHOAMI_DCID 0x000F
	81	#define BCSR_WHOAMI_CPLD 0x00F0
	82	#define BCSR_WHOAMI_BOARD 0x0F00
	83
	84	#define BCSR_STATUS_PC0VS 0x0003
	85	#define BCSR_STATUS_PC1VS 0x000C
	86	#define BCSR_STATUS_PC0FI 0x0010
	87	#define BCSR_STATUS_PC1FI 0x0020
	88	#define BCSR_STATUS_FLASHBUSY 0x0100
	89	#define BCSR_STATUS_ROMBUSY 0x0400
	90	#define BCSR_STATUS_SWAPBOOT 0x2000
	91	#define BCSR_STATUS_FLASHDEN 0xC000
	92
	93	#define BCSR_SWITCHES_DIP 0x00FF
	94	#define BCSR_SWITCHES_DIP_1 0x0080
	95	#define BCSR_SWITCHES_DIP_2 0x0040
	96	#define BCSR_SWITCHES_DIP_3 0x0020
	97	#define BCSR_SWITCHES_DIP_4 0x0010
	98	#define BCSR_SWITCHES_DIP_5 0x0008
	99	#define BCSR_SWITCHES_DIP_6 0x0004
	100	#define BCSR_SWITCHES_DIP_7 0x0002
	101	#define BCSR_SWITCHES_DIP_8 0x0001
	102	#define BCSR_SWITCHES_ROTARY 0x0F00
	103
	104	#define BCSR_RESETS_PHY0 0x0001
	105	#define BCSR_RESETS_PHY1 0x0002
	106	#define BCSR_RESETS_DC 0x0004
	107	#define BCSR_RESETS_FIR_SEL 0x2000
	108	#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
	109	#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
	110	#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
	111	#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
	112	#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
	113
	114	#define BCSR_PCMCIA_PC0VPP 0x0003
	115	#define BCSR_PCMCIA_PC0VCC 0x000C
	116	#define BCSR_PCMCIA_PC0DRVEN 0x0010
	117	#define BCSR_PCMCIA_PC0RST 0x0080
118	#define BCSR_PCMCIA_PC1VPP 0x0300
119	#define BCSR_PCMCIA_PC1VCC 0x0C00
120	#define BCSR_PCMCIA_PC1DRVEN 0x1000
121	#define BCSR_PCMCIA_PC1RST 0x8000
122
123	#define BCSR_BOARD_PCIM66EN 0x0001
124	#define BCSR_BOARD_SD0_PWR 0x0040
125	#define BCSR_BOARD_SD1_PWR 0x0080
126	#define BCSR_BOARD_PCIM33 0x0100
127	#define BCSR_BOARD_GPIO200RST 0x0400
128	#define BCSR_BOARD_PCICFG 0x1000
129	#define BCSR_BOARD_SD0_WP 0x4000
130	#define BCSR_BOARD_SD1_WP 0x8000
131
132	#define BCSR_LEDS_DECIMALS 0x0003
133	#define BCSR_LEDS_LED0 0x0100
134	#define BCSR_LEDS_LED1 0x0200
135	#define BCSR_LEDS_LED2 0x0400
136	#define BCSR_LEDS_LED3 0x0800
137
138	#define BCSR_SWRESET_RESET 0x0080
139
abd14cc0 SS	140	/* PCMCIA DBAu1x00 specific defines */
	141	#define PCMCIA_MAX_SOCK 1
	142	#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
1da177e4 LT	143
	144	/* VPP/VCC */
	145	#define SET_VCC_VPP(VCC, VPP, SLOT)\
abd14cc0	146	((((VCC) << 2) \| ((VPP) << 0)) << ((SLOT) * 8))
1da177e4	147
1da177e4	148	/*
abd14cc0	149	* SD controller macros
1da177e4	150	*/
abd14cc0 SS	151
abd14cc0 SS	152	/* Detect card. */
1da177e4 LT	153	#define mmc_card_inserted(_n_, _res_) \
	154	do { \
	155	BCSR * const bcsr = (BCSR *)0xAE000000; \
	156	unsigned long mmc_wp, board_specific; \
	157	if ((_n_)) { \
	158	mmc_wp = BCSR_BOARD_SD1_WP; \
	159	} else { \
	160	mmc_wp = BCSR_BOARD_SD0_WP; \
	161	} \
	162	board_specific = au_readl((unsigned long)(&bcsr->specific)); \
	163	if (!(board_specific & mmc_wp)) {/* low means card present */ \
	164	(int )(_res_) = 1; \
	165	} else { \
	166	(int )(_res_) = 0; \
	167	} \
	168	} while (0)
	169
	170	/*
	171	* Apply power to card slot(s).
	172	*/
	173	#define mmc_power_on(_n_) \
	174	do { \
	175	BCSR * const bcsr = (BCSR *)0xAE000000; \
	176	unsigned long mmc_pwr, mmc_wp, board_specific; \
	177	if ((_n_)) { \
	178	mmc_pwr = BCSR_BOARD_SD1_PWR; \
abd14cc0	179	mmc_wp = BCSR_BOARD_SD1_WP; \
1da177e4 LT	180	} else { \
1da177e4 LT	181	mmc_pwr = BCSR_BOARD_SD0_PWR; \
abd14cc0	182	mmc_wp = BCSR_BOARD_SD0_WP; \
1da177e4 LT	183	} \
	184	board_specific = au_readl((unsigned long)(&bcsr->specific)); \
	185	if (!(board_specific & mmc_wp)) {/* low means card present */ \
	186	board_specific \|= mmc_pwr; \
	187	au_writel(board_specific, (int)(&bcsr->specific)); \
	188	au_sync(); \
	189	} \
	190	} while (0)
	191
	192
abd14cc0 SS	193	/*
	194	* NAND defines
	195	*
	196	* Timing values as described in databook, * ns value stripped of the
1da177e4	197	* lower 2 bits.
abd14cc0	198	* These defines are here rather than an Au1550 generic file because
1da177e4 LT	199	* the parts chosen on another board may be different and may require
	200	* different timings.
	201	*/
abd14cc0 SS	202	#define NAND_T_H (18 >> 2)
	203	#define NAND_T_PUL (30 >> 2)
	204	#define NAND_T_SU (30 >> 2)
	205	#define NAND_T_WH (30 >> 2)
1da177e4 LT	206
	207	/* Bitfield shift amounts */
	208	#define NAND_T_H_SHIFT 0
	209	#define NAND_T_PUL_SHIFT 4
	210	#define NAND_T_SU_SHIFT 8
	211	#define NAND_T_WH_SHIFT 12
	212
abd14cc0 SS	213	#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) \| \
	214	((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) \| \
	215	((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) \| \
	216	((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
	217	#define NAND_CS 1
bdc3c3c7	218
abd14cc0 SS	219	/* Should be done by YAMON */
	220	#define NAND_STCFG 0x00400005 /* 8-bit NAND */
	221	#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
	222	#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
1da177e4 LT	223
1da177e4 LT	224	#endif /* __ASM_DB1X00_H */