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1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2003 by Ralf Baechle | |
7 | */ | |
8 | #ifndef __ASM_PREFETCH_H | |
9 | #define __ASM_PREFETCH_H | |
10 | ||
11 | #include <linux/config.h> | |
12 | ||
13 | /* | |
14 | * R5000 and RM5200 implements pref and prefx instructions but they're nops, so | |
15 | * rather than wasting time we pretend these processors don't support | |
16 | * prefetching at all. | |
17 | * | |
18 | * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained, | |
19 | * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore. | |
20 | * | |
21 | * Hell (and the book on my shelf I can't open ...) know what the R8000 does. | |
22 | * | |
23 | * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements | |
24 | * Pref_PrepareForStore also. | |
25 | * | |
26 | * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's | |
27 | * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in | |
28 | * current versions due to erratum G105. | |
29 | * | |
30 | * VR7701 only implements the Load prefetch. | |
31 | * | |
32 | * Finally MIPS32 and MIPS64 implement all of the following hints. | |
33 | */ | |
34 | ||
35 | #define Pref_Load 0 | |
36 | #define Pref_Store 1 | |
37 | /* 2 and 3 are reserved */ | |
38 | #define Pref_LoadStreamed 4 | |
39 | #define Pref_StoreStreamed 5 | |
40 | #define Pref_LoadRetained 6 | |
41 | #define Pref_StoreRetained 7 | |
42 | /* 8 ... 24 are reserved */ | |
43 | #define Pref_WriteBackInvalidate 25 | |
44 | #define Pref_PrepareForStore 30 | |
45 | ||
46 | #ifdef __ASSEMBLY__ | |
47 | ||
48 | .macro __pref hint addr | |
49 | #ifdef CONFIG_CPU_HAS_PREFETCH | |
50 | pref \hint, \addr | |
51 | #endif | |
52 | .endm | |
53 | ||
54 | .macro pref_load addr | |
55 | __pref Pref_Load, \addr | |
56 | .endm | |
57 | ||
58 | .macro pref_store addr | |
59 | __pref Pref_Store, \addr | |
60 | .endm | |
61 | ||
62 | .macro pref_load_streamed addr | |
63 | __pref Pref_LoadStreamed, \addr | |
64 | .endm | |
65 | ||
66 | .macro pref_store_streamed addr | |
67 | __pref Pref_StoreStreamed, \addr | |
68 | .endm | |
69 | ||
70 | .macro pref_load_retained addr | |
71 | __pref Pref_LoadRetained, \addr | |
72 | .endm | |
73 | ||
74 | .macro pref_store_retained addr | |
75 | __pref Pref_StoreRetained, \addr | |
76 | .endm | |
77 | ||
78 | .macro pref_wback_inv addr | |
79 | __pref Pref_WriteBackInvalidate, \addr | |
80 | .endm | |
81 | ||
82 | .macro pref_prepare_for_store addr | |
83 | __pref Pref_PrepareForStore, \addr | |
84 | .endm | |
85 | ||
86 | #endif | |
87 | ||
88 | #endif /* __ASM_PREFETCH_H */ |