[deliverable/linux.git] / include / asm-mips / system.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
 * Copyright (C) 1996 by Paul M. Antoine
 * Copyright (C) 1999 Silicon Graphics
 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.
 */
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H

#include <linux/types.h>
#include <linux/irqflags.h>

#include <asm/addrspace.h>
#include <asm/barrier.h>
#include <asm/cpu-features.h>
#include <asm/dsp.h>
#include <asm/ptrace.h>
#include <asm/war.h>


/*
 * switch_to(n) should switch tasks to task nr n, first
 * checking that n isn't the current task, in which case it does nothing.
 */
extern asmlinkage void *resume(void *last, void *next, void *next_ti);

struct task_struct;

#ifdef CONFIG_MIPS_MT_FPAFF

/*
 * Handle the scheduler resume end of FPU affinity management.  We do this
 * inline to try to keep the overhead down. If we have been forced to run on
 * a "CPU" with an FPU because of a previous high level of FP computation,
 * but did not actually use the FPU during the most recent time-slice (CU1
 * isn't set), we undo the restriction on cpus_allowed.
 *
 * We're not calling set_cpus_allowed() here, because we have no need to
 * force prompt migration - we're already switching the current CPU to a
 * different thread.
 */

#define switch_to(prev,next,last)					\
do {									\
	if (cpu_has_fpu &&						\
	    (prev->thread.mflags & MF_FPUBOUND) &&			\
	     (!(KSTK_STATUS(prev) & ST0_CU1))) {			\
		prev->thread.mflags &= ~MF_FPUBOUND;			\
		prev->cpus_allowed = prev->thread.user_cpus_allowed;	\
	}								\
	if (cpu_has_dsp)						\
		__save_dsp(prev);					\
	next->thread.emulated_fp = 0;					\
	(last) = resume(prev, next, next->thread_info);			\
	if (cpu_has_dsp)						\
		__restore_dsp(current);					\
} while(0)

#else
#define switch_to(prev,next,last)					\
do {									\
	if (cpu_has_dsp)						\
		__save_dsp(prev);					\
	(last) = resume(prev, next, task_thread_info(next));		\
	if (cpu_has_dsp)						\
		__restore_dsp(current);					\
} while(0)
#endif

/*
 * On SMP systems, when the scheduler does migration-cost autodetection,
 * it needs a way to flush as much of the CPU's caches as possible.
 *
 * TODO: fill this in!
 */
static inline void sched_cacheflush(void)
{
}

static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
{
	__u32 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	ll	%0, %3			# xchg_u32	\n"
		"	.set	mips0					\n"
		"	move	%2, %z4					\n"
		"	.set	mips3					\n"
		"	sc	%2, %1					\n"
		"	beqzl	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else if (cpu_has_llsc) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	ll	%0, %3			# xchg_u32	\n"
		"	.set	mips0					\n"
		"	move	%2, %z4					\n"
		"	.set	mips3					\n"
		"	sc	%2, %1					\n"
		"	beqz	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else {
		unsigned long flags;

		local_irq_save(flags);
		retval = *m;
		*m = val;
		local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_mb();

	return retval;
}

#ifdef CONFIG_64BIT
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
{
	__u64 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	lld	%0, %3			# xchg_u64	\n"
		"	move	%2, %z4					\n"
		"	scd	%2, %1					\n"
		"	beqzl	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else if (cpu_has_llsc) {
		unsigned long dummy;

		__asm__ __volatile__(
		"	.set	mips3					\n"
		"1:	lld	%0, %3			# xchg_u64	\n"
		"	move	%2, %z4					\n"
		"	scd	%2, %1					\n"
		"	beqz	%2, 1b					\n"
		"	.set	mips0					\n"
		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
		: "R" (*m), "Jr" (val)
		: "memory");
	} else {
		unsigned long flags;

		local_irq_save(flags);
		retval = *m;
		*m = val;
		local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_mb();

	return retval;
}
#else
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
#endif

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid xchg().  */
extern void __xchg_called_with_bad_pointer(void);

static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
	switch (size) {
	case 4:
		return __xchg_u32(ptr, x);
	case 8:
		return __xchg_u64(ptr, x);
	}
	__xchg_called_with_bad_pointer();
	return x;
}

#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
#define tas(ptr) (xchg((ptr),1))

#define __HAVE_ARCH_CMPXCHG 1

static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
	unsigned long new)
{
	__u32 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		__asm__ __volatile__(
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
		"	bne	%0, %z3, 2f				\n"
		"	.set	mips0					\n"
		"	move	$1, %z4					\n"
		"	.set	mips3					\n"
		"	sc	$1, %1					\n"
		"	beqzl	$1, 1b					\n"
		"2:							\n"
		"	.set	pop					\n"
		: "=&r" (retval), "=R" (*m)
		: "R" (*m), "Jr" (old), "Jr" (new)
		: "memory");
	} else if (cpu_has_llsc) {
		__asm__ __volatile__(
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
		"	bne	%0, %z3, 2f				\n"
		"	.set	mips0					\n"
		"	move	$1, %z4					\n"
		"	.set	mips3					\n"
		"	sc	$1, %1					\n"
		"	beqz	$1, 1b					\n"
		"2:							\n"
		"	.set	pop					\n"
		: "=&r" (retval), "=R" (*m)
		: "R" (*m), "Jr" (old), "Jr" (new)
		: "memory");
	} else {
		unsigned long flags;

		local_irq_save(flags);
		retval = *m;
		if (retval == old)
			*m = new;
		local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_mb();

	return retval;
}

#ifdef CONFIG_64BIT
static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
	unsigned long new)
{
	__u64 retval;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		__asm__ __volatile__(
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
		"	bne	%0, %z3, 2f				\n"
		"	move	$1, %z4					\n"
		"	scd	$1, %1					\n"
		"	beqzl	$1, 1b					\n"
		"2:							\n"
		"	.set	pop					\n"
		: "=&r" (retval), "=R" (*m)
		: "R" (*m), "Jr" (old), "Jr" (new)
		: "memory");
	} else if (cpu_has_llsc) {
		__asm__ __volatile__(
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	mips3					\n"
		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
		"	bne	%0, %z3, 2f				\n"
		"	move	$1, %z4					\n"
		"	scd	$1, %1					\n"
		"	beqz	$1, 1b					\n"
		"2:							\n"
		"	.set	pop					\n"
		: "=&r" (retval), "=R" (*m)
		: "R" (*m), "Jr" (old), "Jr" (new)
		: "memory");
	} else {
		unsigned long flags;

		local_irq_save(flags);
		retval = *m;
		if (retval == old)
			*m = new;
		local_irq_restore(flags);	/* implies memory barrier  */
	}

	smp_mb();

	return retval;
}
#else
extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
	volatile int * m, unsigned long old, unsigned long new);
#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
#endif

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid cmpxchg().  */
extern void __cmpxchg_called_with_bad_pointer(void);

static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
	unsigned long new, int size)
{
	switch (size) {
	case 4:
		return __cmpxchg_u32(ptr, old, new);
	case 8:
		return __cmpxchg_u64(ptr, old, new);
	}
	__cmpxchg_called_with_bad_pointer();
	return old;
}

#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))

extern void set_handler (unsigned long offset, void *addr, unsigned long len);
extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
extern void *set_vi_handler (int n, void *addr);
extern void *set_except_vector(int n, void *addr);
extern unsigned long ebase;
extern void per_cpu_trap_init(void);

extern NORET_TYPE void die(const char *, struct pt_regs *);

static inline void die_if_kernel(const char *str, struct pt_regs *regs)
{
	if (unlikely(!user_mode(regs)))
		die(str, regs);
}

extern int stop_a_enabled;

/*
 * See include/asm-ia64/system.h; prevents deadlock on SMP
 * systems.
 */
#define __ARCH_WANT_UNLOCKED_CTXSW

#define arch_align_stack(x) (x)

#endif /* _ASM_SYSTEM_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
0004a9df	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
1da177e4 LT	7	* Copyright (C) 1996 by Paul M. Antoine
	8	* Copyright (C) 1999 Silicon Graphics
	9	* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	*/
	12	#ifndef _ASM_SYSTEM_H
	13	#define _ASM_SYSTEM_H
	14
1da177e4	15	#include <linux/types.h>
192ef366	16	#include <linux/irqflags.h>
1da177e4 LT	17
1da177e4 LT	18	#include <asm/addrspace.h>
0004a9df	19	#include <asm/barrier.h>
1da177e4	20	#include <asm/cpu-features.h>
e50c0a8f	21	#include <asm/dsp.h>
1da177e4 LT	22	#include <asm/ptrace.h>
1da177e4 LT	23	#include <asm/war.h>
1da177e4	24
1da177e4	25
1da177e4 LT	26	/*
	27	* switch_to(n) should switch tasks to task nr n, first
	28	* checking that n isn't the current task, in which case it does nothing.
	29	*/
	30	extern asmlinkage void resume(void last, void next, void next_ti);
	31
	32	struct task_struct;
	33
f088fc84 RB	34	#ifdef CONFIG_MIPS_MT_FPAFF
	35
	36	/*
	37	* Handle the scheduler resume end of FPU affinity management. We do this
	38	* inline to try to keep the overhead down. If we have been forced to run on
	39	* a "CPU" with an FPU because of a previous high level of FP computation,
	40	* but did not actually use the FPU during the most recent time-slice (CU1
	41	* isn't set), we undo the restriction on cpus_allowed.
	42	*
	43	* We're not calling set_cpus_allowed() here, because we have no need to
	44	* force prompt migration - we're already switching the current CPU to a
	45	* different thread.
	46	*/
	47
	48	#define switch_to(prev,next,last) \
	49	do { \
	50	if (cpu_has_fpu && \
	51	(prev->thread.mflags & MF_FPUBOUND) && \
	52	(!(KSTK_STATUS(prev) & ST0_CU1))) { \
	53	prev->thread.mflags &= ~MF_FPUBOUND; \
	54	prev->cpus_allowed = prev->thread.user_cpus_allowed; \
	55	} \
	56	if (cpu_has_dsp) \
	57	__save_dsp(prev); \
	58	next->thread.emulated_fp = 0; \
	59	(last) = resume(prev, next, next->thread_info); \
	60	if (cpu_has_dsp) \
	61	__restore_dsp(current); \
	62	} while(0)
	63
	64	#else
e50c0a8f RB	65	#define switch_to(prev,next,last) \
	66	do { \
	67	if (cpu_has_dsp) \
	68	__save_dsp(prev); \
40bc9c67	69	(last) = resume(prev, next, task_thread_info(next)); \
e50c0a8f RB	70	if (cpu_has_dsp) \
e50c0a8f RB	71	__restore_dsp(current); \
1da177e4	72	} while(0)
f088fc84	73	#endif
1da177e4	74
4dc7a0bb IM	75	/*
	76	* On SMP systems, when the scheduler does migration-cost autodetection,
	77	* it needs a way to flush as much of the CPU's caches as possible.
	78	*
	79	* TODO: fill this in!
	80	*/
	81	static inline void sched_cacheflush(void)
	82	{
	83	}
	84
1da177e4 LT	85	static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
	86	{
	87	__u32 retval;
	88
	89	if (cpu_has_llsc && R10000_LLSC_WAR) {
	90	unsigned long dummy;
	91
	92	__asm__ __volatile__(
c4559f67	93	" .set mips3 \n"
1da177e4	94	"1: ll %0, %3 # xchg_u32 \n"
7222424e	95	" .set mips0 \n"
1da177e4	96	" move %2, %z4 \n"
7222424e	97	" .set mips3 \n"
1da177e4 LT	98	" sc %2, %1 \n"
1da177e4 LT	99	" beqzl %2, 1b \n"
aac8aa77	100	" .set mips0 \n"
1da177e4 LT	101	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	102	: "R" (*m), "Jr" (val)
	103	: "memory");
	104	} else if (cpu_has_llsc) {
	105	unsigned long dummy;
	106
	107	__asm__ __volatile__(
c4559f67	108	" .set mips3 \n"
1da177e4	109	"1: ll %0, %3 # xchg_u32 \n"
7222424e	110	" .set mips0 \n"
1da177e4	111	" move %2, %z4 \n"
7222424e	112	" .set mips3 \n"
1da177e4 LT	113	" sc %2, %1 \n"
1da177e4 LT	114	" beqz %2, 1b \n"
aac8aa77	115	" .set mips0 \n"
1da177e4 LT	116	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	117	: "R" (*m), "Jr" (val)
	118	: "memory");
	119	} else {
	120	unsigned long flags;
	121
	122	local_irq_save(flags);
	123	retval = *m;
	124	*m = val;
	125	local_irq_restore(flags); /* implies memory barrier */
	126	}
	127
0004a9df RB	128	smp_mb();
0004a9df RB	129
1da177e4 LT	130	return retval;
	131	}
	132
875d43e7	133	#ifdef CONFIG_64BIT
1da177e4 LT	134	static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
	135	{
	136	__u64 retval;
	137
	138	if (cpu_has_llsc && R10000_LLSC_WAR) {
	139	unsigned long dummy;
	140
	141	__asm__ __volatile__(
aac8aa77	142	" .set mips3 \n"
1da177e4 LT	143	"1: lld %0, %3 # xchg_u64 \n"
	144	" move %2, %z4 \n"
	145	" scd %2, %1 \n"
	146	" beqzl %2, 1b \n"
aac8aa77	147	" .set mips0 \n"
1da177e4 LT	148	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	149	: "R" (*m), "Jr" (val)
	150	: "memory");
	151	} else if (cpu_has_llsc) {
	152	unsigned long dummy;
	153
	154	__asm__ __volatile__(
aac8aa77	155	" .set mips3 \n"
1da177e4 LT	156	"1: lld %0, %3 # xchg_u64 \n"
	157	" move %2, %z4 \n"
	158	" scd %2, %1 \n"
	159	" beqz %2, 1b \n"
aac8aa77	160	" .set mips0 \n"
1da177e4 LT	161	: "=&r" (retval), "=m" (*m), "=&r" (dummy)
	162	: "R" (*m), "Jr" (val)
	163	: "memory");
	164	} else {
	165	unsigned long flags;
	166
	167	local_irq_save(flags);
	168	retval = *m;
	169	*m = val;
	170	local_irq_restore(flags); /* implies memory barrier */
	171	}
	172
0004a9df RB	173	smp_mb();
0004a9df RB	174
1da177e4 LT	175	return retval;
	176	}
	177	#else
	178	extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
	179	#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
	180	#endif
	181
	182	/* This function doesn't exist, so you'll get a linker error
	183	if something tries to do an invalid xchg(). */
	184	extern void __xchg_called_with_bad_pointer(void);
	185
	186	static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
	187	{
	188	switch (size) {
0cea043b RB	189	case 4:
	190	return __xchg_u32(ptr, x);
	191	case 8:
	192	return __xchg_u64(ptr, x);
1da177e4 LT	193	}
	194	__xchg_called_with_bad_pointer();
	195	return x;
	196	}
	197
	198	#define xchg(ptr,x) ((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
	199	#define tas(ptr) (xchg((ptr),1))
	200
	201	#define __HAVE_ARCH_CMPXCHG 1
	202
	203	static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
	204	unsigned long new)
	205	{
	206	__u32 retval;
	207
	208	if (cpu_has_llsc && R10000_LLSC_WAR) {
	209	__asm__ __volatile__(
aac8aa77	210	" .set push \n"
1da177e4	211	" .set noat \n"
c4559f67	212	" .set mips3 \n"
1da177e4 LT	213	"1: ll %0, %2 # __cmpxchg_u32 \n"
1da177e4 LT	214	" bne %0, %z3, 2f \n"
f99d3023	215	" .set mips0 \n"
1da177e4	216	" move $1, %z4 \n"
f99d3023	217	" .set mips3 \n"
1da177e4 LT	218	" sc $1, %1 \n"
1da177e4 LT	219	" beqzl $1, 1b \n"
1da177e4	220	"2: \n"
aac8aa77	221	" .set pop \n"
3e6cb2d3	222	: "=&r" (retval), "=R" (*m)
1da177e4 LT	223	: "R" (*m), "Jr" (old), "Jr" (new)
	224	: "memory");
	225	} else if (cpu_has_llsc) {
	226	__asm__ __volatile__(
aac8aa77	227	" .set push \n"
1da177e4	228	" .set noat \n"
c4559f67	229	" .set mips3 \n"
1da177e4 LT	230	"1: ll %0, %2 # __cmpxchg_u32 \n"
1da177e4 LT	231	" bne %0, %z3, 2f \n"
f99d3023	232	" .set mips0 \n"
1da177e4	233	" move $1, %z4 \n"
f99d3023	234	" .set mips3 \n"
1da177e4 LT	235	" sc $1, %1 \n"
1da177e4 LT	236	" beqz $1, 1b \n"
1da177e4	237	"2: \n"
aac8aa77	238	" .set pop \n"
3e6cb2d3	239	: "=&r" (retval), "=R" (*m)
1da177e4 LT	240	: "R" (*m), "Jr" (old), "Jr" (new)
	241	: "memory");
	242	} else {
	243	unsigned long flags;
	244
	245	local_irq_save(flags);
	246	retval = *m;
	247	if (retval == old)
	248	*m = new;
	249	local_irq_restore(flags); /* implies memory barrier */
	250	}
	251
0004a9df RB	252	smp_mb();
0004a9df RB	253
1da177e4 LT	254	return retval;
	255	}
	256
875d43e7	257	#ifdef CONFIG_64BIT
1da177e4 LT	258	static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
	259	unsigned long new)
	260	{
	261	__u64 retval;
	262
904880e7	263	if (cpu_has_llsc && R10000_LLSC_WAR) {
1da177e4	264	__asm__ __volatile__(
aac8aa77	265	" .set push \n"
1da177e4	266	" .set noat \n"
aac8aa77	267	" .set mips3 \n"
1da177e4 LT	268	"1: lld %0, %2 # __cmpxchg_u64 \n"
	269	" bne %0, %z3, 2f \n"
	270	" move $1, %z4 \n"
	271	" scd $1, %1 \n"
	272	" beqzl $1, 1b \n"
1da177e4	273	"2: \n"
aac8aa77	274	" .set pop \n"
3e6cb2d3	275	: "=&r" (retval), "=R" (*m)
1da177e4 LT	276	: "R" (*m), "Jr" (old), "Jr" (new)
	277	: "memory");
	278	} else if (cpu_has_llsc) {
	279	__asm__ __volatile__(
aac8aa77	280	" .set push \n"
1da177e4	281	" .set noat \n"
c4559f67	282	" .set mips3 \n"
1da177e4 LT	283	"1: lld %0, %2 # __cmpxchg_u64 \n"
	284	" bne %0, %z3, 2f \n"
	285	" move $1, %z4 \n"
	286	" scd $1, %1 \n"
	287	" beqz $1, 1b \n"
1da177e4	288	"2: \n"
aac8aa77	289	" .set pop \n"
3e6cb2d3	290	: "=&r" (retval), "=R" (*m)
1da177e4 LT	291	: "R" (*m), "Jr" (old), "Jr" (new)
	292	: "memory");
	293	} else {
	294	unsigned long flags;
	295
	296	local_irq_save(flags);
	297	retval = *m;
	298	if (retval == old)
	299	*m = new;
	300	local_irq_restore(flags); /* implies memory barrier */
	301	}
	302
0004a9df RB	303	smp_mb();
0004a9df RB	304
1da177e4 LT	305	return retval;
	306	}
	307	#else
	308	extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
	309	volatile int * m, unsigned long old, unsigned long new);
	310	#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
	311	#endif
	312
	313	/* This function doesn't exist, so you'll get a linker error
	314	if something tries to do an invalid cmpxchg(). */
	315	extern void __cmpxchg_called_with_bad_pointer(void);
	316
	317	static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
	318	unsigned long new, int size)
	319	{
	320	switch (size) {
	321	case 4:
	322	return __cmpxchg_u32(ptr, old, new);
	323	case 8:
	324	return __cmpxchg_u64(ptr, old, new);
	325	}
	326	__cmpxchg_called_with_bad_pointer();
	327	return old;
	328	}
	329
	330	#define cmpxchg(ptr,old,new) ((__typeof__((ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof((ptr))))
	331
e01402b1 RB	332	extern void set_handler (unsigned long offset, void *addr, unsigned long len);
	333	extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
	334	extern void set_vi_handler (int n, void addr);
1da177e4	335	extern void set_except_vector(int n, void addr);
91b05e67	336	extern unsigned long ebase;
1da177e4 LT	337	extern void per_cpu_trap_init(void);
1da177e4 LT	338
178086c8 RB	339	extern NORET_TYPE void die(const char , struct pt_regs );
	340
	341	static inline void die_if_kernel(const char str, struct pt_regs regs)
	342	{
	343	if (unlikely(!user_mode(regs)))
	344	die(str, regs);
	345	}
1da177e4 LT	346
	347	extern int stop_a_enabled;
	348
	349	/*
4866cde0	350	* See include/asm-ia64/system.h; prevents deadlock on SMP
1da177e4 LT	351	* systems.
1da177e4 LT	352	*/
4866cde0	353	#define __ARCH_WANT_UNLOCKED_CTXSW
1da177e4 LT	354
	355	#define arch_align_stack(x) (x)
	356
	357	#endif /* _ASM_SYSTEM_H */