Commit | Line | Data |
---|---|---|
b920de1b DH |
1 | /* MN10300 on-board DMA controller registers |
2 | * | |
3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public Licence | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the Licence, or (at your option) any later version. | |
10 | */ | |
11 | #ifndef _ASM_DMACTL_REGS_H | |
12 | #define _ASM_DMACTL_REGS_H | |
13 | ||
14 | #include <asm/cpu-regs.h> | |
15 | ||
16 | #ifdef __KERNEL__ | |
17 | ||
18 | /* DMA registers */ | |
19 | #define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */ | |
20 | #define DMxCTR_BG 0x0000001f /* transfer request source */ | |
21 | #define DMxCTR_BG_SOFT 0x00000000 /* - software source */ | |
22 | #define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */ | |
23 | #define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */ | |
24 | #define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */ | |
25 | #define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */ | |
26 | #define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */ | |
27 | #define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */ | |
28 | #define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */ | |
29 | #define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */ | |
30 | #define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */ | |
31 | #define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */ | |
32 | #define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */ | |
33 | #define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */ | |
34 | #define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */ | |
35 | #define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */ | |
36 | #define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */ | |
37 | #define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */ | |
38 | #define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */ | |
39 | #define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */ | |
40 | #define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */ | |
41 | #define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */ | |
42 | #define DMxCTR_SAM_INCR 0x00000000 /* - increment */ | |
43 | #define DMxCTR_SAM_DECR 0x00000020 /* - decrement */ | |
44 | #define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */ | |
45 | #define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */ | |
46 | #define DMxCTR_DAM_INCR 0x00000000 /* - increment */ | |
47 | #define DMxCTR_DAM_DECR 0x00000100 /* - decrement */ | |
48 | #define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */ | |
49 | #define DMxCTR_TM 0x00001800 /* DMA transfer mode */ | |
50 | #define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */ | |
51 | #define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */ | |
52 | #define DMxCTR_UT 0x00006000 /* DMA transfer unit */ | |
53 | #define DMxCTR_UT_1 0x00000000 /* - 1 byte */ | |
54 | #define DMxCTR_UT_2 0x00002000 /* - 2 byte */ | |
55 | #define DMxCTR_UT_4 0x00004000 /* - 4 byte */ | |
56 | #define DMxCTR_UT_16 0x00006000 /* - 16 byte */ | |
57 | #define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */ | |
58 | #define DMxCTR_RQM 0x00060000 /* external request input source mode */ | |
59 | #define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */ | |
60 | #define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */ | |
61 | #define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */ | |
62 | #define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */ | |
63 | #define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */ | |
64 | #define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */ | |
65 | ||
66 | #define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */ | |
67 | ||
68 | #define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */ | |
69 | ||
70 | #define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */ | |
71 | #define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */ | |
72 | ||
73 | #define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent | |
74 | * size reg */ | |
75 | #define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */ | |
76 | ||
77 | #define DM0IRQ 16 /* DMA channel 0 complete IRQ */ | |
78 | #define DM1IRQ 17 /* DMA channel 1 complete IRQ */ | |
79 | #define DM2IRQ 18 /* DMA channel 2 complete IRQ */ | |
80 | #define DM3IRQ 19 /* DMA channel 3 complete IRQ */ | |
81 | ||
82 | #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */ | |
83 | #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */ | |
84 | #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */ | |
85 | #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */ | |
86 | ||
87 | #ifndef __ASSEMBLY__ | |
88 | ||
89 | struct mn10300_dmactl_regs { | |
90 | u32 ctr; | |
91 | const void *src; | |
92 | void *dst; | |
93 | u32 siz; | |
94 | u32 cyc; | |
95 | } __attribute__((aligned(0x100))); | |
96 | ||
97 | #endif /* __ASSEMBLY__ */ | |
98 | ||
99 | #endif /* __KERNEL__ */ | |
100 | ||
101 | #endif /* _ASM_DMACTL_REGS_H */ |