[deliverable/linux.git] / include / asm-parisc / atomic.h

/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
 * Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
 */

#ifndef _ASM_PARISC_ATOMIC_H_
#define _ASM_PARISC_ATOMIC_H_

#include <linux/types.h>
#include <asm/system.h>

/*
 * Atomic operations that C can't guarantee us.  Useful for
 * resource counting etc..
 *
 * And probably incredibly slow on parisc.  OTOH, we don't
 * have to write any serious assembly.   prumpf
 */

#ifdef CONFIG_SMP
#include <asm/spinlock.h>
#include <asm/cache.h>		/* we use L1_CACHE_BYTES */

/* Use an array of spinlocks for our atomic_ts.
 * Hash function to index into a different SPINLOCK.
 * Since "a" is usually an address, use one spinlock per cacheline.
 */
#  define ATOMIC_HASH_SIZE 4
#  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))

extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;

/* Can't use raw_spin_lock_irq because of #include problems, so
 * this is the substitute */
#define _atomic_spin_lock_irqsave(l,f) do {	\
	raw_spinlock_t *s = ATOMIC_HASH(l);		\
	local_irq_save(f);			\
	__raw_spin_lock(s);			\
} while(0)

#define _atomic_spin_unlock_irqrestore(l,f) do {	\
	raw_spinlock_t *s = ATOMIC_HASH(l);			\
	__raw_spin_unlock(s);				\
	local_irq_restore(f);				\
} while(0)


#else
#  define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
#  define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
#endif

/* This should get optimized out since it's never called.
** Or get a link error if xchg is used "wrong".
*/
extern void __xchg_called_with_bad_pointer(void);


/* __xchg32/64 defined in arch/parisc/lib/bitops.c */
extern unsigned long __xchg8(char, char *);
extern unsigned long __xchg32(int, int *);
#ifdef CONFIG_64BIT
extern unsigned long __xchg64(unsigned long, unsigned long *);
#endif

/* optimizer better get rid of switch since size is a constant */
static __inline__ unsigned long
__xchg(unsigned long x, __volatile__ void * ptr, int size)
{
	switch(size) {
#ifdef CONFIG_64BIT
	case 8: return __xchg64(x,(unsigned long *) ptr);
#endif
	case 4: return __xchg32((int) x, (int *) ptr);
	case 1: return __xchg8((char) x, (char *) ptr);
	}
	__xchg_called_with_bad_pointer();
	return x;
}


/*
** REVISIT - Abandoned use of LDCW in xchg() for now:
** o need to test sizeof(*ptr) to avoid clearing adjacent bytes
** o and while we are at it, could CONFIG_64BIT code use LDCD too?
**
**	if (__builtin_constant_p(x) && (x == NULL))
**		if (((unsigned long)p & 0xf) == 0)
**			return __ldcw(p);
*/
#define xchg(ptr,x) \
	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))


#define __HAVE_ARCH_CMPXCHG	1

/* bug catcher for when unsupported size is used - won't link */
extern void __cmpxchg_called_with_bad_pointer(void);

/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old, unsigned int new_);
extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new_);

/* don't worry...optimizer will get rid of most of this */
static __inline__ unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
{
	switch(size) {
#ifdef CONFIG_64BIT
	case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
#endif
	case 4: return __cmpxchg_u32((unsigned int *)ptr, (unsigned int) old, (unsigned int) new_);
	}
	__cmpxchg_called_with_bad_pointer();
	return old;
}

#define cmpxchg(ptr,o,n)						 \
  ({									 \
     __typeof__(*(ptr)) _o_ = (o);					 \
     __typeof__(*(ptr)) _n_ = (n);					 \
     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
				    (unsigned long)_n_, sizeof(*(ptr))); \
  })

/* Note that we need not lock read accesses - aligned word writes/reads
 * are atomic, so a reader never sees unconsistent values.
 *
 * Cache-line alignment would conflict with, for example, linux/module.h
 */

typedef struct { volatile int counter; } atomic_t;

/* It's possible to reduce all atomic operations to either
 * __atomic_add_return, atomic_set and atomic_read (the latter
 * is there only for consistency).
 */

static __inline__ int __atomic_add_return(int i, atomic_t *v)
{
	int ret;
	unsigned long flags;
	_atomic_spin_lock_irqsave(v, flags);

	ret = (v->counter += i);

	_atomic_spin_unlock_irqrestore(v, flags);
	return ret;
}

static __inline__ void atomic_set(atomic_t *v, int i) 
{
	unsigned long flags;
	_atomic_spin_lock_irqsave(v, flags);

	v->counter = i;

	_atomic_spin_unlock_irqrestore(v, flags);
}

static __inline__ int atomic_read(const atomic_t *v)
{
	return v->counter;
}

/* exported interface */
#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

/**
 * atomic_add_unless - add unless the number is a given value
 * @v: pointer of type atomic_t
 * @a: the amount to add to v...
 * @u: ...unless v is equal to u.
 *
 * Atomically adds @a to @v, so long as it was not @u.
 * Returns non-zero if @v was not @u, and zero otherwise.
 */
static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
{
	int c, old;
	c = atomic_read(v);
	for (;;) {
		if (unlikely(c == (u)))
			break;
		old = atomic_cmpxchg((v), c, c + (a));
		if (likely(old == c))
			break;
		c = old;
	}
	return c != (u);
}

#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)

#define atomic_add(i,v)	((void)(__atomic_add_return( ((int)i),(v))))
#define atomic_sub(i,v)	((void)(__atomic_add_return(-((int)i),(v))))
#define atomic_inc(v)	((void)(__atomic_add_return(   1,(v))))
#define atomic_dec(v)	((void)(__atomic_add_return(  -1,(v))))

#define atomic_add_return(i,v)	(__atomic_add_return( ((int)i),(v)))
#define atomic_sub_return(i,v)	(__atomic_add_return(-((int)i),(v)))
#define atomic_inc_return(v)	(__atomic_add_return(   1,(v)))
#define atomic_dec_return(v)	(__atomic_add_return(  -1,(v)))

#define atomic_add_negative(a, v)	(atomic_add_return((a), (v)) < 0)

/*
 * atomic_inc_and_test - increment and test
 * @v: pointer of type atomic_t
 *
 * Atomically increments @v by 1
 * and returns true if the result is zero, or false for all
 * other cases.
 */
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)

#define atomic_dec_and_test(v)	(atomic_dec_return(v) == 0)

#define atomic_sub_and_test(i,v)	(atomic_sub_return((i),(v)) == 0)

#define ATOMIC_INIT(i)	((atomic_t) { (i) })

#define smp_mb__before_atomic_dec()	smp_mb()
#define smp_mb__after_atomic_dec()	smp_mb()
#define smp_mb__before_atomic_inc()	smp_mb()
#define smp_mb__after_atomic_inc()	smp_mb()

#ifdef CONFIG_64BIT

typedef struct { volatile s64 counter; } atomic64_t;

#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })

static __inline__ int
__atomic64_add_return(s64 i, atomic64_t *v)
{
	int ret;
	unsigned long flags;
	_atomic_spin_lock_irqsave(v, flags);

	ret = (v->counter += i);

	_atomic_spin_unlock_irqrestore(v, flags);
	return ret;
}

static __inline__ void
atomic64_set(atomic64_t *v, s64 i)
{
	unsigned long flags;
	_atomic_spin_lock_irqsave(v, flags);

	v->counter = i;

	_atomic_spin_unlock_irqrestore(v, flags);
}

static __inline__ s64
atomic64_read(const atomic64_t *v)
{
	return v->counter;
}

#define atomic64_add(i,v)	((void)(__atomic64_add_return( ((s64)i),(v))))
#define atomic64_sub(i,v)	((void)(__atomic64_add_return(-((s64)i),(v))))
#define atomic64_inc(v)		((void)(__atomic64_add_return(   1,(v))))
#define atomic64_dec(v)		((void)(__atomic64_add_return(  -1,(v))))

#define atomic64_add_return(i,v)	(__atomic64_add_return( ((s64)i),(v)))
#define atomic64_sub_return(i,v)	(__atomic64_add_return(-((s64)i),(v)))
#define atomic64_inc_return(v)		(__atomic64_add_return(   1,(v)))
#define atomic64_dec_return(v)		(__atomic64_add_return(  -1,(v)))

#define atomic64_add_negative(a, v)	(atomic64_add_return((a), (v)) < 0)

#define atomic64_inc_and_test(v) 	(atomic64_inc_return(v) == 0)
#define atomic64_dec_and_test(v)	(atomic64_dec_return(v) == 0)
#define atomic64_sub_and_test(i,v)	(atomic64_sub_return((i),(v)) == 0)

/* exported interface */
#define atomic64_cmpxchg(v, o, n) \
	((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))

/**
 * atomic64_add_unless - add unless the number is a given value
 * @v: pointer of type atomic64_t
 * @a: the amount to add to v...
 * @u: ...unless v is equal to u.
 *
 * Atomically adds @a to @v, so long as it was not @u.
 * Returns non-zero if @v was not @u, and zero otherwise.
 */
static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
{
	long c, old;
	c = atomic64_read(v);
	for (;;) {
		if (unlikely(c == (u)))
			break;
		old = atomic64_cmpxchg((v), c, c + (a));
		if (likely(old == c))
			break;
		c = old;
	}
	return c != (u);
}

#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)

#endif /* CONFIG_64BIT */

#include <asm-generic/atomic.h>

#endif /* _ASM_PARISC_ATOMIC_H_ */
Commit	Line	Data
2e13b31e KM	1	/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
	2	* Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
	3	*/
	4
1da177e4 LT	5	#ifndef _ASM_PARISC_ATOMIC_H_
	6	#define _ASM_PARISC_ATOMIC_H_
	7
2e13b31e	8	#include <linux/types.h>
2856f5e3	9	#include <asm/system.h>
1da177e4 LT	10
	11	/*
	12	* Atomic operations that C can't guarantee us. Useful for
	13	* resource counting etc..
	14	*
	15	* And probably incredibly slow on parisc. OTOH, we don't
	16	* have to write any serious assembly. prumpf
	17	*/
	18
	19	#ifdef CONFIG_SMP
	20	#include <asm/spinlock.h>
	21	#include <asm/cache.h> /* we use L1_CACHE_BYTES */
	22
	23	/* Use an array of spinlocks for our atomic_ts.
	24	* Hash function to index into a different SPINLOCK.
	25	* Since "a" is usually an address, use one spinlock per cacheline.
	26	*/
	27	# define ATOMIC_HASH_SIZE 4
	28	# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
	29
fb1c8f93	30	extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
1da177e4	31
fb1c8f93	32	/* Can't use raw_spin_lock_irq because of #include problems, so
1da177e4 LT	33	* this is the substitute */
1da177e4 LT	34	#define _atomic_spin_lock_irqsave(l,f) do { \
fb1c8f93	35	raw_spinlock_t *s = ATOMIC_HASH(l); \
1da177e4	36	local_irq_save(f); \
fb1c8f93	37	__raw_spin_lock(s); \
1da177e4 LT	38	} while(0)
	39
	40	#define _atomic_spin_unlock_irqrestore(l,f) do { \
fb1c8f93 IM	41	raw_spinlock_t *s = ATOMIC_HASH(l); \
fb1c8f93 IM	42	__raw_spin_unlock(s); \
1da177e4 LT	43	local_irq_restore(f); \
	44	} while(0)
	45
	46
	47	#else
	48	# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
	49	# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
	50	#endif
	51
1da177e4 LT	52	/* This should get optimized out since it's never called.
	53	** Or get a link error if xchg is used "wrong".
	54	*/
	55	extern void __xchg_called_with_bad_pointer(void);
	56
	57
	58	/* __xchg32/64 defined in arch/parisc/lib/bitops.c */
	59	extern unsigned long __xchg8(char, char *);
	60	extern unsigned long __xchg32(int, int *);
513e7ecd	61	#ifdef CONFIG_64BIT
1da177e4 LT	62	extern unsigned long __xchg64(unsigned long, unsigned long *);
	63	#endif
	64
	65	/* optimizer better get rid of switch since size is a constant */
2e13b31e KM	66	static __inline__ unsigned long
2e13b31e KM	67	__xchg(unsigned long x, __volatile__ void * ptr, int size)
1da177e4	68	{
1da177e4	69	switch(size) {
513e7ecd	70	#ifdef CONFIG_64BIT
1da177e4 LT	71	case 8: return __xchg64(x,(unsigned long *) ptr);
	72	#endif
	73	case 4: return __xchg32((int) x, (int *) ptr);
	74	case 1: return __xchg8((char) x, (char *) ptr);
	75	}
	76	__xchg_called_with_bad_pointer();
	77	return x;
	78	}
	79
	80
	81	/*
	82	** REVISIT - Abandoned use of LDCW in xchg() for now:
	83	** o need to test sizeof(*ptr) to avoid clearing adjacent bytes
513e7ecd	84	** o and while we are at it, could CONFIG_64BIT code use LDCD too?
1da177e4 LT	85	**
	86	** if (__builtin_constant_p(x) && (x == NULL))
	87	** if (((unsigned long)p & 0xf) == 0)
	88	** return __ldcw(p);
	89	*/
	90	#define xchg(ptr,x) \
	91	((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
	92
	93
	94	#define __HAVE_ARCH_CMPXCHG 1
	95
	96	/* bug catcher for when unsupported size is used - won't link */
	97	extern void __cmpxchg_called_with_bad_pointer(void);
	98
	99	/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
	100	extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old, unsigned int new_);
	101	extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new_);
	102
	103	/* don't worry...optimizer will get rid of most of this */
	104	static __inline__ unsigned long
	105	__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
	106	{
	107	switch(size) {
513e7ecd	108	#ifdef CONFIG_64BIT
1da177e4 LT	109	case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
	110	#endif
	111	case 4: return __cmpxchg_u32((unsigned int *)ptr, (unsigned int) old, (unsigned int) new_);
	112	}
	113	__cmpxchg_called_with_bad_pointer();
	114	return old;
	115	}
	116
	117	#define cmpxchg(ptr,o,n) \
	118	({ \
	119	__typeof__(*(ptr)) _o_ = (o); \
	120	__typeof__(*(ptr)) _n_ = (n); \
	121	(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
	122	(unsigned long)_n_, sizeof(*(ptr))); \
	123	})
	124
2e13b31e KM	125	/* Note that we need not lock read accesses - aligned word writes/reads
	126	* are atomic, so a reader never sees unconsistent values.
	127	*
	128	* Cache-line alignment would conflict with, for example, linux/module.h
	129	*/
1da177e4	130
2e13b31e	131	typedef struct { volatile int counter; } atomic_t;
1da177e4 LT	132
	133	/* It's possible to reduce all atomic operations to either
	134	* __atomic_add_return, atomic_set and atomic_read (the latter
	135	* is there only for consistency).
	136	*/
	137
	138	static __inline__ int __atomic_add_return(int i, atomic_t *v)
	139	{
	140	int ret;
	141	unsigned long flags;
	142	_atomic_spin_lock_irqsave(v, flags);
	143
	144	ret = (v->counter += i);
	145
	146	_atomic_spin_unlock_irqrestore(v, flags);
	147	return ret;
	148	}
	149
	150	static __inline__ void atomic_set(atomic_t *v, int i)
	151	{
	152	unsigned long flags;
	153	_atomic_spin_lock_irqsave(v, flags);
	154
	155	v->counter = i;
	156
	157	_atomic_spin_unlock_irqrestore(v, flags);
	158	}
	159
	160	static __inline__ int atomic_read(const atomic_t *v)
	161	{
	162	return v->counter;
	163	}
	164
	165	/* exported interface */
8ffe9d0b	166	#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
ffbf670f	167	#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
1da177e4	168
8426e1f6 NP	169	/**
	170	* atomic_add_unless - add unless the number is a given value
	171	* @v: pointer of type atomic_t
	172	* @a: the amount to add to v...
	173	* @u: ...unless v is equal to u.
	174	*
	175	* Atomically adds @a to @v, so long as it was not @u.
	176	* Returns non-zero if @v was not @u, and zero otherwise.
	177	*/
2856f5e3 MD	178	static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
	179	{
	180	int c, old;
	181	c = atomic_read(v);
	182	for (;;) {
	183	if (unlikely(c == (u)))
	184	break;
	185	old = atomic_cmpxchg((v), c, c + (a));
	186	if (likely(old == c))
	187	break;
	188	c = old;
	189	}
	190	return c != (u);
	191	}
	192
8426e1f6 NP	193	#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
8426e1f6 NP	194
1da177e4 LT	195	#define atomic_add(i,v) ((void)(__atomic_add_return( ((int)i),(v))))
	196	#define atomic_sub(i,v) ((void)(__atomic_add_return(-((int)i),(v))))
	197	#define atomic_inc(v) ((void)(__atomic_add_return( 1,(v))))
	198	#define atomic_dec(v) ((void)(__atomic_add_return( -1,(v))))
	199
	200	#define atomic_add_return(i,v) (__atomic_add_return( ((int)i),(v)))
	201	#define atomic_sub_return(i,v) (__atomic_add_return(-((int)i),(v)))
	202	#define atomic_inc_return(v) (__atomic_add_return( 1,(v)))
	203	#define atomic_dec_return(v) (__atomic_add_return( -1,(v)))
	204
	205	#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
	206
	207	/*
	208	* atomic_inc_and_test - increment and test
	209	* @v: pointer of type atomic_t
	210	*
	211	* Atomically increments @v by 1
	212	* and returns true if the result is zero, or false for all
	213	* other cases.
	214	*/
	215	#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
	216
	217	#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
	218
4da9f131 KM	219	#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
4da9f131 KM	220
2e13b31e	221	#define ATOMIC_INIT(i) ((atomic_t) { (i) })
1da177e4 LT	222
	223	#define smp_mb__before_atomic_dec() smp_mb()
	224	#define smp_mb__after_atomic_dec() smp_mb()
	225	#define smp_mb__before_atomic_inc() smp_mb()
	226	#define smp_mb__after_atomic_inc() smp_mb()
	227
513e7ecd	228	#ifdef CONFIG_64BIT
2e13b31e KM	229
	230	typedef struct { volatile s64 counter; } atomic64_t;
	231
	232	#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
	233
	234	static __inline__ int
	235	__atomic64_add_return(s64 i, atomic64_t *v)
	236	{
	237	int ret;
	238	unsigned long flags;
	239	_atomic_spin_lock_irqsave(v, flags);
	240
	241	ret = (v->counter += i);
	242
	243	_atomic_spin_unlock_irqrestore(v, flags);
	244	return ret;
	245	}
	246
	247	static __inline__ void
	248	atomic64_set(atomic64_t *v, s64 i)
	249	{
	250	unsigned long flags;
	251	_atomic_spin_lock_irqsave(v, flags);
	252
	253	v->counter = i;
	254
	255	_atomic_spin_unlock_irqrestore(v, flags);
	256	}
	257
	258	static __inline__ s64
	259	atomic64_read(const atomic64_t *v)
	260	{
	261	return v->counter;
	262	}
	263
	264	#define atomic64_add(i,v) ((void)(__atomic64_add_return( ((s64)i),(v))))
	265	#define atomic64_sub(i,v) ((void)(__atomic64_add_return(-((s64)i),(v))))
	266	#define atomic64_inc(v) ((void)(__atomic64_add_return( 1,(v))))
	267	#define atomic64_dec(v) ((void)(__atomic64_add_return( -1,(v))))
	268
	269	#define atomic64_add_return(i,v) (__atomic64_add_return( ((s64)i),(v)))
	270	#define atomic64_sub_return(i,v) (__atomic64_add_return(-((s64)i),(v)))
	271	#define atomic64_inc_return(v) (__atomic64_add_return( 1,(v)))
	272	#define atomic64_dec_return(v) (__atomic64_add_return( -1,(v)))
	273
	274	#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
	275
	276	#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
	277	#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
4da9f131	278	#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i),(v)) == 0)
2e13b31e	279
8ffe9d0b MD	280	/* exported interface */
	281	#define atomic64_cmpxchg(v, o, n) \
	282	((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
	283	#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
	284
	285	/**
	286	* atomic64_add_unless - add unless the number is a given value
	287	* @v: pointer of type atomic64_t
	288	* @a: the amount to add to v...
	289	* @u: ...unless v is equal to u.
	290	*
	291	* Atomically adds @a to @v, so long as it was not @u.
	292	* Returns non-zero if @v was not @u, and zero otherwise.
	293	*/
2856f5e3 MD	294	static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
	295	{
	296	long c, old;
	297	c = atomic64_read(v);
	298	for (;;) {
	299	if (unlikely(c == (u)))
	300	break;
	301	old = atomic64_cmpxchg((v), c, c + (a));
	302	if (likely(old == c))
	303	break;
	304	c = old;
	305	}
	306	return c != (u);
	307	}
	308
8ffe9d0b MD	309	#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
8ffe9d0b MD	310
513e7ecd	311	#endif /* CONFIG_64BIT */
2e13b31e	312
d3cb4871	313	#include <asm-generic/atomic.h>
2e13b31e KM	314
2e13b31e KM	315	#endif /* _ASM_PARISC_ATOMIC_H_ */