Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * include/asm-parisc/cache.h | |
3 | */ | |
4 | ||
5 | #ifndef __ARCH_PARISC_CACHE_H | |
6 | #define __ARCH_PARISC_CACHE_H | |
7 | ||
8 | #include <linux/config.h> | |
9 | ||
10 | /* | |
11 | * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have | |
12 | * 32-byte cachelines. The default configuration is not for SMP anyway, | |
13 | * so if you're building for SMP, you should select the appropriate | |
14 | * processor type. There is a potential livelock danger when running | |
15 | * a machine with this value set too small, but it's more probable you'll | |
16 | * just ruin performance. | |
17 | */ | |
18 | #ifdef CONFIG_PA20 | |
19 | #define L1_CACHE_BYTES 64 | |
20 | #define L1_CACHE_SHIFT 6 | |
21 | #else | |
22 | #define L1_CACHE_BYTES 32 | |
23 | #define L1_CACHE_SHIFT 5 | |
24 | #endif | |
25 | ||
26 | #ifndef __ASSEMBLY__ | |
27 | ||
28 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) | |
29 | ||
30 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | |
31 | #define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */ | |
32 | ||
33 | extern void flush_data_cache_local(void); /* flushes local data-cache only */ | |
34 | extern void flush_instruction_cache_local(void); /* flushes local code-cache only */ | |
35 | #ifdef CONFIG_SMP | |
36 | extern void flush_data_cache(void); /* flushes data-cache only (all processors) */ | |
37 | extern void flush_instruction_cache(void); /* flushes i-cache only (all processors) */ | |
38 | #else | |
39 | #define flush_data_cache flush_data_cache_local | |
40 | #define flush_instruction_cache flush_instruction_cache_local | |
41 | #endif | |
42 | ||
43 | extern void parisc_cache_init(void); /* initializes cache-flushing */ | |
44 | extern void flush_all_caches(void); /* flush everything (tlb & cache) */ | |
45 | extern int get_cache_info(char *); | |
46 | extern void flush_user_icache_range_asm(unsigned long, unsigned long); | |
47 | extern void flush_kernel_icache_range_asm(unsigned long, unsigned long); | |
48 | extern void flush_user_dcache_range_asm(unsigned long, unsigned long); | |
49 | extern void flush_kernel_dcache_range_asm(unsigned long, unsigned long); | |
50 | extern void flush_kernel_dcache_page(void *); | |
51 | extern void flush_kernel_icache_page(void *); | |
52 | extern void disable_sr_hashing(void); /* turns off space register hashing */ | |
53 | extern void disable_sr_hashing_asm(int); /* low level support for above */ | |
54 | extern void free_sid(unsigned long); | |
55 | unsigned long alloc_sid(void); | |
56 | extern void flush_user_dcache_page(unsigned long); | |
57 | extern void flush_user_icache_page(unsigned long); | |
58 | ||
59 | struct seq_file; | |
60 | extern void show_cache_info(struct seq_file *m); | |
61 | ||
62 | extern int split_tlb; | |
63 | extern int dcache_stride; | |
64 | extern int icache_stride; | |
65 | extern struct pdc_cache_info cache_info; | |
66 | ||
67 | #define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr)); | |
68 | #define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr)); | |
69 | #define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr)); | |
70 | ||
71 | #endif /* ! __ASSEMBLY__ */ | |
72 | ||
73 | /* Classes of processor wrt: disabling space register hashing */ | |
74 | ||
75 | #define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */ | |
76 | #define SRHASH_PCXL 1 /* pcxl */ | |
77 | #define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */ | |
78 | ||
79 | #endif |