[deliverable/linux.git] / include / asm-parisc / pci.h

#ifndef __ASM_PARISC_PCI_H
#define __ASM_PARISC_PCI_H

#include <linux/config.h>
#include <asm/scatterlist.h>


/*
** HP PCI platforms generally support multiple bus adapters.
**    (workstations 1-~4, servers 2-~32)
**
** Newer platforms number the busses across PCI bus adapters *sparsely*.
** E.g. 0, 8, 16, ...
**
** Under a PCI bus, most HP platforms support PPBs up to two or three
** levels deep. See "Bit3" product line. 
*/
#define PCI_MAX_BUSSES	256


/* To be used as: mdelay(pci_post_reset_delay);
 *
 * post_reset is the time the kernel should stall to prevent anyone from
 * accessing the PCI bus once #RESET is de-asserted. 
 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
 * this makes the boot time much longer than necessary.
 * 20ms seems to work for all the HP PCI implementations to date.
 */
#define pci_post_reset_delay 50


/*
** pci_hba_data (aka H2P_OBJECT in HP/UX)
**
** This is the "common" or "base" data structure which HBA drivers
** (eg Dino or LBA) are required to place at the top of their own
** platform_data structure.  I've heard this called "C inheritance" too.
**
** Data needed by pcibios layer belongs here.
*/
struct pci_hba_data {
	void __iomem   *base_addr;	/* aka Host Physical Address */
	const struct parisc_device *dev; /* device from PA bus walk */
	struct pci_bus *hba_bus;	/* primary PCI bus below HBA */
	int		hba_num;	/* I/O port space access "key" */
	struct resource bus_num;	/* PCI bus numbers */
	struct resource io_space;	/* PIOP */
	struct resource lmmio_space;	/* bus addresses < 4Gb */
	struct resource elmmio_space;	/* additional bus addresses < 4Gb */
	struct resource gmmio_space;	/* bus addresses > 4Gb */

	/* NOTE: Dino code assumes it can use *all* of the lmmio_space,
	 * elmmio_space and gmmio_space as a contiguous array of
	 * resources.  This #define represents the array size */
	#define DINO_MAX_LMMIO_RESOURCES	3

	unsigned long   lmmio_space_offset;  /* CPU view - PCI view */
	void *          iommu;          /* IOMMU this device is under */
	/* REVISIT - spinlock to protect resources? */

	#define HBA_NAME_SIZE 16
	char io_name[HBA_NAME_SIZE];
	char lmmio_name[HBA_NAME_SIZE];
	char elmmio_name[HBA_NAME_SIZE];
	char gmmio_name[HBA_NAME_SIZE];
};

#define HBA_DATA(d)		((struct pci_hba_data *) (d))

/* 
** We support 2^16 I/O ports per HBA.  These are set up in the form
** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
** space address.
*/
#define HBA_PORT_SPACE_BITS	16

#define HBA_PORT_BASE(h)	((h) << HBA_PORT_SPACE_BITS)
#define HBA_PORT_SPACE_SIZE	(1UL << HBA_PORT_SPACE_BITS)

#define PCI_PORT_HBA(a)		((a) >> HBA_PORT_SPACE_BITS)
#define PCI_PORT_ADDR(a)	((a) & (HBA_PORT_SPACE_SIZE - 1))

#ifdef CONFIG_64BIT
#define PCI_F_EXTEND		0xffffffff00000000UL
#define PCI_IS_LMMIO(hba,a)	pci_is_lmmio(hba,a)

/* We need to know if an address is LMMMIO or GMMIO.
 * LMMIO requires mangling and GMMIO we must use as-is.
 */
static __inline__  int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
{
	return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
}

/*
** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
** See pci.c for more conversions used by Generic PCI code.
**
** Platform characteristics/firmware guarantee that
**	(1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
**	(2) PA_VIEW == IO_VIEW for GMMIO
*/
#define PCI_BUS_ADDR(hba,a)	(PCI_IS_LMMIO(hba,a)	\
		?  ((a) - hba->lmmio_space_offset)	/* mangle LMMIO */ \
		: (a))					/* GMMIO */
#define PCI_HOST_ADDR(hba,a)	(((a) & PCI_F_EXTEND) == 0 \
		? (a) + hba->lmmio_space_offset \
		: (a))

#else	/* !CONFIG_64BIT */

#define PCI_BUS_ADDR(hba,a)	(a)
#define PCI_HOST_ADDR(hba,a)	(a)
#define PCI_F_EXTEND		0UL
#define PCI_IS_LMMIO(hba,a)	(1)	/* 32-bit doesn't support GMMIO */

#endif /* !CONFIG_64BIT */

/*
** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
** (This eliminates some of the warnings).
*/
struct pci_bus;
struct pci_dev;

/*
 * If the PCI device's view of memory is the same as the CPU's view of memory,
 * PCI_DMA_BUS_IS_PHYS is true.  The networking and block device layers use
 * this boolean for bounce buffer decisions.
 */
#ifdef CONFIG_PA20
/* All PA-2.0 machines have an IOMMU. */
#define PCI_DMA_BUS_IS_PHYS	0
#define parisc_has_iommu()	do { } while (0)
#else

#if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA)
extern int parisc_bus_is_phys; 	/* in arch/parisc/kernel/setup.c */
#define PCI_DMA_BUS_IS_PHYS	parisc_bus_is_phys
#define parisc_has_iommu()	do { parisc_bus_is_phys = 0; } while (0)
#else
#define PCI_DMA_BUS_IS_PHYS	1
#define parisc_has_iommu()	do { } while (0)
#endif

#endif	/* !CONFIG_PA20 */


/*
** Most PCI devices (eg Tulip, NCR720) also export the same registers
** to both MMIO and I/O port space.  Due to poor performance of I/O Port
** access under HP PCI bus adapters, strongly reccomend use of MMIO
** address space.
**
** While I'm at it more PA programming notes:
**
** 1) MMIO stores (writes) are posted operations. This means the processor
**    gets an "ACK" before the write actually gets to the device. A read
**    to the same device (or typically the bus adapter above it) will
**    force in-flight write transaction(s) out to the targeted device
**    before the read can complete.
**
** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
**    respect to DMA on all platforms. Ie PIO data can reach the processor
**    before in-flight DMA reaches memory. Since most SMP PA platforms
**    are I/O coherent, it generally doesn't matter...but sometimes
**    it does.
**
** I've helped device driver writers debug both types of problems.
*/
struct pci_port_ops {
	  u8 (*inb)  (struct pci_hba_data *hba, u16 port);
	 u16 (*inw)  (struct pci_hba_data *hba, u16 port);
	 u32 (*inl)  (struct pci_hba_data *hba, u16 port);
	void (*outb) (struct pci_hba_data *hba, u16 port,  u8 data);
	void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
	void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
};


struct pci_bios_ops {
	void (*init)(void);
	void (*fixup_bus)(struct pci_bus *bus);
};

/* pci_unmap_{single,page} is not a nop, thus... */
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
	dma_addr_t ADDR_NAME;
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
	__u32 LEN_NAME;
#define pci_unmap_addr(PTR, ADDR_NAME)			\
	((PTR)->ADDR_NAME)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
	(((PTR)->ADDR_NAME) = (VAL))
#define pci_unmap_len(PTR, LEN_NAME)			\
	((PTR)->LEN_NAME)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
	(((PTR)->LEN_NAME) = (VAL))

/*
** Stuff declared in arch/parisc/kernel/pci.c
*/
extern struct pci_port_ops *pci_port;
extern struct pci_bios_ops *pci_bios;
extern int pci_hba_count;
extern struct pci_hba_data *parisc_pci_hba[];

#ifdef CONFIG_PCI
extern void pcibios_register_hba(struct pci_hba_data *);
extern void pcibios_set_master(struct pci_dev *);
#else
extern inline void pcibios_register_hba(struct pci_hba_data *x)
{
}
#endif

/*
 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
 *   0 == check if bridge is numbered before re-numbering.
 *   1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
 *
 *   We *should* set this to zero for "legacy" platforms and one
 *   for PAT platforms.
 *
 *   But legacy platforms also need to renumber the busses below a Host
 *   Bus controller.  Adding a 4-port Tulip card on the first PCI root
 *   bus of a C200 resulted in the secondary bus being numbered as 1.
 *   The second PCI host bus controller's root bus had already been
 *   assigned bus number 1 by firmware and sysfs complained.
 *
 *   Firmware isn't doing anything wrong here since each controller
 *   is its own PCI domain.  It's simpler and easier for us to renumber
 *   the busses rather than treat each Dino as a separate PCI domain.
 *   Eventually, we may want to introduce PCI domains for Superdome or
 *   rp7420/8420 boxes and then revisit this issue.
 */
#define pcibios_assign_all_busses()     (1)
#define pcibios_scan_all_fns(a, b)	(0)

#define PCIBIOS_MIN_IO          0x10
#define PCIBIOS_MIN_MEM         0x1000 /* NBPG - but pci/setup-res.c dies */

/* Don't support DAC yet. */
#define pci_dac_dma_supported(pci_dev, mask)   (0)

/* export the pci_ DMA API in terms of the dma_ one */
#include <asm-generic/pci-dma-compat.h>

#ifdef CONFIG_PCI
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	unsigned long cacheline_size;
	u8 byte;

	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	if (byte == 0)
		cacheline_size = 1024;
	else
		cacheline_size = (int) byte * 4;

	*strat = PCI_DMA_BURST_MULTIPLE;
	*strategy_parameter = cacheline_size;
}
#endif

extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
			 struct resource *res);

extern void
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
			struct pci_bus_region *region);

static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
	struct resource *root = NULL;

	if (res->flags & IORESOURCE_IO)
		root = &ioport_resource;
	if (res->flags & IORESOURCE_MEM)
		root = &iomem_resource;

	return root;
}

static inline void pcibios_add_platform_entries(struct pci_dev *dev)
{
}

#endif /* __ASM_PARISC_PCI_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_PARISC_PCI_H
	2	#define __ASM_PARISC_PCI_H
	3
	4	#include <linux/config.h>
	5	#include <asm/scatterlist.h>
	6
	7
	8
	9	/*
	10	** HP PCI platforms generally support multiple bus adapters.
	11	** (workstations 1-~4, servers 2-~32)
	12	**
	13	** Newer platforms number the busses across PCI bus adapters sparsely.
	14	** E.g. 0, 8, 16, ...
	15	**
	16	** Under a PCI bus, most HP platforms support PPBs up to two or three
	17	** levels deep. See "Bit3" product line.
	18	*/
	19	#define PCI_MAX_BUSSES 256
	20
cb6fc18e HD	21
	22	/* To be used as: mdelay(pci_post_reset_delay);
	23	*
	24	* post_reset is the time the kernel should stall to prevent anyone from
	25	* accessing the PCI bus once #RESET is de-asserted.
	26	* PCI spec somewhere says 1 second but with multi-PCI bus systems,
	27	* this makes the boot time much longer than necessary.
	28	* 20ms seems to work for all the HP PCI implementations to date.
	29	*/
	30	#define pci_post_reset_delay 50
	31
	32
1da177e4 LT	33	/*
	34	** pci_hba_data (aka H2P_OBJECT in HP/UX)
	35	**
	36	** This is the "common" or "base" data structure which HBA drivers
	37	** (eg Dino or LBA) are required to place at the top of their own
	38	** platform_data structure. I've heard this called "C inheritance" too.
	39	**
	40	** Data needed by pcibios layer belongs here.
	41	*/
	42	struct pci_hba_data {
	43	void __iomem base_addr; / aka Host Physical Address */
	44	const struct parisc_device dev; / device from PA bus walk */
	45	struct pci_bus hba_bus; / primary PCI bus below HBA */
	46	int hba_num; /* I/O port space access "key" */
	47	struct resource bus_num; /* PCI bus numbers */
	48	struct resource io_space; /* PIOP */
	49	struct resource lmmio_space; /* bus addresses < 4Gb */
	50	struct resource elmmio_space; /* additional bus addresses < 4Gb */
	51	struct resource gmmio_space; /* bus addresses > 4Gb */
	52
	53	/* NOTE: Dino code assumes it can use all of the lmmio_space,
	54	* elmmio_space and gmmio_space as a contiguous array of
	55	* resources. This #define represents the array size */
	56	#define DINO_MAX_LMMIO_RESOURCES 3
	57
	58	unsigned long lmmio_space_offset; /* CPU view - PCI view */
	59	void * iommu; /* IOMMU this device is under */
	60	/* REVISIT - spinlock to protect resources? */
	61
	62	#define HBA_NAME_SIZE 16
	63	char io_name[HBA_NAME_SIZE];
	64	char lmmio_name[HBA_NAME_SIZE];
	65	char elmmio_name[HBA_NAME_SIZE];
	66	char gmmio_name[HBA_NAME_SIZE];
	67	};
	68
	69	#define HBA_DATA(d) ((struct pci_hba_data *) (d))
	70
	71	/*
	72	** We support 2^16 I/O ports per HBA. These are set up in the form
	73	** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
	74	** space address.
	75	*/
	76	#define HBA_PORT_SPACE_BITS 16
	77
	78	#define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
	79	#define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
	80
	81	#define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
	82	#define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
	83
74d13f84	84	#ifdef CONFIG_64BIT
1da177e4 LT	85	#define PCI_F_EXTEND 0xffffffff00000000UL
	86	#define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a)
	87
	88	/* We need to know if an address is LMMMIO or GMMIO.
	89	* LMMIO requires mangling and GMMIO we must use as-is.
	90	*/
	91	static __inline__ int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
	92	{
	93	return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
	94	}
	95
	96	/*
	97	** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
cb6fc18e	98	** See pci.c for more conversions used by Generic PCI code.
9b9ff2e1 GG	99	**
	100	** Platform characteristics/firmware guarantee that
	101	** (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
	102	** (2) PA_VIEW == IO_VIEW for GMMIO
1da177e4 LT	103	*/
	104	#define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \
	105	? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \
	106	: (a)) /* GMMIO */
9b9ff2e1 GG	107	#define PCI_HOST_ADDR(hba,a) (((a) & PCI_F_EXTEND) == 0 \
	108	? (a) + hba->lmmio_space_offset \
	109	: (a))
1da177e4 LT	110
	111	#else /* !CONFIG_64BIT */
	112
	113	#define PCI_BUS_ADDR(hba,a) (a)
	114	#define PCI_HOST_ADDR(hba,a) (a)
	115	#define PCI_F_EXTEND 0UL
	116	#define PCI_IS_LMMIO(hba,a) (1) /* 32-bit doesn't support GMMIO */
	117
	118	#endif /* !CONFIG_64BIT */
	119
	120	/*
	121	** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
	122	** (This eliminates some of the warnings).
	123	*/
	124	struct pci_bus;
	125	struct pci_dev;
	126
	127	/*
	128	* If the PCI device's view of memory is the same as the CPU's view of memory,
	129	* PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use
	130	* this boolean for bounce buffer decisions.
	131	*/
	132	#ifdef CONFIG_PA20
	133	/* All PA-2.0 machines have an IOMMU. */
	134	#define PCI_DMA_BUS_IS_PHYS 0
	135	#define parisc_has_iommu() do { } while (0)
	136	#else
	137
	138	#if defined(CONFIG_IOMMU_CCIO) \|\| defined(CONFIG_IOMMU_SBA)
	139	extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */
	140	#define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys
	141	#define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0)
	142	#else
	143	#define PCI_DMA_BUS_IS_PHYS 1
	144	#define parisc_has_iommu() do { } while (0)
	145	#endif
	146
	147	#endif /* !CONFIG_PA20 */
	148
	149
	150	/*
	151	** Most PCI devices (eg Tulip, NCR720) also export the same registers
	152	** to both MMIO and I/O port space. Due to poor performance of I/O Port
	153	** access under HP PCI bus adapters, strongly reccomend use of MMIO
	154	** address space.
	155	**
	156	** While I'm at it more PA programming notes:
	157	**
	158	** 1) MMIO stores (writes) are posted operations. This means the processor
	159	** gets an "ACK" before the write actually gets to the device. A read
	160	** to the same device (or typically the bus adapter above it) will
	161	** force in-flight write transaction(s) out to the targeted device
	162	** before the read can complete.
	163	**
	164	** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
	165	** respect to DMA on all platforms. Ie PIO data can reach the processor
	166	** before in-flight DMA reaches memory. Since most SMP PA platforms
	167	** are I/O coherent, it generally doesn't matter...but sometimes
	168	** it does.
	169	**
	170	** I've helped device driver writers debug both types of problems.
	171	*/
	172	struct pci_port_ops {
	173	u8 (inb) (struct pci_hba_data hba, u16 port);
174	u16 (inw) (struct pci_hba_data hba, u16 port);
175	u32 (inl) (struct pci_hba_data hba, u16 port);
176	void (outb) (struct pci_hba_data hba, u16 port, u8 data);
177	void (outw) (struct pci_hba_data hba, u16 port, u16 data);
178	void (outl) (struct pci_hba_data hba, u16 port, u32 data);
179	};
180
181
182	struct pci_bios_ops {
183	void (*init)(void);
184	void (fixup_bus)(struct pci_bus bus);
185	};
186
187	/* pci_unmap_{single,page} is not a nop, thus... */
188	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
189	dma_addr_t ADDR_NAME;
190	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
191	__u32 LEN_NAME;
192	#define pci_unmap_addr(PTR, ADDR_NAME) \
193	((PTR)->ADDR_NAME)
194	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
195	(((PTR)->ADDR_NAME) = (VAL))
196	#define pci_unmap_len(PTR, LEN_NAME) \
197	((PTR)->LEN_NAME)
198	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
199	(((PTR)->LEN_NAME) = (VAL))
200
201	/*
202	** Stuff declared in arch/parisc/kernel/pci.c
203	*/
204	extern struct pci_port_ops *pci_port;
205	extern struct pci_bios_ops *pci_bios;
1da177e4 LT	206	extern int pci_hba_count;
	207	extern struct pci_hba_data *parisc_pci_hba[];
	208
	209	#ifdef CONFIG_PCI
	210	extern void pcibios_register_hba(struct pci_hba_data *);
	211	extern void pcibios_set_master(struct pci_dev *);
	212	#else
	213	extern inline void pcibios_register_hba(struct pci_hba_data *x)
	214	{
	215	}
	216	#endif
	217
	218	/*
	219	* pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
	220	* 0 == check if bridge is numbered before re-numbering.
	221	* 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
	222	*
	223	* We should set this to zero for "legacy" platforms and one
	224	* for PAT platforms.
	225	*
	226	* But legacy platforms also need to renumber the busses below a Host
	227	* Bus controller. Adding a 4-port Tulip card on the first PCI root
	228	* bus of a C200 resulted in the secondary bus being numbered as 1.
	229	* The second PCI host bus controller's root bus had already been
	230	* assigned bus number 1 by firmware and sysfs complained.
	231	*
	232	* Firmware isn't doing anything wrong here since each controller
	233	* is its own PCI domain. It's simpler and easier for us to renumber
	234	* the busses rather than treat each Dino as a separate PCI domain.
	235	* Eventually, we may want to introduce PCI domains for Superdome or
	236	* rp7420/8420 boxes and then revisit this issue.
	237	*/
	238	#define pcibios_assign_all_busses() (1)
	239	#define pcibios_scan_all_fns(a, b) (0)
	240
	241	#define PCIBIOS_MIN_IO 0x10
	242	#define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
	243
	244	/* Don't support DAC yet. */
	245	#define pci_dac_dma_supported(pci_dev, mask) (0)
	246
	247	/* export the pci_ DMA API in terms of the dma_ one */
	248	#include <asm-generic/pci-dma-compat.h>
	249
bb4a61b6	250	#ifdef CONFIG_PCI
e24c2d96 DM	251	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	252	enum pci_dma_burst_strategy *strat,
	253	unsigned long *strategy_parameter)
	254	{
	255	unsigned long cacheline_size;
	256	u8 byte;
	257
	258	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	259	if (byte == 0)
	260	cacheline_size = 1024;
	261	else
	262	cacheline_size = (int) byte * 4;
	263
	264	*strat = PCI_DMA_BURST_MULTIPLE;
	265	*strategy_parameter = cacheline_size;
	266	}
bb4a61b6	267	#endif
e24c2d96	268
1da177e4 LT	269	extern void
	270	pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
	271	struct resource *res);
	272
43c34735 DB	273	extern void
	274	pcibios_bus_to_resource(struct pci_dev dev, struct resource res,
	275	struct pci_bus_region *region);
	276
085ae41f DM	277	static inline struct resource *
	278	pcibios_select_root(struct pci_dev pdev, struct resource res)
	279	{
	280	struct resource *root = NULL;
	281
	282	if (res->flags & IORESOURCE_IO)
	283	root = &ioport_resource;
	284	if (res->flags & IORESOURCE_MEM)
	285	root = &iomem_resource;
	286
	287	return root;
	288	}
	289
1da177e4 LT	290	static inline void pcibios_add_platform_entries(struct pci_dev *dev)
	291	{
	292	}
	293
	294	#endif /* __ASM_PARISC_PCI_H */