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[POWERPC] Add cpu feature for SPE handling
[deliverable/linux.git] / include / asm-powerpc / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
3ddfbcf1 4#include <asm/asm-compat.h>
10b35d99
KG		 5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 17#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
80f15dc7 22#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 25#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 26#define PPC_FEATURE_PA6T 0x00000800
974a76f5
PM		 27#define PPC_FEATURE_HAS_DFP 0x00000400
28#define PPC_FEATURE_POWER6_EXT 0x00000200
10b35d99 29
fab5db97
PM		 30#define PPC_FEATURE_TRUE_LE 0x00000002
31#define PPC_FEATURE_PPC_LE 0x00000001
32
10b35d99
KG		 33#ifdef __KERNEL__
34#ifndef __ASSEMBLY__
35
36/* This structure can grow, it's real size is used by head.S code
37 * via the mkdefs mechanism.
38 */
39struct cpu_spec;
10b35d99 40
10b35d99 41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 42typedef void (*cpu_restore_t)(void);
10b35d99 43
32a33994 44enum powerpc_oprofile_type {
7a45fb19
AW		 45 PPC_OPROFILE_INVALID = 0,
46 PPC_OPROFILE_RS64 = 1,
47 PPC_OPROFILE_POWER4 = 2,
48 PPC_OPROFILE_G4 = 3,
49 PPC_OPROFILE_BOOKE = 4,
18f2190d 50 PPC_OPROFILE_CELL = 5,
25fc530e 51 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 52};
53
1bd2e5ae
OJ		 54enum powerpc_pmc_type {
55 PPC_PMC_DEFAULT = 0,
56 PPC_PMC_IBM = 1,
57 PPC_PMC_PA6T = 2,
58};
59
10b35d99
KG		 60struct cpu_spec {
61 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
62 unsigned int pvr_mask;
63 unsigned int pvr_value;
64
65 char *cpu_name;
66 unsigned long cpu_features; /* Kernel features */
67 unsigned int cpu_user_features; /* Userland features */
68
69 /* cache line sizes */
70 unsigned int icache_bsize;
71 unsigned int dcache_bsize;
72
73 /* number of performance monitor counters */
74 unsigned int num_pmcs;
1bd2e5ae 75 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 76
77 /* this is called to initialize various CPU bits like L1 cache,
78 * BHT, SPD, etc... from head.S before branching to identify_machine
79 */
80 cpu_setup_t cpu_setup;
f39b7a55
OJ		 81 /* Used to restore cpu setup on secondary processors and at resume */
82 cpu_restore_t cpu_restore;
10b35d99
KG		 83
84 /* Used by oprofile userspace to select the right counters */
85 char *oprofile_cpu_type;
86
87 /* Processor specific oprofile operations */
32a33994 88 enum powerpc_oprofile_type oprofile_type;
80f15dc7 89
e78dbc80
MN		 90 /* Bit locations inside the mmcra change */
91 unsigned long oprofile_mmcra_sihv;
92 unsigned long oprofile_mmcra_sipr;
93
94 /* Bits to clear during an oprofile exception */
95 unsigned long oprofile_mmcra_clear;
96
80f15dc7
PM		 97 /* Name of processor class, for the ELF AT_PLATFORM entry */
98 char *platform;
10b35d99
KG		 99};
100
10b35d99 101extern struct cpu_spec *cur_cpu_spec;
10b35d99 102
42c4aaad
BH		 103extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
104
974a76f5 105extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 106extern void do_feature_fixups(unsigned long value, void *fixup_start,
107 void *fixup_end);
9b6b563c 108
10b35d99
KG		 109#endif /* __ASSEMBLY__ */
110
111/* CPU kernel features */
112
113/* Retain the 32b definitions all use bottom half of word */
4508dc21 114#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
10b35d99
KG		 115#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
116#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
117#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
118#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
119#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
120#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
121#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
122#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
123#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
124#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
125#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
126#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
127#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
128#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
129#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
130#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
131#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
132#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
133#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b 134#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 135#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
136#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
aa42c69c 137#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
4508dc21 138#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
5e14d21e 139#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
10b35d99 140
3965f8c5
PM		 141/*
142 * Add the 64-bit processor unique features in the top half of the word;
143 * on 32-bit, make the names available but defined to be 0.
144 */
10b35d99 145#ifdef __powerpc64__
3965f8c5 146#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 147#else
3965f8c5 148#define LONG_ASM_CONST(x) 0
10b35d99
KG		 149#endif
150
3965f8c5
PM		 151#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
152#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
153#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
154#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
155#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
156#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
157#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
158#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
3965f8c5
PM		 159#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
160#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
161#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
162#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9 163#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
974a76f5 164#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
4c198557 165#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
3965f8c5 166
10b35d99
KG		 167#ifndef __ASSEMBLY__
168
0470466d
SR		 169#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
170 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
171 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
10b35d99
KG		 172
173/* We only set the altivec features if the kernel was compiled with altivec
174 * support
175 */
176#ifdef CONFIG_ALTIVEC
177#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
178#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
179#else
180#define CPU_FTR_ALTIVEC_COMP 0
181#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
182#endif
183
5e14d21e
KG		 184/* We only set the spe features if the kernel was compiled with spe
185 * support
186 */
187#ifdef CONFIG_SPE
188#define CPU_FTR_SPE_COMP CPU_FTR_SPE
189#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
190#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
191#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
192#else
193#define CPU_FTR_SPE_COMP 0
194#define PPC_FEATURE_HAS_SPE_COMP 0
195#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
196#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
197#endif
198
10b35d99 199/* We need to mark all pages as being coherent if we're SMP or we
1775dbbc
KG		 200 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
201 * it for PCI "streaming/prefetch" to work properly.
10b35d99 202 */
1775dbbc
KG		 203#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
204 || defined(CONFIG_PPC_83xx)
10b35d99
KG		 205#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
206#else
207#define CPU_FTR_COMMON 0
208#endif
209
210/* The powersave features NAP & DOZE seems to confuse BDI when
211 debugging. So if a BDI is used, disable theses
212 */
213#ifndef CONFIG_BDI_SWITCH
214#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
215#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
216#else
217#define CPU_FTR_MAYBE_CAN_DOZE 0
218#define CPU_FTR_MAYBE_CAN_NAP 0
219#endif
220
221#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
222 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
223 !defined(CONFIG_BOOKE))
224
4508dc21
DG		 225#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
226 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
227#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 228 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 229 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 230#define CPU_FTRS_604 (CPU_FTR_COMMON | \
fab5db97
PM		 231 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
232 CPU_FTR_PPC_LE)
4508dc21 233#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 234 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97 235 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 236#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 237 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 238 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
239 CPU_FTR_PPC_LE)
4508dc21 240#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 241 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 242 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
243 CPU_FTR_PPC_LE)
b6f41cc8
JB		 244#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
245#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
246#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
247#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
248 CPU_FTR_HAS_HIGH_BATS)
249#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 250#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c
SR		 251 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
252 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 253 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 254#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c
SR		 255 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
256 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 257 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 258#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c
SR		 259 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
260 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 261 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 262#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 263 CPU_FTR_USE_TB | \
264 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
265 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
266 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 267 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 268#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
7c92943c
SR		 269 CPU_FTR_USE_TB | \
270 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
271 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 272 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 273#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
7c92943c
SR		 274 CPU_FTR_USE_TB | \
275 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
276 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 277 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 278#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
7c92943c
SR		 279 CPU_FTR_USE_TB | \
280 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
281 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
282 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 283 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
4508dc21 284#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 285 CPU_FTR_USE_TB | \
286 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
287 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
288 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 289 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 290#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 291 CPU_FTR_USE_TB | \
292 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
293 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
294 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 295 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
4508dc21 296#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 297 CPU_FTR_USE_TB | \
298 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
299 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
300 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 301 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 302#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 303 CPU_FTR_USE_TB | \
304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
305 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
306 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 307 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 308#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 309 CPU_FTR_USE_TB | \
310 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
311 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
312 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
313 CPU_FTR_PPC_LE)
4508dc21 314#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 315 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
4508dc21 316#define CPU_FTRS_G2_LE (CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c 317 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
4508dc21 318#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c
SR		 319 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
320 CPU_FTR_COMMON)
4508dc21 321#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
aa42c69c
KP		 322 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
323 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
4508dc21 324#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
7c92943c 325 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
4508dc21
DG		 326#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
327#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
328#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
5e14d21e
KG		 329#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
330 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
331 CPU_FTR_UNIFIED_ID_CACHE)
332#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
333 CPU_FTR_NODSISRALIGN)
334#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
7c92943c
SR		 335 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
336#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 337
338/* 64-bit CPUs */
4508dc21 339#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
fab5db97 340 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
4508dc21 341#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
7c92943c
SR		 342 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
343 CPU_FTR_MMCRA | CPU_FTR_CTRL)
4508dc21 344#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
00243000
OJ		 345 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
346 CPU_FTR_MMCRA)
4508dc21 347#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
00243000 348 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 349 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
4508dc21 350#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
00243000 351 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 352 CPU_FTR_MMCRA | CPU_FTR_SMT | \
353 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
e78dbc80 354 CPU_FTR_PURR)
4508dc21 355#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
00243000 356 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 357 CPU_FTR_MMCRA | CPU_FTR_SMT | \
358 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
4c198557
AB		 359 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
360 CPU_FTR_DSCR)
4508dc21 361#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
00243000 362 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 363 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
859deea9 364 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
4508dc21 365#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
b3ebd1d8
OJ		 366 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
367 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
368 CPU_FTR_PURR | CPU_FTR_REAL_LE)
4508dc21 369#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
7c92943c 370 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 371
2406f606 372#ifdef __powerpc64__
7c92943c
SR		 373#define CPU_FTRS_POSSIBLE \
374 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 375 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
b3ebd1d8 376 CPU_FTRS_CELL | CPU_FTRS_PA6T)
2406f606 377#else
7c92943c
SR		 378enum {
379 CPU_FTRS_POSSIBLE =
10b35d99
KG		 380#if CLASSIC_PPC
381 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
382 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
383 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
384 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
385 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
386 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
387 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 388 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
389 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 390#else
391 CPU_FTRS_GENERIC_32 |
392#endif
10b35d99
KG		 393#ifdef CONFIG_8xx
394 CPU_FTRS_8XX |
395#endif
396#ifdef CONFIG_40x
397 CPU_FTRS_40X |
398#endif
399#ifdef CONFIG_44x
400 CPU_FTRS_44X |
401#endif
402#ifdef CONFIG_E200
403 CPU_FTRS_E200 |
404#endif
405#ifdef CONFIG_E500
406 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
407#endif
10b35d99 408 0,
7c92943c
SR		 409};
410#endif /* __powerpc64__ */
10b35d99 411
2406f606 412#ifdef __powerpc64__
7c92943c
SR		 413#define CPU_FTRS_ALWAYS \
414 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 415 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
b3ebd1d8 416 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 417#else
7c92943c
SR		 418enum {
419 CPU_FTRS_ALWAYS =
10b35d99
KG		 420#if CLASSIC_PPC
421 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
422 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
423 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
424 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
425 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
426 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
427 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 428 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
429 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 430#else
431 CPU_FTRS_GENERIC_32 &
432#endif
10b35d99
KG		 433#ifdef CONFIG_8xx
434 CPU_FTRS_8XX &
435#endif
436#ifdef CONFIG_40x
437 CPU_FTRS_40X &
438#endif
439#ifdef CONFIG_44x
440 CPU_FTRS_44X &
441#endif
442#ifdef CONFIG_E200
443 CPU_FTRS_E200 &
444#endif
445#ifdef CONFIG_E500
446 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
447#endif
10b35d99
KG		 448 CPU_FTRS_POSSIBLE,
449};
7c92943c 450#endif /* __powerpc64__ */
10b35d99
KG		 451
452static inline int cpu_has_feature(unsigned long feature)
453{
454 return (CPU_FTRS_ALWAYS & feature) ||
455 (CPU_FTRS_POSSIBLE
10b35d99 456 & cur_cpu_spec->cpu_features
10b35d99
KG		 457 & feature);
458}
459
460#endif /* !__ASSEMBLY__ */
461
462#ifdef __ASSEMBLY__
463
7aeb7324 464#define BEGIN_FTR_SECTION_NESTED(label) label:
0909c8c2 465#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
7aeb7324 466#define END_FTR_SECTION_NESTED(msk, val, label) \
0909c8c2 467 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
7aeb7324 468#define END_FTR_SECTION(msk, val) \
0909c8c2 469 END_FTR_SECTION_NESTED(msk, val, 97)
7aeb7324 470
10b35d99
KG		 471#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
472#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
473#endif /* __ASSEMBLY__ */
474
475#endif /* __KERNEL__ */
476#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux kernel - Deliverables
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