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[POWERPC] Fix PowerPC 750CL and 750GX CPU features
[deliverable/linux.git] / include / asm-powerpc / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
3ddfbcf1 4#include <asm/asm-compat.h>
10b35d99
KG		 5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 17#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
80f15dc7 22#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 25#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 26#define PPC_FEATURE_PA6T 0x00000800
974a76f5
PM		 27#define PPC_FEATURE_HAS_DFP 0x00000400
28#define PPC_FEATURE_POWER6_EXT 0x00000200
10b35d99 29
fab5db97
PM		 30#define PPC_FEATURE_TRUE_LE 0x00000002
31#define PPC_FEATURE_PPC_LE 0x00000001
32
10b35d99
KG		 33#ifdef __KERNEL__
34#ifndef __ASSEMBLY__
35
36/* This structure can grow, it's real size is used by head.S code
37 * via the mkdefs mechanism.
38 */
39struct cpu_spec;
10b35d99 40
10b35d99 41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 42typedef void (*cpu_restore_t)(void);
10b35d99 43
32a33994 44enum powerpc_oprofile_type {
7a45fb19
AW		 45 PPC_OPROFILE_INVALID = 0,
46 PPC_OPROFILE_RS64 = 1,
47 PPC_OPROFILE_POWER4 = 2,
48 PPC_OPROFILE_G4 = 3,
49 PPC_OPROFILE_BOOKE = 4,
18f2190d 50 PPC_OPROFILE_CELL = 5,
32a33994
AB		 51};
52
1bd2e5ae
OJ		 53enum powerpc_pmc_type {
54 PPC_PMC_DEFAULT = 0,
55 PPC_PMC_IBM = 1,
56 PPC_PMC_PA6T = 2,
57};
58
10b35d99
KG		 59struct cpu_spec {
60 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
61 unsigned int pvr_mask;
62 unsigned int pvr_value;
63
64 char *cpu_name;
65 unsigned long cpu_features; /* Kernel features */
66 unsigned int cpu_user_features; /* Userland features */
67
68 /* cache line sizes */
69 unsigned int icache_bsize;
70 unsigned int dcache_bsize;
71
72 /* number of performance monitor counters */
73 unsigned int num_pmcs;
1bd2e5ae 74 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 75
76 /* this is called to initialize various CPU bits like L1 cache,
77 * BHT, SPD, etc... from head.S before branching to identify_machine
78 */
79 cpu_setup_t cpu_setup;
f39b7a55
OJ		 80 /* Used to restore cpu setup on secondary processors and at resume */
81 cpu_restore_t cpu_restore;
10b35d99
KG		 82
83 /* Used by oprofile userspace to select the right counters */
84 char *oprofile_cpu_type;
85
86 /* Processor specific oprofile operations */
32a33994 87 enum powerpc_oprofile_type oprofile_type;
80f15dc7 88
e78dbc80
MN		 89 /* Bit locations inside the mmcra change */
90 unsigned long oprofile_mmcra_sihv;
91 unsigned long oprofile_mmcra_sipr;
92
93 /* Bits to clear during an oprofile exception */
94 unsigned long oprofile_mmcra_clear;
95
80f15dc7
PM		 96 /* Name of processor class, for the ELF AT_PLATFORM entry */
97 char *platform;
10b35d99
KG		 98};
99
10b35d99 100extern struct cpu_spec *cur_cpu_spec;
10b35d99 101
42c4aaad
BH		 102extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
103
974a76f5 104extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 105extern void do_feature_fixups(unsigned long value, void *fixup_start,
106 void *fixup_end);
9b6b563c 107
10b35d99
KG		 108#endif /* __ASSEMBLY__ */
109
110/* CPU kernel features */
111
112/* Retain the 32b definitions all use bottom half of word */
113#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
114#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
115#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
116#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
117#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
118#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
119#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
120#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
121#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
122#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
123#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
124#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
125#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
126#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
127#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
128#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
129#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
130#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
131#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
132#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b 133#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 134#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
135#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
aa42c69c 136#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
10b35d99 137
3965f8c5
PM		 138/*
139 * Add the 64-bit processor unique features in the top half of the word;
140 * on 32-bit, make the names available but defined to be 0.
141 */
10b35d99 142#ifdef __powerpc64__
3965f8c5 143#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 144#else
3965f8c5 145#define LONG_ASM_CONST(x) 0
10b35d99
KG		 146#endif
147
3965f8c5
PM		 148#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
149#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
150#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
151#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
152#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
153#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
154#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
155#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
156#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
157#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
158#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
159#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
160#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9 161#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
974a76f5 162#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
4c198557 163#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
3965f8c5 164
10b35d99
KG		 165#ifndef __ASSEMBLY__
166
0470466d
SR		 167#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
168 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
169 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
10b35d99
KG		 170
171/* We only set the altivec features if the kernel was compiled with altivec
172 * support
173 */
174#ifdef CONFIG_ALTIVEC
175#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
176#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
177#else
178#define CPU_FTR_ALTIVEC_COMP 0
179#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
180#endif
181
182/* We need to mark all pages as being coherent if we're SMP or we
1775dbbc
KG		 183 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
184 * it for PCI "streaming/prefetch" to work properly.
10b35d99 185 */
1775dbbc
KG		 186#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
187 || defined(CONFIG_PPC_83xx)
10b35d99
KG		 188#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
189#else
190#define CPU_FTR_COMMON 0
191#endif
192
193/* The powersave features NAP & DOZE seems to confuse BDI when
194 debugging. So if a BDI is used, disable theses
195 */
196#ifndef CONFIG_BDI_SWITCH
197#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
198#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
199#else
200#define CPU_FTR_MAYBE_CAN_DOZE 0
201#define CPU_FTR_MAYBE_CAN_NAP 0
202#endif
203
204#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
205 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
206 !defined(CONFIG_BOOKE))
207
7c92943c
SR		 208#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
209#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
210 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 211 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
7c92943c 212#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
fab5db97
PM		 213 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
214 CPU_FTR_PPC_LE)
7c92943c
SR		 215#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
216 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97 217 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
7c92943c
SR		 218#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
219 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 220 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
221 CPU_FTR_PPC_LE)
7c92943c
SR		 222#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
223 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 224 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
225 CPU_FTR_PPC_LE)
a14c4508
JB		 226#define CPU_FTRS_750CL (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
227 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
228 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
229 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
7c92943c
SR		 230#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
231 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
232 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 233 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
7c92943c
SR		 234#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
235 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
236 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 237 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
7c92943c
SR		 238#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
239 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
240 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 241 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
a14c4508
JB		 242#define CPU_FTRS_750GX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
243 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
244 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 245 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
7c92943c
SR		 246#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
247 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
248 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
7c92943c
SR		 250#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
251 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
252 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 253 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
7c92943c
SR		 254#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
255 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
256 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 257 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 258#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
259 CPU_FTR_USE_TB | \
260 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
261 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
262 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 263 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 264#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
265 CPU_FTR_USE_TB | \
266 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
267 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 268 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 269#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
270 CPU_FTR_USE_TB | \
271 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
272 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 273 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 274#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
275 CPU_FTR_USE_TB | \
276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
277 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
278 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 279 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
7c92943c
SR		 280#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
281 CPU_FTR_USE_TB | \
282 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
283 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
284 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 285 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 286#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
287 CPU_FTR_USE_TB | \
288 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
289 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
290 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 291 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
7c92943c
SR		 292#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
293 CPU_FTR_USE_TB | \
294 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
295 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
296 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 297 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 298#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
299 CPU_FTR_USE_TB | \
300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
301 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
302 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 303 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 304#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
305 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
306#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
307 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
308#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
309 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
310 CPU_FTR_COMMON)
aa42c69c
KP		 311#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
312 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
313 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c92943c
SR		 314#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
315 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
7c92943c
SR		 316#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
317#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
318 CPU_FTR_NODSISRALIGN)
319#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
320 CPU_FTR_NODSISRALIGN)
321#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
322#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
323 CPU_FTR_NODSISRALIGN)
324#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
325 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
326#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 327
328/* 64-bit CPUs */
7c92943c 329#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
fab5db97 330 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
7c92943c
SR		 331#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
332 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
333 CPU_FTR_MMCRA | CPU_FTR_CTRL)
334#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000
OJ		 335 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
336 CPU_FTR_MMCRA)
7c92943c 337#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000 338 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 339 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
340#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000 341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 342 CPU_FTR_MMCRA | CPU_FTR_SMT | \
343 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
e78dbc80 344 CPU_FTR_PURR)
03054d51 345#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000 346 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 347 CPU_FTR_MMCRA | CPU_FTR_SMT | \
348 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
4c198557
AB		 349 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
350 CPU_FTR_DSCR)
7c92943c 351#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000 352 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 353 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
859deea9 354 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
b3ebd1d8
OJ		 355#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
356 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
357 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
358 CPU_FTR_PURR | CPU_FTR_REAL_LE)
7c92943c
SR		 359#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
360 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 361
2406f606 362#ifdef __powerpc64__
7c92943c
SR		 363#define CPU_FTRS_POSSIBLE \
364 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 365 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
b3ebd1d8 366 CPU_FTRS_CELL | CPU_FTRS_PA6T)
2406f606 367#else
7c92943c
SR		 368enum {
369 CPU_FTRS_POSSIBLE =
10b35d99
KG		 370#if CLASSIC_PPC
371 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
372 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
373 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
374 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
375 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
376 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
377 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 378 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
379 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 380#else
381 CPU_FTRS_GENERIC_32 |
382#endif
10b35d99
KG		 383#ifdef CONFIG_8xx
384 CPU_FTRS_8XX |
385#endif
386#ifdef CONFIG_40x
387 CPU_FTRS_40X |
388#endif
389#ifdef CONFIG_44x
390 CPU_FTRS_44X |
391#endif
392#ifdef CONFIG_E200
393 CPU_FTRS_E200 |
394#endif
395#ifdef CONFIG_E500
396 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
397#endif
10b35d99 398 0,
7c92943c
SR		 399};
400#endif /* __powerpc64__ */
10b35d99 401
2406f606 402#ifdef __powerpc64__
7c92943c
SR		 403#define CPU_FTRS_ALWAYS \
404 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 405 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
b3ebd1d8 406 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 407#else
7c92943c
SR		 408enum {
409 CPU_FTRS_ALWAYS =
10b35d99
KG		 410#if CLASSIC_PPC
411 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
412 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
413 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
414 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
415 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
416 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
417 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 418 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
419 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 420#else
421 CPU_FTRS_GENERIC_32 &
422#endif
10b35d99
KG		 423#ifdef CONFIG_8xx
424 CPU_FTRS_8XX &
425#endif
426#ifdef CONFIG_40x
427 CPU_FTRS_40X &
428#endif
429#ifdef CONFIG_44x
430 CPU_FTRS_44X &
431#endif
432#ifdef CONFIG_E200
433 CPU_FTRS_E200 &
434#endif
435#ifdef CONFIG_E500
436 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
437#endif
10b35d99
KG		 438 CPU_FTRS_POSSIBLE,
439};
7c92943c 440#endif /* __powerpc64__ */
10b35d99
KG		 441
442static inline int cpu_has_feature(unsigned long feature)
443{
444 return (CPU_FTRS_ALWAYS & feature) ||
445 (CPU_FTRS_POSSIBLE
10b35d99 446 & cur_cpu_spec->cpu_features
10b35d99
KG		 447 & feature);
448}
449
450#endif /* !__ASSEMBLY__ */
451
452#ifdef __ASSEMBLY__
453
7aeb7324 454#define BEGIN_FTR_SECTION_NESTED(label) label:
0909c8c2 455#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
7aeb7324 456#define END_FTR_SECTION_NESTED(msk, val, label) \
0909c8c2 457 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
7aeb7324 458#define END_FTR_SECTION(msk, val) \
0909c8c2 459 END_FTR_SECTION_NESTED(msk, val, 97)
7aeb7324 460
10b35d99
KG		 461#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
462#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
463#endif /* __ASSEMBLY__ */
464
465#endif /* __KERNEL__ */
466#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux kernel - Deliverables
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