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4c75a6f4 BH |
1 | /* |
2 | * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp. | |
3 | * <benh@kernel.crashing.org> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
13 | * the GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #ifndef _ASM_POWERPC_DCR_NATIVE_H | |
21 | #define _ASM_POWERPC_DCR_NATIVE_H | |
22 | #ifdef __KERNEL__ | |
45d8e7aa | 23 | #ifndef __ASSEMBLY__ |
4c75a6f4 | 24 | |
0e6140a5 BH |
25 | #include <linux/spinlock.h> |
26 | ||
0b94a1ee ME |
27 | typedef struct { |
28 | unsigned int base; | |
29 | } dcr_host_t; | |
4c75a6f4 BH |
30 | |
31 | #define DCR_MAP_OK(host) (1) | |
32 | ||
0b94a1ee | 33 | #define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) }) |
cdbd3865 | 34 | #define dcr_unmap(host, dcr_c) do {} while (0) |
83f34df4 ME |
35 | #define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base) |
36 | #define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base, value) | |
4c75a6f4 | 37 | |
45d8e7aa KG |
38 | /* Device Control Registers */ |
39 | void __mtdcr(int reg, unsigned int val); | |
40 | unsigned int __mfdcr(int reg); | |
41 | #define mfdcr(rn) \ | |
42 | ({unsigned int rval; \ | |
43 | if (__builtin_constant_p(rn)) \ | |
44 | asm volatile("mfdcr %0," __stringify(rn) \ | |
45 | : "=r" (rval)); \ | |
46 | else \ | |
47 | rval = __mfdcr(rn); \ | |
48 | rval;}) | |
49 | ||
50 | #define mtdcr(rn, v) \ | |
51 | do { \ | |
52 | if (__builtin_constant_p(rn)) \ | |
53 | asm volatile("mtdcr " __stringify(rn) ",%0" \ | |
54 | : : "r" (v)); \ | |
55 | else \ | |
56 | __mtdcr(rn, v); \ | |
57 | } while (0) | |
58 | ||
59 | /* R/W of indirect DCRs make use of standard naming conventions for DCRs */ | |
0e6140a5 BH |
60 | extern spinlock_t dcr_ind_lock; |
61 | ||
e8318d98 VB |
62 | static inline unsigned __mfdcri(int base_addr, int base_data, int reg) |
63 | { | |
64 | unsigned long flags; | |
65 | unsigned int val; | |
45d8e7aa | 66 | |
e8318d98 VB |
67 | spin_lock_irqsave(&dcr_ind_lock, flags); |
68 | __mtdcr(base_addr, reg); | |
69 | val = __mfdcr(base_data); | |
70 | spin_unlock_irqrestore(&dcr_ind_lock, flags); | |
71 | return val; | |
72 | } | |
73 | ||
74 | static inline void __mtdcri(int base_addr, int base_data, int reg, | |
75 | unsigned val) | |
76 | { | |
77 | unsigned long flags; | |
78 | ||
79 | spin_lock_irqsave(&dcr_ind_lock, flags); | |
80 | __mtdcr(base_addr, reg); | |
81 | __mtdcr(base_data, val); | |
82 | spin_unlock_irqrestore(&dcr_ind_lock, flags); | |
83 | } | |
84 | ||
85 | #define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \ | |
86 | DCRN_ ## base ## _CONFIG_DATA, \ | |
87 | reg) | |
88 | ||
89 | #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \ | |
90 | DCRN_ ## base ## _CONFIG_DATA, \ | |
91 | reg, data) | |
4c75a6f4 | 92 | |
45d8e7aa | 93 | #endif /* __ASSEMBLY__ */ |
4c75a6f4 BH |
94 | #endif /* __KERNEL__ */ |
95 | #endif /* _ASM_POWERPC_DCR_NATIVE_H */ |