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0e6140a5 BH |
1 | /* |
2 | * Common DCR / SDR / CPR register definitions used on various IBM/AMCC | |
3 | * 4xx processors | |
4 | * | |
5 | * Copyright 2007 Benjamin Herrenschmidt, IBM Corp | |
6 | * <benh@kernel.crashing.org> | |
7 | * | |
8 | * Mostly lifted from asm-ppc/ibm4xx.h by | |
9 | * | |
10 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | |
11 | * | |
12 | */ | |
13 | ||
14 | #ifndef __DCR_REGS_H__ | |
15 | #define __DCR_REGS_H__ | |
16 | ||
17 | /* | |
18 | * Most DCRs used for controlling devices such as the MAL, DMA engine, | |
19 | * etc... are obtained for the device tree. | |
20 | * | |
21 | * The definitions in this files are fixed DCRs and indirect DCRs that | |
22 | * are commonly used outside of specific drivers or refer to core | |
23 | * common registers that may occasionally have to be tweaked outside | |
24 | * of the driver main register set | |
25 | */ | |
26 | ||
27 | /* CPRs (440GX and 440SP/440SPe) */ | |
28 | #define DCRN_CPR0_CONFIG_ADDR 0xc | |
29 | #define DCRN_CPR0_CONFIG_DATA 0xd | |
30 | ||
31 | /* SDRs (440GX and 440SP/440SPe) */ | |
32 | #define DCRN_SDR0_CONFIG_ADDR 0xe | |
33 | #define DCRN_SDR0_CONFIG_DATA 0xf | |
34 | ||
35 | #define SDR0_PFC0 0x4100 | |
36 | #define SDR0_PFC1 0x4101 | |
37 | #define SDR0_PFC1_EPS 0x1c00000 | |
38 | #define SDR0_PFC1_EPS_SHIFT 22 | |
39 | #define SDR0_PFC1_RMII 0x02000000 | |
40 | #define SDR0_MFR 0x4300 | |
41 | #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ | |
42 | #define SDR0_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ | |
43 | #define SDR0_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ | |
44 | #define SDR0_MFR_ECS 0x08000000 /* EMAC int clk */ | |
45 | #define SDR0_MFR_T0TXFL 0x00080000 | |
46 | #define SDR0_MFR_T0TXFH 0x00040000 | |
47 | #define SDR0_MFR_T1TXFL 0x00020000 | |
48 | #define SDR0_MFR_T1TXFH 0x00010000 | |
49 | #define SDR0_MFR_E0TXFL 0x00008000 | |
50 | #define SDR0_MFR_E0TXFH 0x00004000 | |
51 | #define SDR0_MFR_E0RXFL 0x00002000 | |
52 | #define SDR0_MFR_E0RXFH 0x00001000 | |
53 | #define SDR0_MFR_E1TXFL 0x00000800 | |
54 | #define SDR0_MFR_E1TXFH 0x00000400 | |
55 | #define SDR0_MFR_E1RXFL 0x00000200 | |
56 | #define SDR0_MFR_E1RXFH 0x00000100 | |
57 | #define SDR0_MFR_E2TXFL 0x00000080 | |
58 | #define SDR0_MFR_E2TXFH 0x00000040 | |
59 | #define SDR0_MFR_E2RXFL 0x00000020 | |
60 | #define SDR0_MFR_E2RXFH 0x00000010 | |
61 | #define SDR0_MFR_E3TXFL 0x00000008 | |
62 | #define SDR0_MFR_E3TXFH 0x00000004 | |
63 | #define SDR0_MFR_E3RXFL 0x00000002 | |
64 | #define SDR0_MFR_E3RXFH 0x00000001 | |
65 | #define SDR0_UART0 0x0120 | |
66 | #define SDR0_UART1 0x0121 | |
67 | #define SDR0_UART2 0x0122 | |
68 | #define SDR0_UART3 0x0123 | |
69 | #define SDR0_CUST0 0x4000 | |
70 | ||
71 | #endif /* __DCR_REGS_H__ */ |