[deliverable/linux.git] / include / asm-powerpc / dma-mapping.h

/*
 * Copyright (C) 2004 IBM
 *
 * Implements the generic device dma API for powerpc.
 * the pci and vio busses
 */
#ifndef _ASM_DMA_MAPPING_H
#define _ASM_DMA_MAPPING_H
#ifdef __KERNEL__

#include <linux/types.h>
#include <linux/cache.h>
/* need struct page definitions */
#include <linux/mm.h>
#include <linux/scatterlist.h>
#include <asm/io.h>

#define DMA_ERROR_CODE		(~(dma_addr_t)0x0)

#ifdef CONFIG_NOT_COHERENT_CACHE
/*
 * DMA-consistent mapping functions for PowerPCs that don't support
 * cache snooping.  These allocate/free a region of uncached mapped
 * memory space for use with DMA devices.  Alternatively, you could
 * allocate the space "normally" and use the cache management functions
 * to ensure it is consistent.
 */
extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
extern void __dma_free_coherent(size_t size, void *vaddr);
extern void __dma_sync(void *vaddr, size_t size, int direction);
extern void __dma_sync_page(struct page *page, unsigned long offset,
				 size_t size, int direction);

#else /* ! CONFIG_NOT_COHERENT_CACHE */
/*
 * Cache coherent cores.
 */

#define __dma_alloc_coherent(gfp, size, handle)	NULL
#define __dma_free_coherent(size, addr)		((void)0)
#define __dma_sync(addr, size, rw)		((void)0)
#define __dma_sync_page(pg, off, sz, rw)	((void)0)

#endif /* ! CONFIG_NOT_COHERENT_CACHE */

#ifdef CONFIG_PPC64
/*
 * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
 */
struct dma_mapping_ops {
	void *		(*alloc_coherent)(struct device *dev, size_t size,
				dma_addr_t *dma_handle, gfp_t flag);
	void		(*free_coherent)(struct device *dev, size_t size,
				void *vaddr, dma_addr_t dma_handle);
	dma_addr_t	(*map_single)(struct device *dev, void *ptr,
				size_t size, enum dma_data_direction direction);
	void		(*unmap_single)(struct device *dev, dma_addr_t dma_addr,
				size_t size, enum dma_data_direction direction);
	int		(*map_sg)(struct device *dev, struct scatterlist *sg,
				int nents, enum dma_data_direction direction);
	void		(*unmap_sg)(struct device *dev, struct scatterlist *sg,
				int nents, enum dma_data_direction direction);
	int		(*dma_supported)(struct device *dev, u64 mask);
	int		(*set_dma_mask)(struct device *dev, u64 dma_mask);
};

static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
{
	/* We don't handle the NULL dev case for ISA for now. We could
	 * do it via an out of line call but it is not needed for now. The
	 * only ISA DMA device we support is the floppy and we have a hack
	 * in the floppy driver directly to get a device for us.
	 */
	if (unlikely(dev == NULL || dev->archdata.dma_ops == NULL))
		return NULL;
	return dev->archdata.dma_ops;
}

static inline int dma_supported(struct device *dev, u64 mask)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	if (unlikely(dma_ops == NULL))
		return 0;
	if (dma_ops->dma_supported == NULL)
		return 1;
	return dma_ops->dma_supported(dev, mask);
}

/* We have our own implementation of pci_set_dma_mask() */
#define HAVE_ARCH_PCI_SET_DMA_MASK

static inline int dma_set_mask(struct device *dev, u64 dma_mask)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	if (unlikely(dma_ops == NULL))
		return -EIO;
	if (dma_ops->set_dma_mask != NULL)
		return dma_ops->set_dma_mask(dev, dma_mask);
	if (!dev->dma_mask || !dma_supported(dev, dma_mask))
		return -EIO;
	*dev->dma_mask = dma_mask;
	return 0;
}

static inline void *dma_alloc_coherent(struct device *dev, size_t size,
				       dma_addr_t *dma_handle, gfp_t flag)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	BUG_ON(!dma_ops);
	return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
}

static inline void dma_free_coherent(struct device *dev, size_t size,
				     void *cpu_addr, dma_addr_t dma_handle)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	BUG_ON(!dma_ops);
	dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
}

static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
					size_t size,
					enum dma_data_direction direction)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	BUG_ON(!dma_ops);
	return dma_ops->map_single(dev, cpu_addr, size, direction);
}

static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
				    size_t size,
				    enum dma_data_direction direction)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	BUG_ON(!dma_ops);
	dma_ops->unmap_single(dev, dma_addr, size, direction);
}

static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
				      unsigned long offset, size_t size,
				      enum dma_data_direction direction)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	BUG_ON(!dma_ops);
	return dma_ops->map_single(dev, page_address(page) + offset, size,
			direction);
}

static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
				  size_t size,
				  enum dma_data_direction direction)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	BUG_ON(!dma_ops);
	dma_ops->unmap_single(dev, dma_address, size, direction);
}

static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
			     int nents, enum dma_data_direction direction)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	BUG_ON(!dma_ops);
	return dma_ops->map_sg(dev, sg, nents, direction);
}

static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
				int nhwentries,
				enum dma_data_direction direction)
{
	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);

	BUG_ON(!dma_ops);
	dma_ops->unmap_sg(dev, sg, nhwentries, direction);
}


/*
 * Available generic sets of operations
 */
extern struct dma_mapping_ops dma_iommu_ops;
extern struct dma_mapping_ops dma_direct_ops;

#else /* CONFIG_PPC64 */

#define dma_supported(dev, mask)	(1)

static inline int dma_set_mask(struct device *dev, u64 dma_mask)
{
	if (!dev->dma_mask || !dma_supported(dev, mask))
		return -EIO;

	*dev->dma_mask = dma_mask;

	return 0;
}

static inline void *dma_alloc_coherent(struct device *dev, size_t size,
				       dma_addr_t * dma_handle,
				       gfp_t gfp)
{
#ifdef CONFIG_NOT_COHERENT_CACHE
	return __dma_alloc_coherent(size, dma_handle, gfp);
#else
	void *ret;
	/* ignore region specifiers */
	gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);

	if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
		gfp |= GFP_DMA;

	ret = (void *)__get_free_pages(gfp, get_order(size));

	if (ret != NULL) {
		memset(ret, 0, size);
		*dma_handle = virt_to_bus(ret);
	}

	return ret;
#endif
}

static inline void
dma_free_coherent(struct device *dev, size_t size, void *vaddr,
		  dma_addr_t dma_handle)
{
#ifdef CONFIG_NOT_COHERENT_CACHE
	__dma_free_coherent(size, vaddr);
#else
	free_pages((unsigned long)vaddr, get_order(size));
#endif
}

static inline dma_addr_t
dma_map_single(struct device *dev, void *ptr, size_t size,
	       enum dma_data_direction direction)
{
	BUG_ON(direction == DMA_NONE);

	__dma_sync(ptr, size, direction);

	return virt_to_bus(ptr);
}

static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
				    size_t size,
				    enum dma_data_direction direction)
{
	/* We do nothing. */
}

static inline dma_addr_t
dma_map_page(struct device *dev, struct page *page,
	     unsigned long offset, size_t size,
	     enum dma_data_direction direction)
{
	BUG_ON(direction == DMA_NONE);

	__dma_sync_page(page, offset, size, direction);

	return page_to_bus(page) + offset;
}

static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
				  size_t size,
				  enum dma_data_direction direction)
{
	/* We do nothing. */
}

static inline int
dma_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
	   enum dma_data_direction direction)
{
	struct scatterlist *sg;
	int i;

	BUG_ON(direction == DMA_NONE);

	for_each_sg(sgl, sg, nents, i) {
		BUG_ON(!sg_page(sg));
		__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
		sg->dma_address = page_to_bus(sg_page(sg)) + sg->offset;
	}

	return nents;
}

static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
				int nhwentries,
				enum dma_data_direction direction)
{
	/* We don't do anything here. */
}

#endif /* CONFIG_PPC64 */

static inline void dma_sync_single_for_cpu(struct device *dev,
		dma_addr_t dma_handle, size_t size,
		enum dma_data_direction direction)
{
	BUG_ON(direction == DMA_NONE);
	__dma_sync(bus_to_virt(dma_handle), size, direction);
}

static inline void dma_sync_single_for_device(struct device *dev,
		dma_addr_t dma_handle, size_t size,
		enum dma_data_direction direction)
{
	BUG_ON(direction == DMA_NONE);
	__dma_sync(bus_to_virt(dma_handle), size, direction);
}

static inline void dma_sync_sg_for_cpu(struct device *dev,
		struct scatterlist *sgl, int nents,
		enum dma_data_direction direction)
{
	struct scatterlist *sg;
	int i;

	BUG_ON(direction == DMA_NONE);

	for_each_sg(sgl, sg, nents, i)
		__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
}

static inline void dma_sync_sg_for_device(struct device *dev,
		struct scatterlist *sgl, int nents,
		enum dma_data_direction direction)
{
	struct scatterlist *sg;
	int i;

	BUG_ON(direction == DMA_NONE);

	for_each_sg(sgl, sg, nents, i)
		__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
}

static inline int dma_mapping_error(dma_addr_t dma_addr)
{
#ifdef CONFIG_PPC64
	return (dma_addr == DMA_ERROR_CODE);
#else
	return 0;
#endif
}

#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#ifdef CONFIG_NOT_COHERENT_CACHE
#define dma_is_consistent(d, h)	(0)
#else
#define dma_is_consistent(d, h)	(1)
#endif

static inline int dma_get_cache_alignment(void)
{
#ifdef CONFIG_PPC64
	/* no easy way to get cache size on all processors, so return
	 * the maximum possible, to be safe */
	return (1 << INTERNODE_CACHE_SHIFT);
#else
	/*
	 * Each processor family will define its own L1_CACHE_SHIFT,
	 * L1_CACHE_BYTES wraps to this, so this is always safe.
	 */
	return L1_CACHE_BYTES;
#endif
}

static inline void dma_sync_single_range_for_cpu(struct device *dev,
		dma_addr_t dma_handle, unsigned long offset, size_t size,
		enum dma_data_direction direction)
{
	/* just sync everything for now */
	dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
}

static inline void dma_sync_single_range_for_device(struct device *dev,
		dma_addr_t dma_handle, unsigned long offset, size_t size,
		enum dma_data_direction direction)
{
	/* just sync everything for now */
	dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
}

static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
		enum dma_data_direction direction)
{
	BUG_ON(direction == DMA_NONE);
	__dma_sync(vaddr, size, (int)direction);
}

#endif /* __KERNEL__ */
#endif	/* _ASM_DMA_MAPPING_H */
Commit	Line	Data
1da177e4	1	/*
78b09735 SR	2	* Copyright (C) 2004 IBM
	3	*
	4	* Implements the generic device dma API for powerpc.
	5	* the pci and vio busses
1da177e4	6	*/
78b09735 SR	7	#ifndef _ASM_DMA_MAPPING_H
78b09735 SR	8	#define _ASM_DMA_MAPPING_H
33ff910f AB	9	#ifdef __KERNEL__
	10
	11	#include <linux/types.h>
	12	#include <linux/cache.h>
	13	/* need struct page definitions */
	14	#include <linux/mm.h>
	15	#include <linux/scatterlist.h>
	16	#include <asm/io.h>
	17
	18	#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
	19
	20	#ifdef CONFIG_NOT_COHERENT_CACHE
	21	/*
	22	* DMA-consistent mapping functions for PowerPCs that don't support
	23	* cache snooping. These allocate/free a region of uncached mapped
	24	* memory space for use with DMA devices. Alternatively, you could
	25	* allocate the space "normally" and use the cache management functions
	26	* to ensure it is consistent.
	27	*/
	28	extern void __dma_alloc_coherent(size_t size, dma_addr_t handle, gfp_t gfp);
	29	extern void __dma_free_coherent(size_t size, void *vaddr);
	30	extern void __dma_sync(void *vaddr, size_t size, int direction);
	31	extern void __dma_sync_page(struct page *page, unsigned long offset,
	32	size_t size, int direction);
	33
	34	#else /* ! CONFIG_NOT_COHERENT_CACHE */
	35	/*
	36	* Cache coherent cores.
	37	*/
	38
	39	#define __dma_alloc_coherent(gfp, size, handle) NULL
	40	#define __dma_free_coherent(size, addr) ((void)0)
	41	#define __dma_sync(addr, size, rw) ((void)0)
	42	#define __dma_sync_page(pg, off, sz, rw) ((void)0)
	43
	44	#endif /* ! CONFIG_NOT_COHERENT_CACHE */
	45
	46	#ifdef CONFIG_PPC64
	47	/*
	48	* DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
	49	*/
	50	struct dma_mapping_ops {
	51	void * (alloc_coherent)(struct device dev, size_t size,
	52	dma_addr_t *dma_handle, gfp_t flag);
	53	void (free_coherent)(struct device dev, size_t size,
	54	void *vaddr, dma_addr_t dma_handle);
	55	dma_addr_t (map_single)(struct device dev, void *ptr,
	56	size_t size, enum dma_data_direction direction);
	57	void (unmap_single)(struct device dev, dma_addr_t dma_addr,
	58	size_t size, enum dma_data_direction direction);
	59	int (map_sg)(struct device dev, struct scatterlist *sg,
	60	int nents, enum dma_data_direction direction);
	61	void (unmap_sg)(struct device dev, struct scatterlist *sg,
	62	int nents, enum dma_data_direction direction);
	63	int (dma_supported)(struct device dev, u64 mask);
	64	int (set_dma_mask)(struct device dev, u64 dma_mask);
	65	};
	66
	67	static inline struct dma_mapping_ops get_dma_ops(struct device dev)
	68	{
	69	/* We don't handle the NULL dev case for ISA for now. We could
	70	* do it via an out of line call but it is not needed for now. The
	71	* only ISA DMA device we support is the floppy and we have a hack
	72	* in the floppy driver directly to get a device for us.
73	*/
74	if (unlikely(dev == NULL \|\| dev->archdata.dma_ops == NULL))
75	return NULL;
76	return dev->archdata.dma_ops;
77	}
78
79	static inline int dma_supported(struct device *dev, u64 mask)
80	{
81	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
82
83	if (unlikely(dma_ops == NULL))
84	return 0;
85	if (dma_ops->dma_supported == NULL)
86	return 1;
87	return dma_ops->dma_supported(dev, mask);
88	}
89
84631f37 ME	90	/* We have our own implementation of pci_set_dma_mask() */
	91	#define HAVE_ARCH_PCI_SET_DMA_MASK
	92
33ff910f AB	93	static inline int dma_set_mask(struct device *dev, u64 dma_mask)
	94	{
	95	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	96
	97	if (unlikely(dma_ops == NULL))
	98	return -EIO;
	99	if (dma_ops->set_dma_mask != NULL)
	100	return dma_ops->set_dma_mask(dev, dma_mask);
	101	if (!dev->dma_mask \|\| !dma_supported(dev, dma_mask))
	102	return -EIO;
	103	*dev->dma_mask = dma_mask;
	104	return 0;
	105	}
	106
	107	static inline void dma_alloc_coherent(struct device dev, size_t size,
	108	dma_addr_t *dma_handle, gfp_t flag)
	109	{
	110	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	111
	112	BUG_ON(!dma_ops);
	113	return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
	114	}
	115
	116	static inline void dma_free_coherent(struct device *dev, size_t size,
	117	void *cpu_addr, dma_addr_t dma_handle)
	118	{
	119	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	120
	121	BUG_ON(!dma_ops);
	122	dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
	123	}
	124
	125	static inline dma_addr_t dma_map_single(struct device dev, void cpu_addr,
	126	size_t size,
	127	enum dma_data_direction direction)
	128	{
	129	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	130
	131	BUG_ON(!dma_ops);
	132	return dma_ops->map_single(dev, cpu_addr, size, direction);
	133	}
	134
	135	static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
	136	size_t size,
	137	enum dma_data_direction direction)
	138	{
	139	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	140
	141	BUG_ON(!dma_ops);
	142	dma_ops->unmap_single(dev, dma_addr, size, direction);
	143	}
	144
	145	static inline dma_addr_t dma_map_page(struct device dev, struct page page,
	146	unsigned long offset, size_t size,
	147	enum dma_data_direction direction)
	148	{
	149	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	150
	151	BUG_ON(!dma_ops);
	152	return dma_ops->map_single(dev, page_address(page) + offset, size,
	153	direction);
	154	}
12d04eef BH	155
	156	static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
	157	size_t size,
	158	enum dma_data_direction direction)
	159	{
	160	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	161
	162	BUG_ON(!dma_ops);
	163	dma_ops->unmap_single(dev, dma_address, size, direction);
	164	}
	165
	166	static inline int dma_map_sg(struct device dev, struct scatterlist sg,
	167	int nents, enum dma_data_direction direction)
	168	{
	169	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	170
	171	BUG_ON(!dma_ops);
	172	return dma_ops->map_sg(dev, sg, nents, direction);
	173	}
	174
	175	static inline void dma_unmap_sg(struct device dev, struct scatterlist sg,
	176	int nhwentries,
	177	enum dma_data_direction direction)
	178	{
	179	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
	180
	181	BUG_ON(!dma_ops);
	182	dma_ops->unmap_sg(dev, sg, nhwentries, direction);
	183	}
78b09735	184
12d04eef BH	185
	186	/*
	187	* Available generic sets of operations
	188	*/
	189	extern struct dma_mapping_ops dma_iommu_ops;
	190	extern struct dma_mapping_ops dma_direct_ops;
78b09735 SR	191
	192	#else /* CONFIG_PPC64 */
	193
1da177e4 LT	194	#define dma_supported(dev, mask) (1)
	195
	196	static inline int dma_set_mask(struct device *dev, u64 dma_mask)
	197	{
	198	if (!dev->dma_mask \|\| !dma_supported(dev, mask))
	199	return -EIO;
	200
	201	*dev->dma_mask = dma_mask;
	202
	203	return 0;
	204	}
	205
	206	static inline void dma_alloc_coherent(struct device dev, size_t size,
d27477c2	207	dma_addr_t * dma_handle,
dd0fc66f	208	gfp_t gfp)
1da177e4 LT	209	{
	210	#ifdef CONFIG_NOT_COHERENT_CACHE
	211	return __dma_alloc_coherent(size, dma_handle, gfp);
	212	#else
	213	void *ret;
	214	/* ignore region specifiers */
	215	gfp &= ~(__GFP_DMA \| __GFP_HIGHMEM);
	216
	217	if (dev == NULL \|\| dev->coherent_dma_mask < 0xffffffff)
	218	gfp \|= GFP_DMA;
	219
	220	ret = (void *)__get_free_pages(gfp, get_order(size));
	221
	222	if (ret != NULL) {
	223	memset(ret, 0, size);
	224	*dma_handle = virt_to_bus(ret);
	225	}
	226
	227	return ret;
	228	#endif
	229	}
	230
	231	static inline void
	232	dma_free_coherent(struct device dev, size_t size, void vaddr,
	233	dma_addr_t dma_handle)
	234	{
	235	#ifdef CONFIG_NOT_COHERENT_CACHE
	236	__dma_free_coherent(size, vaddr);
	237	#else
	238	free_pages((unsigned long)vaddr, get_order(size));
	239	#endif
	240	}
	241
	242	static inline dma_addr_t
	243	dma_map_single(struct device dev, void ptr, size_t size,
	244	enum dma_data_direction direction)
	245	{
	246	BUG_ON(direction == DMA_NONE);
	247
	248	__dma_sync(ptr, size, direction);
	249
	250	return virt_to_bus(ptr);
	251	}
	252
f774216d SB	253	static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
	254	size_t size,
	255	enum dma_data_direction direction)
	256	{
	257	/* We do nothing. */
	258	}
1da177e4 LT	259
	260	static inline dma_addr_t
	261	dma_map_page(struct device dev, struct page page,
	262	unsigned long offset, size_t size,
	263	enum dma_data_direction direction)
	264	{
	265	BUG_ON(direction == DMA_NONE);
	266
	267	__dma_sync_page(page, offset, size, direction);
	268
9f6a3d08	269	return page_to_bus(page) + offset;
1da177e4 LT	270	}
1da177e4 LT	271
f774216d SB	272	static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
	273	size_t size,
	274	enum dma_data_direction direction)
	275	{
	276	/* We do nothing. */
	277	}
1da177e4 LT	278
1da177e4 LT	279	static inline int
78bdc310	280	dma_map_sg(struct device dev, struct scatterlist sgl, int nents,
1da177e4 LT	281	enum dma_data_direction direction)
1da177e4 LT	282	{
78bdc310	283	struct scatterlist *sg;
1da177e4 LT	284	int i;
	285
	286	BUG_ON(direction == DMA_NONE);
	287
78bdc310	288	for_each_sg(sgl, sg, nents, i) {
5edadbd0 OJ	289	BUG_ON(!sg_page(sg));
	290	__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
	291	sg->dma_address = page_to_bus(sg_page(sg)) + sg->offset;
1da177e4 LT	292	}
	293
	294	return nents;
	295	}
	296
f774216d SB	297	static inline void dma_unmap_sg(struct device dev, struct scatterlist sg,
	298	int nhwentries,
	299	enum dma_data_direction direction)
	300	{
	301	/* We don't do anything here. */
	302	}
1da177e4	303
78b09735 SR	304	#endif /* CONFIG_PPC64 */
	305
	306	static inline void dma_sync_single_for_cpu(struct device *dev,
	307	dma_addr_t dma_handle, size_t size,
	308	enum dma_data_direction direction)
1da177e4 LT	309	{
1da177e4 LT	310	BUG_ON(direction == DMA_NONE);
1da177e4 LT	311	__dma_sync(bus_to_virt(dma_handle), size, direction);
	312	}
	313
78b09735 SR	314	static inline void dma_sync_single_for_device(struct device *dev,
	315	dma_addr_t dma_handle, size_t size,
	316	enum dma_data_direction direction)
1da177e4 LT	317	{
1da177e4 LT	318	BUG_ON(direction == DMA_NONE);
1da177e4 LT	319	__dma_sync(bus_to_virt(dma_handle), size, direction);
	320	}
	321
78b09735	322	static inline void dma_sync_sg_for_cpu(struct device *dev,
78bdc310	323	struct scatterlist *sgl, int nents,
78b09735	324	enum dma_data_direction direction)
1da177e4	325	{
78bdc310	326	struct scatterlist *sg;
1da177e4 LT	327	int i;
	328
	329	BUG_ON(direction == DMA_NONE);
	330
78bdc310	331	for_each_sg(sgl, sg, nents, i)
5edadbd0	332	__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
1da177e4 LT	333	}
1da177e4 LT	334
78b09735	335	static inline void dma_sync_sg_for_device(struct device *dev,
78bdc310	336	struct scatterlist *sgl, int nents,
78b09735	337	enum dma_data_direction direction)
1da177e4	338	{
78bdc310	339	struct scatterlist *sg;
1da177e4 LT	340	int i;
	341
	342	BUG_ON(direction == DMA_NONE);
	343
78bdc310	344	for_each_sg(sgl, sg, nents, i)
5edadbd0	345	__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
1da177e4 LT	346	}
1da177e4 LT	347
78b09735 SR	348	static inline int dma_mapping_error(dma_addr_t dma_addr)
	349	{
	350	#ifdef CONFIG_PPC64
	351	return (dma_addr == DMA_ERROR_CODE);
	352	#else
	353	return 0;
	354	#endif
	355	}
	356
1da177e4 LT	357	#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
	358	#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
	359	#ifdef CONFIG_NOT_COHERENT_CACHE
f67637ee	360	#define dma_is_consistent(d, h) (0)
1da177e4	361	#else
f67637ee	362	#define dma_is_consistent(d, h) (1)
1da177e4 LT	363	#endif
	364
	365	static inline int dma_get_cache_alignment(void)
	366	{
78b09735 SR	367	#ifdef CONFIG_PPC64
	368	/* no easy way to get cache size on all processors, so return
	369	* the maximum possible, to be safe */
1fd73c6b	370	return (1 << INTERNODE_CACHE_SHIFT);
78b09735	371	#else
1da177e4 LT	372	/*
	373	* Each processor family will define its own L1_CACHE_SHIFT,
	374	* L1_CACHE_BYTES wraps to this, so this is always safe.
	375	*/
	376	return L1_CACHE_BYTES;
78b09735	377	#endif
1da177e4 LT	378	}
1da177e4 LT	379
78b09735 SR	380	static inline void dma_sync_single_range_for_cpu(struct device *dev,
	381	dma_addr_t dma_handle, unsigned long offset, size_t size,
	382	enum dma_data_direction direction)
1da177e4 LT	383	{
	384	/* just sync everything for now */
	385	dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
	386	}
	387
78b09735 SR	388	static inline void dma_sync_single_range_for_device(struct device *dev,
	389	dma_addr_t dma_handle, unsigned long offset, size_t size,
	390	enum dma_data_direction direction)
1da177e4 LT	391	{
	392	/* just sync everything for now */
	393	dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
	394	}
	395
d3fa72e4	396	static inline void dma_cache_sync(struct device dev, void vaddr, size_t size,
78b09735	397	enum dma_data_direction direction)
1da177e4	398	{
78b09735	399	BUG_ON(direction == DMA_NONE);
1da177e4 LT	400	__dma_sync(vaddr, size, (int)direction);
	401	}
	402
88ced031	403	#endif /* __KERNEL__ */
78b09735	404	#endif /* _ASM_DMA_MAPPING_H */