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sh: Initial ELF FDPIC support.
[deliverable/linux.git] / include / asm-powerpc / elf.h
CommitLineData
a99eb2ef
BB		 1#ifndef _ASM_POWERPC_ELF_H
2#define _ASM_POWERPC_ELF_H
1da177e4 3
88ced031 4#ifdef __KERNEL__
8c65b4a6 5#include <linux/sched.h> /* for task_struct */
dd02ec3a
DW		 6#include <asm/page.h>
7#include <asm/string.h>
88ced031
AB		 8#endif
9
1da177e4
LT		 10#include <asm/types.h>
11#include <asm/ptrace.h>
12#include <asm/cputable.h>
36d57ac4 13#include <asm/auxvec.h>
1da177e4
LT		 14
15/* PowerPC relocations defined by the ABIs */
16#define R_PPC_NONE 0
17#define R_PPC_ADDR32 1 /* 32bit absolute address */
18#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
19#define R_PPC_ADDR16 3 /* 16bit absolute address */
20#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
21#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
22#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
23#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
24#define R_PPC_ADDR14_BRTAKEN 8
25#define R_PPC_ADDR14_BRNTAKEN 9
26#define R_PPC_REL24 10 /* PC relative 26 bit */
27#define R_PPC_REL14 11 /* PC relative 16 bit */
28#define R_PPC_REL14_BRTAKEN 12
29#define R_PPC_REL14_BRNTAKEN 13
30#define R_PPC_GOT16 14
31#define R_PPC_GOT16_LO 15
32#define R_PPC_GOT16_HI 16
33#define R_PPC_GOT16_HA 17
34#define R_PPC_PLTREL24 18
35#define R_PPC_COPY 19
36#define R_PPC_GLOB_DAT 20
37#define R_PPC_JMP_SLOT 21
38#define R_PPC_RELATIVE 22
39#define R_PPC_LOCAL24PC 23
40#define R_PPC_UADDR32 24
41#define R_PPC_UADDR16 25
42#define R_PPC_REL32 26
43#define R_PPC_PLT32 27
44#define R_PPC_PLTREL32 28
45#define R_PPC_PLT16_LO 29
46#define R_PPC_PLT16_HI 30
47#define R_PPC_PLT16_HA 31
48#define R_PPC_SDAREL16 32
49#define R_PPC_SECTOFF 33
50#define R_PPC_SECTOFF_LO 34
51#define R_PPC_SECTOFF_HI 35
52#define R_PPC_SECTOFF_HA 36
53
54/* PowerPC relocations defined for the TLS access ABI. */
55#define R_PPC_TLS 67 /* none (sym+add)@tls */
56#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
57#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
58#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
59#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
60#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
61#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
62#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
63#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
64#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
65#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
66#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
67#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
68#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
69#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
70#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
71#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
72#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
73#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
74#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
75#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
76#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
77#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
78#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
79#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
80#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
81#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
82#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
83
a99eb2ef 84/* keep this the last entry. */
1da177e4
LT		 85#define R_PPC_NUM 95
86
87/*
88 * ELF register definitions..
89 *
90 * This program is free software; you can redistribute it and/or
91 * modify it under the terms of the GNU General Public License
92 * as published by the Free Software Foundation; either version
93 * 2 of the License, or (at your option) any later version.
94 */
1da177e4
LT		 95
96#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
97#define ELF_NFPREG 33 /* includes fpscr */
1da177e4
LT		 98
99typedef unsigned long elf_greg_t64;
100typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
101
102typedef unsigned int elf_greg_t32;
103typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
5f149cf0 104typedef elf_gregset_t32 compat_elf_gregset_t;
1da177e4
LT		 105
106/*
a99eb2ef 107 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
1da177e4 108 */
a99eb2ef
BB		 109#ifdef __powerpc64__
110# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
111# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
ce48b210 112# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
a99eb2ef
BB		 113# define ELF_GREG_TYPE elf_greg_t64
114#else
115# define ELF_NEVRREG 34 /* includes acc (as 2) */
116# define ELF_NVRREG 33 /* includes vscr */
117# define ELF_GREG_TYPE elf_greg_t32
118# define ELF_ARCH EM_PPC
119# define ELF_CLASS ELFCLASS32
120# define ELF_DATA ELFDATA2MSB
121#endif /* __powerpc64__ */
122
1da177e4
LT		 123#ifndef ELF_ARCH
124# define ELF_ARCH EM_PPC64
125# define ELF_CLASS ELFCLASS64
126# define ELF_DATA ELFDATA2MSB
127 typedef elf_greg_t64 elf_greg_t;
128 typedef elf_gregset_t64 elf_gregset_t;
1da177e4
LT		 129#else
130 /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
131 typedef elf_greg_t32 elf_greg_t;
132 typedef elf_gregset_t32 elf_gregset_t;
a99eb2ef 133#endif /* ELF_ARCH */
1da177e4 134
a99eb2ef 135/* Floating point registers */
1da177e4
LT		 136typedef double elf_fpreg_t;
137typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
138
139/* Altivec registers */
140/*
141 * The entries with indexes 0-31 contain the corresponding vector registers.
142 * The entry with index 32 contains the vscr as the last word (offset 12)
143 * within the quadword. This allows the vscr to be stored as either a
144 * quadword (since it must be copied via a vector register to/from storage)
a99eb2ef
BB		 145 * or as a word.
146 *
147 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
1da177e4
LT		 148 * word (offset 0) within the quadword.
149 *
150 * This definition of the VMX state is compatible with the current PPC32
151 * ptrace interface. This allows signal handling and ptrace to use the same
152 * structures. This also simplifies the implementation of a bi-arch
153 * (combined (32- and 64-bit) gdb.
154 *
155 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
156 * vrsave along with vscr and so only uses 33 vectors for the register set
157 */
158typedef __vector128 elf_vrreg_t;
159typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
a99eb2ef 160#ifdef __powerpc64__
1da177e4 161typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
ce48b210 162typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
a99eb2ef 163#endif
1da177e4 164
dd02ec3a 165#ifdef __KERNEL__
1da177e4
LT		 166/*
167 * This is used to ensure we don't load something for the wrong architecture.
168 */
169#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
01e31dba 170#define compat_elf_check_arch(x) ((x)->e_machine == EM_PPC)
1da177e4
LT		 171
172#define USE_ELF_CORE_DUMP
81970387 173#define CORE_DUMP_USE_REGSET
637a6ff6 174#define ELF_EXEC_PAGESIZE PAGE_SIZE
1da177e4
LT		 175
176/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
177 use of this is to invoke "./ld.so someprog" to test out a new version of
178 the loader. We need to make sure that it is out of the way of the program
179 that it will "exec", and that there is sufficient room for the brk. */
180
7e60d1b4 181#define ELF_ET_DYN_BASE (0x20000000)
1da177e4 182
5f149cf0
RM		 183/*
184 * Our registers are always unsigned longs, whether we're a 32 bit
185 * process or 64 bit, on either a 64 bit or 32 bit kernel.
186 *
187 * This macro relies on elf_regs[i] having the right type to truncate to,
188 * either u32 or u64. It defines the body of the elf_core_copy_regs
189 * function, either the native one with elf_gregset_t elf_regs or
190 * the 32-bit one with elf_gregset_t32 elf_regs.
191 */
192#define PPC_ELF_CORE_COPY_REGS(elf_regs, regs) \
193 int i, nregs = min(sizeof(*regs) / sizeof(unsigned long), \
194 (size_t)ELF_NGREG); \
195 for (i = 0; i < nregs; i++) \
196 elf_regs[i] = ((unsigned long *) regs)[i]; \
197 memset(&elf_regs[i], 0, (ELF_NGREG - i) * sizeof(elf_regs[0]))
198
199/* Common routine for both 32-bit and 64-bit native processes */
a99eb2ef 200static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
5f149cf0 201 struct pt_regs *regs)
1da177e4 202{
5f149cf0 203 PPC_ELF_CORE_COPY_REGS(elf_regs, regs);
1da177e4 204}
a99eb2ef 205#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
1da177e4 206
1f7d6668
MN		 207typedef elf_vrregset_t elf_fpxregset_t;
208
a99eb2ef 209/* ELF_HWCAP yields a mask that user programs can use to figure out what
1da177e4
LT		 210 instruction set this cpu supports. This could be done in userspace,
211 but it's not easy, and we've already done it here. */
a99eb2ef 212# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
1da177e4
LT		 213
214/* This yields a string that ld.so will use to load implementation
215 specific libraries for optimization. This is more specific in
80f15dc7 216 intent than poking at uname or /proc/cpuinfo. */
1da177e4 217
80f15dc7 218#define ELF_PLATFORM (cur_cpu_spec->platform)
9115d134
NL		 219
220/* While ELF_PLATFORM indicates the ISA supported by the platform, it
221 * may not accurately reflect the underlying behavior of the hardware
222 * (as in the case of running in Power5+ compatibility mode on a
223 * Power6 machine). ELF_BASE_PLATFORM allows ld.so to load libraries
224 * that are tuned for the real hardware.
225 */
226#define ELF_BASE_PLATFORM (powerpc_base_platform)
1da177e4 227
80f15dc7
PM		 228#ifdef __powerpc64__
229# define ELF_PLAT_INIT(_r, load_addr) do { \
230 _r->gpr[2] = load_addr; \
231} while (0)
232#endif /* __powerpc64__ */
1da177e4 233
a99eb2ef
BB		 234#ifdef __powerpc64__
235# define SET_PERSONALITY(ex, ibcs2) \
1da177e4
LT		 236do { \
237 unsigned long new_flags = 0; \
238 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
239 new_flags = _TIF_32BIT; \
240 if ((current_thread_info()->flags & _TIF_32BIT) \
241 != new_flags) \
242 set_thread_flag(TIF_ABI_PENDING); \
243 else \
244 clear_thread_flag(TIF_ABI_PENDING); \
ce10d979 245 if (personality(current->personality) != PER_LINUX32) \
a91a03ee
EM		 246 set_personality(PER_LINUX | \
247 (current->personality & (~PER_MASK))); \
1da177e4 248} while (0)
1da177e4
LT		 249/*
250 * An executable for which elf_read_implies_exec() returns TRUE will
a2f95a5a
AB		 251 * have the READ_IMPLIES_EXEC personality flag set automatically. This
252 * is only required to work around bugs in old 32bit toolchains. Since
253 * the 64bit ABI has never had these issues dont enable the workaround
254 * even if we have an executable stack.
1da177e4 255 */
a99eb2ef 256# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
a2f95a5a 257 (exec_stk != EXSTACK_DISABLE_X) : 0)
a99eb2ef
BB		 258#else
259# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
260#endif /* __powerpc64__ */
1da177e4 261
1da177e4
LT		 262extern int dcache_bsize;
263extern int icache_bsize;
264extern int ucache_bsize;
265
a7f290da
BH		 266/* vDSO has arch_setup_additional_pages */
267#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
1da177e4 268struct linux_binprm;
a7f290da
BH		 269extern int arch_setup_additional_pages(struct linux_binprm *bprm,
270 int executable_stack);
a99eb2ef 271#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
1da177e4 272
178f8d78
AB		 273#endif /* __KERNEL__ */
274
1da177e4
LT		 275/*
276 * The requirements here are:
277 * - keep the final alignment of sp (sp & 0xf)
278 * - make sure the 32-bit value at the first 16 byte aligned position of
279 * AUXV is greater than 16 for glibc compatibility.
280 * AT_IGNOREPPC is used for that.
281 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
282 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
4f9a58d7 283 * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
1da177e4
LT		 284 */
285#define ARCH_DLINFO \
286do { \
287 /* Handle glibc compatibility. */ \
288 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
289 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
290 /* Cache size items */ \
291 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
292 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
293 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
a5bba930 294 VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base) \
a99eb2ef 295} while (0)
1da177e4
LT		 296
297/* PowerPC64 relocations defined by the ABIs */
298#define R_PPC64_NONE R_PPC_NONE
299#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
300#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
301#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
302#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
303#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
304#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
305#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
306#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
307#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
308#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
309#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
310#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
311#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
312#define R_PPC64_GOT16 R_PPC_GOT16
313#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
314#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
315#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
316
317#define R_PPC64_COPY R_PPC_COPY
318#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
319#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
320#define R_PPC64_RELATIVE R_PPC_RELATIVE
321
322#define R_PPC64_UADDR32 R_PPC_UADDR32
323#define R_PPC64_UADDR16 R_PPC_UADDR16
324#define R_PPC64_REL32 R_PPC_REL32
325#define R_PPC64_PLT32 R_PPC_PLT32
326#define R_PPC64_PLTREL32 R_PPC_PLTREL32
327#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
328#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
329#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
330
331#define R_PPC64_SECTOFF R_PPC_SECTOFF
332#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
333#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
334#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
335#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
336#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
337#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
338#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
339#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
340#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
341#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
342#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
343#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
344#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
345#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
346#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
347#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
348#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
349#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
350#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
351#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
352#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
353#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
354
355#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
356#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
357#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
358#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
359#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
360#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
361#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
362#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
363#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
364#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
365#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
366
367/* PowerPC64 relocations defined for the TLS access ABI. */
368#define R_PPC64_TLS 67 /* none (sym+add)@tls */
369#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
370#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
371#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
372#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
373#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
374#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
375#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
376#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
377#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
378#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
379#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
380#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
381#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
382#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
383#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
384#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
385#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
386#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
387#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
388#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
389#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
390#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
391#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
392#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
393#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
394#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
395#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
396#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
397#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
398#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
399#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
400#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
401#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
402#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
403#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
404#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
405#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
406#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
407#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
408
409/* Keep this the last entry. */
410#define R_PPC64_NUM 107
411
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AB		 412#ifdef __KERNEL__
413
e055595d 414#ifdef CONFIG_SPU_BASE
bf1ab978
DGM		 415/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
416#define NT_SPU 1
417
bf1ab978 418#define ARCH_HAVE_EXTRA_ELF_NOTES
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ME		 419
420#endif /* CONFIG_SPU_BASE */
bf1ab978 421
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AB		 422#endif /* __KERNEL */
423
a99eb2ef 424#endif /* _ASM_POWERPC_ELF_H */
Linux kernel - Deliverables
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