Commit | Line | Data |
---|---|---|
047ea784 PM |
1 | #ifndef _ASM_POWERPC_IO_H |
2 | #define _ASM_POWERPC_IO_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
1da177e4 LT |
4 | |
5 | /* | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
1269277a DW |
12 | /* Check of existence of legacy devices */ |
13 | extern int check_legacy_ioport(unsigned long base_port); | |
30cbc222 | 14 | #define PNPBIOS_BASE 0xf000 /* only relevant for PReP */ |
1269277a | 15 | |
1da177e4 LT |
16 | #include <linux/compiler.h> |
17 | #include <asm/page.h> | |
18 | #include <asm/byteorder.h> | |
feaf7cf1 | 19 | #include <asm/synch.h> |
1da177e4 | 20 | #include <asm/delay.h> |
68a64357 | 21 | #include <asm/mmu.h> |
1da177e4 LT |
22 | |
23 | #include <asm-generic/iomap.h> | |
24 | ||
68a64357 BH |
25 | #ifdef CONFIG_PPC64 |
26 | #include <asm/paca.h> | |
27 | #endif | |
28 | ||
1da177e4 LT |
29 | #define SIO_CONFIG_RA 0x398 |
30 | #define SIO_CONFIG_RD 0x399 | |
31 | ||
32 | #define SLOW_DOWN_IO | |
33 | ||
68a64357 BH |
34 | /* 32 bits uses slightly different variables for the various IO |
35 | * bases. Most of this file only uses _IO_BASE though which we | |
36 | * define properly based on the platform | |
37 | */ | |
38 | #ifndef CONFIG_PCI | |
39 | #define _IO_BASE 0 | |
40 | #define _ISA_MEM_BASE 0 | |
41 | #define PCI_DRAM_OFFSET 0 | |
42 | #elif defined(CONFIG_PPC32) | |
43 | #define _IO_BASE isa_io_base | |
44 | #define _ISA_MEM_BASE isa_mem_base | |
45 | #define PCI_DRAM_OFFSET pci_dram_offset | |
46 | #else | |
47 | #define _IO_BASE pci_io_base | |
48 | #define _ISA_MEM_BASE 0 | |
49 | #define PCI_DRAM_OFFSET 0 | |
50 | #endif | |
51 | ||
52 | extern unsigned long isa_io_base; | |
53 | extern unsigned long isa_mem_base; | |
54 | extern unsigned long pci_io_base; | |
55 | extern unsigned long pci_dram_offset; | |
56 | ||
57 | #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO) | |
58 | #error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits | |
59 | #endif | |
60 | ||
4cb3cee0 BH |
61 | /* |
62 | * | |
63 | * Low level MMIO accessors | |
64 | * | |
65 | * This provides the non-bus specific accessors to MMIO. Those are PowerPC | |
66 | * specific and thus shouldn't be used in generic code. The accessors | |
67 | * provided here are: | |
68 | * | |
69 | * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 | |
70 | * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 | |
71 | * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns | |
72 | * | |
73 | * Those operate directly on a kernel virtual address. Note that the prototype | |
74 | * for the out_* accessors has the arguments in opposite order from the usual | |
75 | * linux PCI accessors. Unlike those, they take the address first and the value | |
76 | * next. | |
77 | * | |
78 | * Note: I might drop the _ns suffix on the stream operations soon as it is | |
79 | * simply normal for stream operations to not swap in the first place. | |
80 | * | |
81 | */ | |
82 | ||
68a64357 | 83 | #ifdef CONFIG_PPC64 |
4cb3cee0 | 84 | #define IO_SET_SYNC_FLAG() do { get_paca()->io_sync = 1; } while(0) |
68a64357 BH |
85 | #else |
86 | #define IO_SET_SYNC_FLAG() | |
87 | #endif | |
4cb3cee0 BH |
88 | |
89 | #define DEF_MMIO_IN(name, type, insn) \ | |
90 | static inline type name(const volatile type __iomem *addr) \ | |
91 | { \ | |
92 | type ret; \ | |
93 | __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync" \ | |
94 | : "=r" (ret) : "r" (addr), "m" (*addr)); \ | |
95 | return ret; \ | |
96 | } | |
97 | ||
98 | #define DEF_MMIO_OUT(name, type, insn) \ | |
99 | static inline void name(volatile type __iomem *addr, type val) \ | |
100 | { \ | |
101 | __asm__ __volatile__("sync;" insn \ | |
102 | : "=m" (*addr) : "r" (val), "r" (addr)); \ | |
103 | IO_SET_SYNC_FLAG(); \ | |
104 | } | |
105 | ||
106 | ||
107 | #define DEF_MMIO_IN_BE(name, size, insn) \ | |
108 | DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2") | |
109 | #define DEF_MMIO_IN_LE(name, size, insn) \ | |
110 | DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1") | |
111 | ||
112 | #define DEF_MMIO_OUT_BE(name, size, insn) \ | |
113 | DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0") | |
114 | #define DEF_MMIO_OUT_LE(name, size, insn) \ | |
115 | DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2") | |
116 | ||
117 | DEF_MMIO_IN_BE(in_8, 8, lbz); | |
118 | DEF_MMIO_IN_BE(in_be16, 16, lhz); | |
119 | DEF_MMIO_IN_BE(in_be32, 32, lwz); | |
4cb3cee0 BH |
120 | DEF_MMIO_IN_LE(in_le16, 16, lhbrx); |
121 | DEF_MMIO_IN_LE(in_le32, 32, lwbrx); | |
122 | ||
123 | DEF_MMIO_OUT_BE(out_8, 8, stb); | |
124 | DEF_MMIO_OUT_BE(out_be16, 16, sth); | |
125 | DEF_MMIO_OUT_BE(out_be32, 32, stw); | |
4cb3cee0 BH |
126 | DEF_MMIO_OUT_LE(out_le16, 16, sthbrx); |
127 | DEF_MMIO_OUT_LE(out_le32, 32, stwbrx); | |
128 | ||
68a64357 BH |
129 | #ifdef __powerpc64__ |
130 | DEF_MMIO_OUT_BE(out_be64, 64, std); | |
131 | DEF_MMIO_IN_BE(in_be64, 64, ld); | |
132 | ||
4cb3cee0 BH |
133 | /* There is no asm instructions for 64 bits reverse loads and stores */ |
134 | static inline u64 in_le64(const volatile u64 __iomem *addr) | |
135 | { | |
136 | return le64_to_cpu(in_be64(addr)); | |
137 | } | |
138 | ||
139 | static inline void out_le64(volatile u64 __iomem *addr, u64 val) | |
140 | { | |
141 | out_be64(addr, cpu_to_le64(val)); | |
142 | } | |
68a64357 | 143 | #endif /* __powerpc64__ */ |
4cb3cee0 BH |
144 | |
145 | /* | |
146 | * Low level IO stream instructions are defined out of line for now | |
147 | */ | |
148 | extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); | |
149 | extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); | |
150 | extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); | |
151 | extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); | |
152 | extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); | |
153 | extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); | |
154 | ||
155 | /* The _ns naming is historical and will be removed. For now, just #define | |
156 | * the non _ns equivalent names | |
157 | */ | |
158 | #define _insw _insw_ns | |
159 | #define _insl _insl_ns | |
160 | #define _outsw _outsw_ns | |
161 | #define _outsl _outsl_ns | |
162 | ||
68a64357 BH |
163 | |
164 | /* | |
165 | * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line | |
166 | */ | |
167 | ||
168 | extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); | |
169 | extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, | |
170 | unsigned long n); | |
171 | extern void _memcpy_toio(volatile void __iomem *dest, const void *src, | |
172 | unsigned long n); | |
173 | ||
4cb3cee0 BH |
174 | /* |
175 | * | |
176 | * PCI and standard ISA accessors | |
177 | * | |
178 | * Those are globally defined linux accessors for devices on PCI or ISA | |
179 | * busses. They follow the Linux defined semantics. The current implementation | |
180 | * for PowerPC is as close as possible to the x86 version of these, and thus | |
181 | * provides fairly heavy weight barriers for the non-raw versions | |
182 | * | |
183 | * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO | |
184 | * allowing the platform to provide its own implementation of some or all | |
185 | * of the accessors. | |
186 | */ | |
187 | ||
4cb3cee0 BH |
188 | |
189 | /* | |
190 | * Non ordered and non-swapping "raw" accessors | |
191 | */ | |
1da177e4 LT |
192 | |
193 | static inline unsigned char __raw_readb(const volatile void __iomem *addr) | |
194 | { | |
195 | return *(volatile unsigned char __force *)addr; | |
196 | } | |
197 | static inline unsigned short __raw_readw(const volatile void __iomem *addr) | |
198 | { | |
199 | return *(volatile unsigned short __force *)addr; | |
200 | } | |
201 | static inline unsigned int __raw_readl(const volatile void __iomem *addr) | |
202 | { | |
203 | return *(volatile unsigned int __force *)addr; | |
204 | } | |
1da177e4 LT |
205 | static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) |
206 | { | |
207 | *(volatile unsigned char __force *)addr = v; | |
208 | } | |
209 | static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) | |
210 | { | |
211 | *(volatile unsigned short __force *)addr = v; | |
212 | } | |
213 | static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) | |
214 | { | |
215 | *(volatile unsigned int __force *)addr = v; | |
216 | } | |
68a64357 BH |
217 | |
218 | #ifdef __powerpc64__ | |
219 | static inline unsigned long __raw_readq(const volatile void __iomem *addr) | |
220 | { | |
221 | return *(volatile unsigned long __force *)addr; | |
222 | } | |
1da177e4 LT |
223 | static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) |
224 | { | |
225 | *(volatile unsigned long __force *)addr = v; | |
226 | } | |
68a64357 | 227 | #endif /* __powerpc64__ */ |
1da177e4 LT |
228 | |
229 | /* | |
4cb3cee0 BH |
230 | * |
231 | * PCI PIO and MMIO accessors. | |
232 | * | |
233 | */ | |
234 | ||
68a64357 BH |
235 | /* |
236 | * Include the EEH definitions when EEH is enabled only so they don't get | |
237 | * in the way when building for 32 bits | |
238 | */ | |
239 | #ifdef CONFIG_EEH | |
4cb3cee0 | 240 | #include <asm/eeh.h> |
68a64357 | 241 | #endif |
4cb3cee0 BH |
242 | |
243 | /* Shortcut to the MMIO argument pointer */ | |
244 | #define PCI_IO_ADDR volatile void __iomem * | |
245 | ||
246 | /* Indirect IO address tokens: | |
247 | * | |
248 | * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks | |
68a64357 | 249 | * on all IOs. (Note that this is all 64 bits only for now) |
4cb3cee0 BH |
250 | * |
251 | * To help platforms who may need to differenciate MMIO addresses in | |
252 | * their hooks, a bitfield is reserved for use by the platform near the | |
253 | * top of MMIO addresses (not PIO, those have to cope the hard way). | |
254 | * | |
255 | * This bit field is 12 bits and is at the top of the IO virtual | |
256 | * addresses PCI_IO_INDIRECT_TOKEN_MASK. | |
257 | * | |
258 | * The kernel virtual space is thus: | |
259 | * | |
260 | * 0xD000000000000000 : vmalloc | |
261 | * 0xD000080000000000 : PCI PHB IO space | |
262 | * 0xD000080080000000 : ioremap | |
263 | * 0xD0000fffffffffff : end of ioremap region | |
264 | * | |
265 | * Since the top 4 bits are reserved as the region ID, we use thus | |
266 | * the next 12 bits and keep 4 bits available for the future if the | |
267 | * virtual address space is ever to be extended. | |
268 | * | |
269 | * The direct IO mapping operations will then mask off those bits | |
270 | * before doing the actual access, though that only happen when | |
271 | * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that | |
272 | * mechanism | |
273 | */ | |
274 | ||
275 | #ifdef CONFIG_PPC_INDIRECT_IO | |
276 | #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul | |
277 | #define PCI_IO_IND_TOKEN_SHIFT 48 | |
278 | #define PCI_FIX_ADDR(addr) \ | |
279 | ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) | |
280 | #define PCI_GET_ADDR_TOKEN(addr) \ | |
281 | (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ | |
282 | PCI_IO_IND_TOKEN_SHIFT) | |
283 | #define PCI_SET_ADDR_TOKEN(addr, token) \ | |
284 | do { \ | |
285 | unsigned long __a = (unsigned long)(addr); \ | |
286 | __a &= ~PCI_IO_IND_TOKEN_MASK; \ | |
287 | __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ | |
288 | (addr) = (void __iomem *)__a; \ | |
289 | } while(0) | |
290 | #else | |
291 | #define PCI_FIX_ADDR(addr) (addr) | |
292 | #endif | |
293 | ||
68a64357 BH |
294 | /* |
295 | * On 32 bits, PIO operations have a recovery mechanism in case they trigger | |
296 | * machine checks (which they occasionally do when probing non existing | |
297 | * IO ports on some platforms, like PowerMac and 8xx). | |
298 | * I always found it to be of dubious reliability and I am tempted to get | |
299 | * rid of it one of these days. So if you think it's important to keep it, | |
300 | * please voice up asap. We never had it for 64 bits and I do not intend | |
301 | * to port it over | |
302 | */ | |
303 | ||
304 | #ifdef CONFIG_PPC32 | |
305 | ||
306 | #define __do_in_asm(name, op) \ | |
307 | extern __inline__ unsigned int name(unsigned int port) \ | |
308 | { \ | |
309 | unsigned int x; \ | |
310 | __asm__ __volatile__( \ | |
311 | "sync\n" \ | |
312 | "0:" op " %0,0,%1\n" \ | |
313 | "1: twi 0,%0,0\n" \ | |
314 | "2: isync\n" \ | |
315 | "3: nop\n" \ | |
316 | "4:\n" \ | |
317 | ".section .fixup,\"ax\"\n" \ | |
318 | "5: li %0,-1\n" \ | |
319 | " b 4b\n" \ | |
320 | ".previous\n" \ | |
321 | ".section __ex_table,\"a\"\n" \ | |
322 | " .align 2\n" \ | |
323 | " .long 0b,5b\n" \ | |
324 | " .long 1b,5b\n" \ | |
325 | " .long 2b,5b\n" \ | |
326 | " .long 3b,5b\n" \ | |
327 | ".previous" \ | |
328 | : "=&r" (x) \ | |
329 | : "r" (port + _IO_BASE)); \ | |
330 | return x; \ | |
331 | } | |
332 | ||
333 | #define __do_out_asm(name, op) \ | |
334 | extern __inline__ void name(unsigned int val, unsigned int port) \ | |
335 | { \ | |
336 | __asm__ __volatile__( \ | |
337 | "sync\n" \ | |
338 | "0:" op " %0,0,%1\n" \ | |
339 | "1: sync\n" \ | |
340 | "2:\n" \ | |
341 | ".section __ex_table,\"a\"\n" \ | |
342 | " .align 2\n" \ | |
343 | " .long 0b,2b\n" \ | |
344 | " .long 1b,2b\n" \ | |
345 | ".previous" \ | |
346 | : : "r" (val), "r" (port + _IO_BASE)); \ | |
347 | } | |
348 | ||
349 | __do_in_asm(_rec_inb, "lbzx") | |
350 | __do_in_asm(_rec_inw, "lhbrx") | |
351 | __do_in_asm(_rec_inl, "lwbrx") | |
352 | __do_out_asm(_rec_outb, "stbx") | |
353 | __do_out_asm(_rec_outw, "sthbrx") | |
354 | __do_out_asm(_rec_outl, "stwbrx") | |
355 | ||
356 | #endif /* CONFIG_PPC32 */ | |
357 | ||
4cb3cee0 BH |
358 | /* The "__do_*" operations below provide the actual "base" implementation |
359 | * for each of the defined acccessor. Some of them use the out_* functions | |
360 | * directly, some of them still use EEH, though we might change that in the | |
361 | * future. Those macros below provide the necessary argument swapping and | |
362 | * handling of the IO base for PIO. | |
363 | * | |
364 | * They are themselves used by the macros that define the actual accessors | |
365 | * and can be used by the hooks if any. | |
366 | * | |
367 | * Note that PIO operations are always defined in terms of their corresonding | |
368 | * MMIO operations. That allows platforms like iSeries who want to modify the | |
369 | * behaviour of both to only hook on the MMIO version and get both. It's also | |
370 | * possible to hook directly at the toplevel PIO operation if they have to | |
371 | * be handled differently | |
372 | */ | |
373 | #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) | |
374 | #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) | |
375 | #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) | |
376 | #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) | |
377 | #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) | |
378 | #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) | |
379 | #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) | |
68a64357 BH |
380 | |
381 | #ifdef CONFIG_EEH | |
4cb3cee0 BH |
382 | #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) |
383 | #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) | |
384 | #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) | |
385 | #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) | |
386 | #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) | |
387 | #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) | |
388 | #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) | |
68a64357 BH |
389 | #else /* CONFIG_EEH */ |
390 | #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) | |
391 | #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) | |
392 | #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) | |
393 | #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) | |
394 | #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) | |
395 | #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) | |
396 | #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) | |
397 | #endif /* !defined(CONFIG_EEH) */ | |
398 | ||
399 | #ifdef CONFIG_PPC32 | |
400 | #define __do_outb(val, port) _rec_outb(val, port) | |
401 | #define __do_outw(val, port) _rec_outw(val, port) | |
402 | #define __do_outl(val, port) _rec_outl(val, port) | |
403 | #define __do_inb(port) _rec_inb(port) | |
404 | #define __do_inw(port) _rec_inw(port) | |
405 | #define __do_inl(port) _rec_inl(port) | |
406 | #else /* CONFIG_PPC32 */ | |
407 | #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); | |
408 | #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); | |
409 | #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); | |
410 | #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); | |
411 | #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); | |
412 | #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); | |
413 | #endif /* !CONFIG_PPC32 */ | |
414 | ||
415 | #ifdef CONFIG_EEH | |
4cb3cee0 BH |
416 | #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) |
417 | #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) | |
418 | #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) | |
68a64357 BH |
419 | #else /* CONFIG_EEH */ |
420 | #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) | |
421 | #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) | |
422 | #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) | |
423 | #endif /* !CONFIG_EEH */ | |
4cb3cee0 BH |
424 | #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) |
425 | #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) | |
426 | #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) | |
427 | ||
68a64357 BH |
428 | #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) |
429 | #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) | |
430 | #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) | |
431 | #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
432 | #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
433 | #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
434 | ||
435 | #define __do_memset_io(addr, c, n) \ | |
436 | _memset_io(PCI_FIX_ADDR(addr), c, n) | |
437 | #define __do_memcpy_toio(dst, src, n) \ | |
438 | _memcpy_toio(PCI_FIX_ADDR(dst), src, n) | |
439 | ||
440 | #ifdef CONFIG_EEH | |
441 | #define __do_memcpy_fromio(dst, src, n) \ | |
442 | eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) | |
443 | #else /* CONFIG_EEH */ | |
444 | #define __do_memcpy_fromio(dst, src, n) \ | |
445 | _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) | |
446 | #endif /* !CONFIG_EEH */ | |
4cb3cee0 BH |
447 | |
448 | #ifdef CONFIG_PPC_INDIRECT_IO | |
449 | #define DEF_PCI_HOOK(x) x | |
450 | #else | |
451 | #define DEF_PCI_HOOK(x) NULL | |
452 | #endif | |
453 | ||
454 | /* Structure containing all the hooks */ | |
455 | extern struct ppc_pci_io { | |
456 | ||
457 | #define DEF_PCI_AC_RET(name, ret, at, al) ret (*name) at; | |
458 | #define DEF_PCI_AC_NORET(name, at, al) void (*name) at; | |
459 | ||
460 | #include <asm/io-defs.h> | |
461 | ||
462 | #undef DEF_PCI_AC_RET | |
463 | #undef DEF_PCI_AC_NORET | |
464 | ||
465 | } ppc_pci_io; | |
466 | ||
467 | /* The inline wrappers */ | |
468 | #define DEF_PCI_AC_RET(name, ret, at, al) \ | |
469 | static inline ret name at \ | |
470 | { \ | |
471 | if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \ | |
472 | return ppc_pci_io.name al; \ | |
473 | return __do_##name al; \ | |
474 | } | |
475 | ||
476 | #define DEF_PCI_AC_NORET(name, at, al) \ | |
477 | static inline void name at \ | |
478 | { \ | |
479 | if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \ | |
480 | ppc_pci_io.name al; \ | |
481 | else \ | |
482 | __do_##name al; \ | |
483 | } | |
484 | ||
485 | #include <asm/io-defs.h> | |
486 | ||
487 | #undef DEF_PCI_AC_RET | |
488 | #undef DEF_PCI_AC_NORET | |
489 | ||
490 | /* Some drivers check for the presence of readq & writeq with | |
491 | * a #ifdef, so we make them happy here. | |
492 | */ | |
68a64357 | 493 | #ifdef __powerpc64__ |
4cb3cee0 BH |
494 | #define readq readq |
495 | #define writeq writeq | |
68a64357 BH |
496 | #endif |
497 | ||
498 | #ifdef CONFIG_NOT_COHERENT_CACHE | |
4cb3cee0 | 499 | |
68a64357 BH |
500 | #define dma_cache_inv(_start,_size) \ |
501 | invalidate_dcache_range(_start, (_start + _size)) | |
502 | #define dma_cache_wback(_start,_size) \ | |
503 | clean_dcache_range(_start, (_start + _size)) | |
504 | #define dma_cache_wback_inv(_start,_size) \ | |
505 | flush_dcache_range(_start, (_start + _size)) | |
506 | ||
507 | #else /* CONFIG_NOT_COHERENT_CACHE */ | |
4cb3cee0 BH |
508 | |
509 | #define dma_cache_inv(_start,_size) do { } while (0) | |
510 | #define dma_cache_wback(_start,_size) do { } while (0) | |
511 | #define dma_cache_wback_inv(_start,_size) do { } while (0) | |
512 | ||
68a64357 | 513 | #endif /* !CONFIG_NOT_COHERENT_CACHE */ |
4cb3cee0 BH |
514 | |
515 | /* | |
516 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
517 | * access | |
518 | */ | |
519 | #define xlate_dev_mem_ptr(p) __va(p) | |
520 | ||
521 | /* | |
522 | * Convert a virtual cached pointer to an uncached pointer | |
523 | */ | |
524 | #define xlate_dev_kmem_ptr(p) p | |
caf81329 | 525 | |
4cb3cee0 BH |
526 | /* |
527 | * We don't do relaxed operations yet, at least not with this semantic | |
528 | */ | |
1da177e4 LT |
529 | #define readb_relaxed(addr) readb(addr) |
530 | #define readw_relaxed(addr) readw(addr) | |
531 | #define readl_relaxed(addr) readl(addr) | |
532 | #define readq_relaxed(addr) readq(addr) | |
533 | ||
68a64357 BH |
534 | #ifdef CONFIG_PPC32 |
535 | #define mmiowb() | |
536 | #else | |
4cb3cee0 BH |
537 | /* |
538 | * Enforce synchronisation of stores vs. spin_unlock | |
539 | * (this does it explicitely, though our implementation of spin_unlock | |
540 | * does it implicitely too) | |
541 | */ | |
f007cacf PM |
542 | static inline void mmiowb(void) |
543 | { | |
292f86f0 HD |
544 | unsigned long tmp; |
545 | ||
546 | __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" | |
547 | : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) | |
548 | : "memory"); | |
f007cacf | 549 | } |
68a64357 | 550 | #endif /* !CONFIG_PPC32 */ |
1da177e4 | 551 | |
4cb3cee0 BH |
552 | static inline void iosync(void) |
553 | { | |
554 | __asm__ __volatile__ ("sync" : : : "memory"); | |
555 | } | |
556 | ||
557 | /* Enforce in-order execution of data I/O. | |
558 | * No distinction between read/write on PPC; use eieio for all three. | |
559 | * Those are fairly week though. They don't provide a barrier between | |
560 | * MMIO and cacheable storage nor do they provide a barrier vs. locks, | |
561 | * they only provide barriers between 2 __raw MMIO operations and | |
562 | * possibly break write combining. | |
563 | */ | |
564 | #define iobarrier_rw() eieio() | |
565 | #define iobarrier_r() eieio() | |
566 | #define iobarrier_w() eieio() | |
567 | ||
568 | ||
1da177e4 LT |
569 | /* |
570 | * output pause versions need a delay at least for the | |
571 | * w83c105 ide controller in a p610. | |
572 | */ | |
573 | #define inb_p(port) inb(port) | |
574 | #define outb_p(val, port) (udelay(1), outb((val), (port))) | |
575 | #define inw_p(port) inw(port) | |
576 | #define outw_p(val, port) (udelay(1), outw((val), (port))) | |
577 | #define inl_p(port) inl(port) | |
578 | #define outl_p(val, port) (udelay(1), outl((val), (port))) | |
579 | ||
1da177e4 LT |
580 | |
581 | #define IO_SPACE_LIMIT ~(0UL) | |
582 | ||
583 | ||
1da177e4 LT |
584 | /** |
585 | * ioremap - map bus memory into CPU space | |
586 | * @address: bus address of the memory | |
587 | * @size: size of the resource to map | |
588 | * | |
589 | * ioremap performs a platform specific sequence of operations to | |
590 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ | |
591 | * writew/writel functions and the other mmio helpers. The returned | |
592 | * address is not guaranteed to be usable directly as a virtual | |
593 | * address. | |
4cb3cee0 BH |
594 | * |
595 | * We provide a few variations of it: | |
596 | * | |
597 | * * ioremap is the standard one and provides non-cacheable guarded mappings | |
598 | * and can be hooked by the platform via ppc_md | |
599 | * | |
600 | * * ioremap_flags allows to specify the page flags as an argument and can | |
601 | * also be hooked by the platform via ppc_md | |
602 | * | |
603 | * * ioremap_nocache is identical to ioremap | |
604 | * | |
605 | * * iounmap undoes such a mapping and can be hooked | |
606 | * | |
607 | * * __ioremap_explicit (and the pending __iounmap_explicit) are low level | |
608 | * functions to create hand-made mappings for use only by the PCI code | |
609 | * and cannot currently be hooked. | |
610 | * | |
611 | * * __ioremap is the low level implementation used by ioremap and | |
612 | * ioremap_flags and cannot be hooked (but can be used by a hook on one | |
613 | * of the previous ones) | |
614 | * | |
615 | * * __iounmap, is the low level implementation used by iounmap and cannot | |
616 | * be hooked (but can be used by a hook on iounmap) | |
617 | * | |
1da177e4 | 618 | */ |
68a64357 BH |
619 | extern void __iomem *ioremap(phys_addr_t address, unsigned long size); |
620 | extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size, | |
4cb3cee0 | 621 | unsigned long flags); |
1da177e4 | 622 | #define ioremap_nocache(addr, size) ioremap((addr), (size)) |
68a64357 | 623 | extern void iounmap(volatile void __iomem *addr); |
4cb3cee0 | 624 | |
68a64357 | 625 | extern void __iomem *__ioremap(phys_addr_t, unsigned long size, |
4cb3cee0 | 626 | unsigned long flags); |
68a64357 | 627 | extern void __iounmap(volatile void __iomem *addr); |
4cb3cee0 | 628 | |
68a64357 | 629 | extern int __ioremap_explicit(phys_addr_t p_addr, unsigned long v_addr, |
4cb3cee0 | 630 | unsigned long size, unsigned long flags); |
68a64357 BH |
631 | extern int __iounmap_explicit(volatile void __iomem *start, |
632 | unsigned long size); | |
4cb3cee0 | 633 | |
1da177e4 LT |
634 | extern void __iomem * reserve_phb_iospace(unsigned long size); |
635 | ||
68a64357 BH |
636 | /* Those are more 32 bits only functions */ |
637 | extern unsigned long iopa(unsigned long addr); | |
638 | extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; | |
639 | extern void io_block_mapping(unsigned long virt, phys_addr_t phys, | |
640 | unsigned int size, int flags); | |
641 | ||
4cb3cee0 BH |
642 | |
643 | /* | |
644 | * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation | |
645 | * which needs some additional definitions here. They basically allow PIO | |
646 | * space overall to be 1GB. This will work as long as we never try to use | |
647 | * iomap to map MMIO below 1GB which should be fine on ppc64 | |
648 | */ | |
649 | #define HAVE_ARCH_PIO_SIZE 1 | |
650 | #define PIO_OFFSET 0x00000000UL | |
651 | #define PIO_MASK 0x3fffffffUL | |
652 | #define PIO_RESERVED 0x40000000UL | |
653 | ||
654 | #define mmio_read16be(addr) readw_be(addr) | |
655 | #define mmio_read32be(addr) readl_be(addr) | |
656 | #define mmio_write16be(val, addr) writew_be(val, addr) | |
657 | #define mmio_write32be(val, addr) writel_be(val, addr) | |
658 | #define mmio_insb(addr, dst, count) readsb(addr, dst, count) | |
659 | #define mmio_insw(addr, dst, count) readsw(addr, dst, count) | |
660 | #define mmio_insl(addr, dst, count) readsl(addr, dst, count) | |
661 | #define mmio_outsb(addr, src, count) writesb(addr, src, count) | |
662 | #define mmio_outsw(addr, src, count) writesw(addr, src, count) | |
663 | #define mmio_outsl(addr, src, count) writesl(addr, src, count) | |
664 | ||
1da177e4 LT |
665 | /** |
666 | * virt_to_phys - map virtual addresses to physical | |
667 | * @address: address to remap | |
668 | * | |
669 | * The returned physical address is the physical (CPU) mapping for | |
670 | * the memory address given. It is only valid to use this function on | |
671 | * addresses directly mapped or allocated via kmalloc. | |
672 | * | |
673 | * This function does not give bus mappings for DMA transfers. In | |
674 | * almost all conceivable cases a device driver should not be using | |
675 | * this function | |
676 | */ | |
677 | static inline unsigned long virt_to_phys(volatile void * address) | |
678 | { | |
679 | return __pa((unsigned long)address); | |
680 | } | |
681 | ||
682 | /** | |
683 | * phys_to_virt - map physical address to virtual | |
684 | * @address: address to remap | |
685 | * | |
686 | * The returned virtual address is a current CPU mapping for | |
687 | * the memory address given. It is only valid to use this function on | |
688 | * addresses that have a kernel mapping | |
689 | * | |
690 | * This function does not handle bus mappings for DMA transfers. In | |
691 | * almost all conceivable cases a device driver should not be using | |
692 | * this function | |
693 | */ | |
694 | static inline void * phys_to_virt(unsigned long address) | |
695 | { | |
696 | return (void *)__va(address); | |
697 | } | |
698 | ||
699 | /* | |
700 | * Change "struct page" to physical address. | |
701 | */ | |
702 | #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) | |
703 | ||
704 | /* We do NOT want virtual merging, it would put too much pressure on | |
705 | * our iommu allocator. Instead, we want drivers to be smart enough | |
706 | * to coalesce sglists that happen to have been mapped in a contiguous | |
707 | * way by the iommu | |
708 | */ | |
709 | #define BIO_VMERGE_BOUNDARY 0 | |
710 | ||
68a64357 BH |
711 | /* |
712 | * 32 bits still uses virt_to_bus() for it's implementation of DMA | |
713 | * mappings se we have to keep it defined here. We also have some old | |
714 | * drivers (shame shame shame) that use bus_to_virt() and haven't been | |
715 | * fixed yet so I need to define it here. | |
716 | */ | |
717 | #ifdef CONFIG_PPC32 | |
718 | ||
719 | static inline unsigned long virt_to_bus(volatile void * address) | |
720 | { | |
721 | if (address == NULL) | |
722 | return 0; | |
723 | return __pa(address) + PCI_DRAM_OFFSET; | |
724 | } | |
725 | ||
726 | static inline void * bus_to_virt(unsigned long address) | |
727 | { | |
728 | if (address == 0) | |
729 | return NULL; | |
730 | return __va(address - PCI_DRAM_OFFSET); | |
731 | } | |
732 | ||
733 | #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) | |
734 | ||
735 | #endif /* CONFIG_PPC32 */ | |
736 | ||
737 | ||
1da177e4 LT |
738 | #endif /* __KERNEL__ */ |
739 | ||
047ea784 | 740 | #endif /* _ASM_POWERPC_IO_H */ |