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8d2169e8 DG |
1 | #ifndef _ASM_POWERPC_MMU_HASH64_H_ |
2 | #define _ASM_POWERPC_MMU_HASH64_H_ | |
3 | /* | |
4 | * PowerPC64 memory management structures | |
5 | * | |
6 | * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com> | |
7 | * PPC64 rework. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <asm/asm-compat.h> | |
16 | #include <asm/page.h> | |
17 | ||
18 | /* | |
19 | * Segment table | |
20 | */ | |
21 | ||
22 | #define STE_ESID_V 0x80 | |
23 | #define STE_ESID_KS 0x20 | |
24 | #define STE_ESID_KP 0x10 | |
25 | #define STE_ESID_N 0x08 | |
26 | ||
27 | #define STE_VSID_SHIFT 12 | |
28 | ||
29 | /* Location of cpu0's segment table */ | |
30 | #define STAB0_PAGE 0x6 | |
31 | #define STAB0_OFFSET (STAB0_PAGE << 12) | |
32 | #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START) | |
33 | ||
34 | #ifndef __ASSEMBLY__ | |
35 | extern char initial_stab[]; | |
36 | #endif /* ! __ASSEMBLY */ | |
37 | ||
38 | /* | |
39 | * SLB | |
40 | */ | |
41 | ||
42 | #define SLB_NUM_BOLTED 3 | |
43 | #define SLB_CACHE_ENTRIES 8 | |
44 | ||
45 | /* Bits in the SLB ESID word */ | |
46 | #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ | |
47 | ||
48 | /* Bits in the SLB VSID word */ | |
49 | #define SLB_VSID_SHIFT 12 | |
1189be65 PM |
50 | #define SLB_VSID_SHIFT_1T 24 |
51 | #define SLB_VSID_SSIZE_SHIFT 62 | |
8d2169e8 DG |
52 | #define SLB_VSID_B ASM_CONST(0xc000000000000000) |
53 | #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) | |
54 | #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) | |
55 | #define SLB_VSID_KS ASM_CONST(0x0000000000000800) | |
56 | #define SLB_VSID_KP ASM_CONST(0x0000000000000400) | |
57 | #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ | |
58 | #define SLB_VSID_L ASM_CONST(0x0000000000000100) | |
59 | #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ | |
60 | #define SLB_VSID_LP ASM_CONST(0x0000000000000030) | |
61 | #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000) | |
62 | #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010) | |
63 | #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020) | |
64 | #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030) | |
65 | #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP) | |
66 | ||
67 | #define SLB_VSID_KERNEL (SLB_VSID_KP) | |
68 | #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) | |
69 | ||
70 | #define SLBIE_C (0x08000000) | |
1189be65 | 71 | #define SLBIE_SSIZE_SHIFT 25 |
8d2169e8 DG |
72 | |
73 | /* | |
74 | * Hash table | |
75 | */ | |
76 | ||
77 | #define HPTES_PER_GROUP 8 | |
78 | ||
2454c7e9 | 79 | #define HPTE_V_SSIZE_SHIFT 62 |
8d2169e8 | 80 | #define HPTE_V_AVPN_SHIFT 7 |
2454c7e9 | 81 | #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) |
8d2169e8 | 82 | #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) |
91bbbe22 | 83 | #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) |
8d2169e8 DG |
84 | #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) |
85 | #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) | |
86 | #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) | |
87 | #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) | |
88 | #define HPTE_V_VALID ASM_CONST(0x0000000000000001) | |
89 | ||
90 | #define HPTE_R_PP0 ASM_CONST(0x8000000000000000) | |
91 | #define HPTE_R_TS ASM_CONST(0x4000000000000000) | |
92 | #define HPTE_R_RPN_SHIFT 12 | |
93 | #define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000) | |
94 | #define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff) | |
95 | #define HPTE_R_PP ASM_CONST(0x0000000000000003) | |
96 | #define HPTE_R_N ASM_CONST(0x0000000000000004) | |
97 | #define HPTE_R_C ASM_CONST(0x0000000000000080) | |
98 | #define HPTE_R_R ASM_CONST(0x0000000000000100) | |
99 | ||
b7abc5c5 SS |
100 | #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000) |
101 | #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000) | |
102 | ||
8d2169e8 DG |
103 | /* Values for PP (assumes Ks=0, Kp=1) */ |
104 | /* pp0 will always be 0 for linux */ | |
105 | #define PP_RWXX 0 /* Supervisor read/write, User none */ | |
106 | #define PP_RWRX 1 /* Supervisor read/write, User read */ | |
107 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ | |
108 | #define PP_RXRX 3 /* Supervisor read, User read */ | |
109 | ||
110 | #ifndef __ASSEMBLY__ | |
111 | ||
8e561e7e | 112 | struct hash_pte { |
8d2169e8 DG |
113 | unsigned long v; |
114 | unsigned long r; | |
8e561e7e | 115 | }; |
8d2169e8 | 116 | |
8e561e7e | 117 | extern struct hash_pte *htab_address; |
8d2169e8 DG |
118 | extern unsigned long htab_size_bytes; |
119 | extern unsigned long htab_hash_mask; | |
120 | ||
121 | /* | |
122 | * Page size definition | |
123 | * | |
124 | * shift : is the "PAGE_SHIFT" value for that page size | |
125 | * sllp : is a bit mask with the value of SLB L || LP to be or'ed | |
126 | * directly to a slbmte "vsid" value | |
127 | * penc : is the HPTE encoding mask for the "LP" field: | |
128 | * | |
129 | */ | |
130 | struct mmu_psize_def | |
131 | { | |
132 | unsigned int shift; /* number of bits */ | |
133 | unsigned int penc; /* HPTE encoding */ | |
134 | unsigned int tlbiel; /* tlbiel supported for that page size */ | |
135 | unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ | |
136 | unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ | |
137 | }; | |
138 | ||
139 | #endif /* __ASSEMBLY__ */ | |
140 | ||
141 | /* | |
142 | * The kernel use the constants below to index in the page sizes array. | |
143 | * The use of fixed constants for this purpose is better for performances | |
144 | * of the low level hash refill handlers. | |
145 | * | |
146 | * A non supported page size has a "shift" field set to 0 | |
147 | * | |
148 | * Any new page size being implemented can get a new entry in here. Whether | |
149 | * the kernel will use it or not is a different matter though. The actual page | |
150 | * size used by hugetlbfs is not defined here and may be made variable | |
151 | */ | |
152 | ||
153 | #define MMU_PAGE_4K 0 /* 4K */ | |
154 | #define MMU_PAGE_64K 1 /* 64K */ | |
155 | #define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */ | |
156 | #define MMU_PAGE_1M 3 /* 1M */ | |
157 | #define MMU_PAGE_16M 4 /* 16M */ | |
158 | #define MMU_PAGE_16G 5 /* 16G */ | |
159 | #define MMU_PAGE_COUNT 6 | |
160 | ||
2454c7e9 PM |
161 | /* |
162 | * Segment sizes. | |
163 | * These are the values used by hardware in the B field of | |
164 | * SLB entries and the first dword of MMU hashtable entries. | |
165 | * The B field is 2 bits; the values 2 and 3 are unused and reserved. | |
166 | */ | |
167 | #define MMU_SEGSIZE_256M 0 | |
168 | #define MMU_SEGSIZE_1T 1 | |
169 | ||
1189be65 | 170 | |
8d2169e8 DG |
171 | #ifndef __ASSEMBLY__ |
172 | ||
173 | /* | |
1189be65 | 174 | * The current system page and segment sizes |
8d2169e8 DG |
175 | */ |
176 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
177 | extern int mmu_linear_psize; | |
178 | extern int mmu_virtual_psize; | |
179 | extern int mmu_vmalloc_psize; | |
180 | extern int mmu_io_psize; | |
1189be65 PM |
181 | extern int mmu_kernel_ssize; |
182 | extern int mmu_highuser_ssize; | |
584f8b71 | 183 | extern u16 mmu_slb_size; |
8d2169e8 DG |
184 | |
185 | /* | |
186 | * If the processor supports 64k normal pages but not 64k cache | |
187 | * inhibited pages, we have to be prepared to switch processes | |
188 | * to use 4k pages when they create cache-inhibited mappings. | |
189 | * If this is the case, mmu_ci_restrictions will be set to 1. | |
190 | */ | |
191 | extern int mmu_ci_restrictions; | |
192 | ||
193 | #ifdef CONFIG_HUGETLB_PAGE | |
194 | /* | |
195 | * The page size index of the huge pages for use by hugetlbfs | |
196 | */ | |
197 | extern int mmu_huge_psize; | |
198 | ||
199 | #endif /* CONFIG_HUGETLB_PAGE */ | |
200 | ||
201 | /* | |
202 | * This function sets the AVPN and L fields of the HPTE appropriately | |
203 | * for the page size | |
204 | */ | |
1189be65 PM |
205 | static inline unsigned long hpte_encode_v(unsigned long va, int psize, |
206 | int ssize) | |
8d2169e8 | 207 | { |
1189be65 | 208 | unsigned long v; |
8d2169e8 DG |
209 | v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm); |
210 | v <<= HPTE_V_AVPN_SHIFT; | |
211 | if (psize != MMU_PAGE_4K) | |
212 | v |= HPTE_V_LARGE; | |
1189be65 | 213 | v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT; |
8d2169e8 DG |
214 | return v; |
215 | } | |
216 | ||
217 | /* | |
218 | * This function sets the ARPN, and LP fields of the HPTE appropriately | |
219 | * for the page size. We assume the pa is already "clean" that is properly | |
220 | * aligned for the requested page size | |
221 | */ | |
222 | static inline unsigned long hpte_encode_r(unsigned long pa, int psize) | |
223 | { | |
224 | unsigned long r; | |
225 | ||
226 | /* A 4K page needs no special encoding */ | |
227 | if (psize == MMU_PAGE_4K) | |
228 | return pa & HPTE_R_RPN; | |
229 | else { | |
230 | unsigned int penc = mmu_psize_defs[psize].penc; | |
231 | unsigned int shift = mmu_psize_defs[psize].shift; | |
232 | return (pa & ~((1ul << shift) - 1)) | (penc << 12); | |
233 | } | |
234 | return r; | |
235 | } | |
236 | ||
237 | /* | |
1189be65 | 238 | * Build a VA given VSID, EA and segment size |
8d2169e8 | 239 | */ |
1189be65 PM |
240 | static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid, |
241 | int ssize) | |
242 | { | |
243 | if (ssize == MMU_SEGSIZE_256M) | |
244 | return (vsid << 28) | (ea & 0xfffffffUL); | |
245 | return (vsid << 40) | (ea & 0xffffffffffUL); | |
246 | } | |
8d2169e8 | 247 | |
1189be65 PM |
248 | /* |
249 | * This hashes a virtual address | |
250 | */ | |
251 | ||
252 | static inline unsigned long hpt_hash(unsigned long va, unsigned int shift, | |
253 | int ssize) | |
8d2169e8 | 254 | { |
1189be65 PM |
255 | unsigned long hash, vsid; |
256 | ||
257 | if (ssize == MMU_SEGSIZE_256M) { | |
258 | hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift); | |
259 | } else { | |
260 | vsid = va >> 40; | |
261 | hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift); | |
262 | } | |
263 | return hash & 0x7fffffffffUL; | |
8d2169e8 DG |
264 | } |
265 | ||
266 | extern int __hash_page_4K(unsigned long ea, unsigned long access, | |
267 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
fa28237c | 268 | unsigned int local, int ssize, int subpage_prot); |
8d2169e8 DG |
269 | extern int __hash_page_64K(unsigned long ea, unsigned long access, |
270 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
1189be65 | 271 | unsigned int local, int ssize); |
8d2169e8 DG |
272 | struct mm_struct; |
273 | extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); | |
274 | extern int hash_huge_page(struct mm_struct *mm, unsigned long access, | |
275 | unsigned long ea, unsigned long vsid, int local, | |
276 | unsigned long trap); | |
277 | ||
278 | extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
279 | unsigned long pstart, unsigned long mode, | |
1189be65 | 280 | int psize, int ssize); |
4ec161cf | 281 | extern void set_huge_psize(int psize); |
fa28237c | 282 | extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); |
8d2169e8 DG |
283 | |
284 | extern void htab_initialize(void); | |
285 | extern void htab_initialize_secondary(void); | |
286 | extern void hpte_init_native(void); | |
287 | extern void hpte_init_lpar(void); | |
288 | extern void hpte_init_iSeries(void); | |
289 | extern void hpte_init_beat(void); | |
7f2c8577 | 290 | extern void hpte_init_beat_v3(void); |
8d2169e8 DG |
291 | |
292 | extern void stabs_alloc(void); | |
293 | extern void slb_initialize(void); | |
294 | extern void slb_flush_and_rebolt(void); | |
295 | extern void stab_initialize(unsigned long stab); | |
296 | ||
67439b76 | 297 | extern void slb_vmalloc_update(void); |
8d2169e8 DG |
298 | #endif /* __ASSEMBLY__ */ |
299 | ||
300 | /* | |
301 | * VSID allocation | |
302 | * | |
303 | * We first generate a 36-bit "proto-VSID". For kernel addresses this | |
304 | * is equal to the ESID, for user addresses it is: | |
305 | * (context << 15) | (esid & 0x7fff) | |
306 | * | |
307 | * The two forms are distinguishable because the top bit is 0 for user | |
308 | * addresses, whereas the top two bits are 1 for kernel addresses. | |
309 | * Proto-VSIDs with the top two bits equal to 0b10 are reserved for | |
310 | * now. | |
311 | * | |
312 | * The proto-VSIDs are then scrambled into real VSIDs with the | |
313 | * multiplicative hash: | |
314 | * | |
315 | * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS | |
316 | * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7 | |
317 | * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF | |
318 | * | |
319 | * This scramble is only well defined for proto-VSIDs below | |
320 | * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are | |
321 | * reserved. VSID_MULTIPLIER is prime, so in particular it is | |
322 | * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. | |
323 | * Because the modulus is 2^n-1 we can compute it efficiently without | |
324 | * a divide or extra multiply (see below). | |
325 | * | |
326 | * This scheme has several advantages over older methods: | |
327 | * | |
328 | * - We have VSIDs allocated for every kernel address | |
329 | * (i.e. everything above 0xC000000000000000), except the very top | |
330 | * segment, which simplifies several things. | |
331 | * | |
332 | * - We allow for 15 significant bits of ESID and 20 bits of | |
333 | * context for user addresses. i.e. 8T (43 bits) of address space for | |
334 | * up to 1M contexts (although the page table structure and context | |
335 | * allocation will need changes to take advantage of this). | |
336 | * | |
337 | * - The scramble function gives robust scattering in the hash | |
338 | * table (at least based on some initial results). The previous | |
339 | * method was more susceptible to pathological cases giving excessive | |
340 | * hash collisions. | |
341 | */ | |
342 | /* | |
343 | * WARNING - If you change these you must make sure the asm | |
344 | * implementations in slb_allocate (slb_low.S), do_stab_bolted | |
345 | * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly. | |
346 | * | |
347 | * You'll also need to change the precomputed VSID values in head.S | |
348 | * which are used by the iSeries firmware. | |
349 | */ | |
350 | ||
1189be65 PM |
351 | #define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */ |
352 | #define VSID_BITS_256M 36 | |
353 | #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1) | |
8d2169e8 | 354 | |
1189be65 PM |
355 | #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ |
356 | #define VSID_BITS_1T 24 | |
357 | #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1) | |
358 | ||
359 | #define CONTEXT_BITS 19 | |
360 | #define USER_ESID_BITS 16 | |
361 | #define USER_ESID_BITS_1T 4 | |
8d2169e8 DG |
362 | |
363 | #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT)) | |
364 | ||
365 | /* | |
366 | * This macro generates asm code to compute the VSID scramble | |
367 | * function. Used in slb_allocate() and do_stab_bolted. The function | |
368 | * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS | |
369 | * | |
370 | * rt = register continaing the proto-VSID and into which the | |
371 | * VSID will be stored | |
372 | * rx = scratch register (clobbered) | |
373 | * | |
374 | * - rt and rx must be different registers | |
1189be65 | 375 | * - The answer will end up in the low VSID_BITS bits of rt. The higher |
8d2169e8 DG |
376 | * bits may contain other garbage, so you may need to mask the |
377 | * result. | |
378 | */ | |
1189be65 PM |
379 | #define ASM_VSID_SCRAMBLE(rt, rx, size) \ |
380 | lis rx,VSID_MULTIPLIER_##size@h; \ | |
381 | ori rx,rx,VSID_MULTIPLIER_##size@l; \ | |
8d2169e8 DG |
382 | mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \ |
383 | \ | |
1189be65 PM |
384 | srdi rx,rt,VSID_BITS_##size; \ |
385 | clrldi rt,rt,(64-VSID_BITS_##size); \ | |
8d2169e8 DG |
386 | add rt,rt,rx; /* add high and low bits */ \ |
387 | /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \ | |
388 | * 2^36-1+2^28-1. That in particular means that if r3 >= \ | |
389 | * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \ | |
390 | * the bit clear, r3 already has the answer we want, if it \ | |
391 | * doesn't, the answer is the low 36 bits of r3+1. So in all \ | |
392 | * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\ | |
393 | addi rx,rt,1; \ | |
1189be65 | 394 | srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \ |
8d2169e8 DG |
395 | add rt,rt,rx |
396 | ||
397 | ||
398 | #ifndef __ASSEMBLY__ | |
399 | ||
400 | typedef unsigned long mm_context_id_t; | |
401 | ||
402 | typedef struct { | |
403 | mm_context_id_t id; | |
d0f13e3c BH |
404 | u16 user_psize; /* page size index */ |
405 | ||
406 | #ifdef CONFIG_PPC_MM_SLICES | |
407 | u64 low_slices_psize; /* SLB page size encodings */ | |
408 | u64 high_slices_psize; /* 4 bits per slice for now */ | |
409 | #else | |
410 | u16 sllp; /* SLB page size encoding */ | |
8d2169e8 DG |
411 | #endif |
412 | unsigned long vdso_base; | |
413 | } mm_context_t; | |
414 | ||
415 | ||
8d2169e8 | 416 | #if 0 |
1189be65 PM |
417 | /* |
418 | * The code below is equivalent to this function for arguments | |
419 | * < 2^VSID_BITS, which is all this should ever be called | |
420 | * with. However gcc is not clever enough to compute the | |
421 | * modulus (2^n-1) without a second multiply. | |
422 | */ | |
423 | #define vsid_scrample(protovsid, size) \ | |
424 | ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size)) | |
8d2169e8 | 425 | |
1189be65 PM |
426 | #else /* 1 */ |
427 | #define vsid_scramble(protovsid, size) \ | |
428 | ({ \ | |
429 | unsigned long x; \ | |
430 | x = (protovsid) * VSID_MULTIPLIER_##size; \ | |
431 | x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \ | |
432 | (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \ | |
433 | }) | |
8d2169e8 | 434 | #endif /* 1 */ |
8d2169e8 DG |
435 | |
436 | /* This is only valid for addresses >= KERNELBASE */ | |
1189be65 | 437 | static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize) |
8d2169e8 | 438 | { |
1189be65 PM |
439 | if (ssize == MMU_SEGSIZE_256M) |
440 | return vsid_scramble(ea >> SID_SHIFT, 256M); | |
441 | return vsid_scramble(ea >> SID_SHIFT_1T, 1T); | |
8d2169e8 DG |
442 | } |
443 | ||
1189be65 PM |
444 | /* Returns the segment size indicator for a user address */ |
445 | static inline int user_segment_size(unsigned long addr) | |
8d2169e8 | 446 | { |
1189be65 PM |
447 | /* Use 1T segments if possible for addresses >= 1T */ |
448 | if (addr >= (1UL << SID_SHIFT_1T)) | |
449 | return mmu_highuser_ssize; | |
450 | return MMU_SEGSIZE_256M; | |
8d2169e8 DG |
451 | } |
452 | ||
1189be65 PM |
453 | /* This is only valid for user addresses (which are below 2^44) */ |
454 | static inline unsigned long get_vsid(unsigned long context, unsigned long ea, | |
455 | int ssize) | |
456 | { | |
457 | if (ssize == MMU_SEGSIZE_256M) | |
458 | return vsid_scramble((context << USER_ESID_BITS) | |
459 | | (ea >> SID_SHIFT), 256M); | |
460 | return vsid_scramble((context << USER_ESID_BITS_1T) | |
461 | | (ea >> SID_SHIFT_1T), 1T); | |
462 | } | |
463 | ||
464 | /* | |
465 | * This is only used on legacy iSeries in lparmap.c, | |
466 | * hence the 256MB segment assumption. | |
467 | */ | |
468 | #define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER_256M) % \ | |
469 | VSID_MODULUS_256M) | |
8d2169e8 DG |
470 | #define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea)) |
471 | ||
472 | /* Physical address used by some IO functions */ | |
473 | typedef unsigned long phys_addr_t; | |
474 | ||
475 | #endif /* __ASSEMBLY__ */ | |
476 | ||
477 | #endif /* _ASM_POWERPC_MMU_HASH64_H_ */ |