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bbeb3f4c SR |
1 | #ifndef _ASM_POWERPC_MPIC_H |
2 | #define _ASM_POWERPC_MPIC_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
bbeb3f4c | 4 | |
14cf11af | 5 | #include <linux/irq.h> |
3669e930 | 6 | #include <linux/sysdev.h> |
fbf0274e | 7 | #include <asm/dcr.h> |
14cf11af PM |
8 | |
9 | /* | |
10 | * Global registers | |
11 | */ | |
12 | ||
13 | #define MPIC_GREG_BASE 0x01000 | |
14 | ||
15 | #define MPIC_GREG_FEATURE_0 0x00000 | |
16 | #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000 | |
17 | #define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16 | |
18 | #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00 | |
19 | #define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8 | |
20 | #define MPIC_GREG_FEATURE_VERSION_MASK 0xff | |
21 | #define MPIC_GREG_FEATURE_1 0x00010 | |
22 | #define MPIC_GREG_GLOBAL_CONF_0 0x00020 | |
23 | #define MPIC_GREG_GCONF_RESET 0x80000000 | |
24 | #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 | |
d87bf3be | 25 | #define MPIC_GREG_GCONF_NO_BIAS 0x10000000 |
14cf11af | 26 | #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff |
f365355e | 27 | #define MPIC_GREG_GCONF_MCK 0x08000000 |
14cf11af | 28 | #define MPIC_GREG_GLOBAL_CONF_1 0x00030 |
868ea0c9 MG |
29 | #define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000 |
30 | #define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000 | |
31 | #define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \ | |
32 | (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK) | |
14cf11af PM |
33 | #define MPIC_GREG_VENDOR_0 0x00040 |
34 | #define MPIC_GREG_VENDOR_1 0x00050 | |
35 | #define MPIC_GREG_VENDOR_2 0x00060 | |
36 | #define MPIC_GREG_VENDOR_3 0x00070 | |
37 | #define MPIC_GREG_VENDOR_ID 0x00080 | |
38 | #define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000 | |
39 | #define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16 | |
40 | #define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 | |
41 | #define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8 | |
42 | #define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff | |
43 | #define MPIC_GREG_PROCESSOR_INIT 0x00090 | |
44 | #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0 | |
45 | #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 | |
46 | #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 | |
47 | #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 | |
7233593b | 48 | #define MPIC_GREG_IPI_STRIDE 0x10 |
14cf11af PM |
49 | #define MPIC_GREG_SPURIOUS 0x000e0 |
50 | #define MPIC_GREG_TIMER_FREQ 0x000f0 | |
51 | ||
52 | /* | |
53 | * | |
54 | * Timer registers | |
55 | */ | |
56 | #define MPIC_TIMER_BASE 0x01100 | |
57 | #define MPIC_TIMER_STRIDE 0x40 | |
58 | ||
59 | #define MPIC_TIMER_CURRENT_CNT 0x00000 | |
60 | #define MPIC_TIMER_BASE_CNT 0x00010 | |
61 | #define MPIC_TIMER_VECTOR_PRI 0x00020 | |
62 | #define MPIC_TIMER_DESTINATION 0x00030 | |
63 | ||
64 | /* | |
65 | * Per-Processor registers | |
66 | */ | |
67 | ||
68 | #define MPIC_CPU_THISBASE 0x00000 | |
69 | #define MPIC_CPU_BASE 0x20000 | |
70 | #define MPIC_CPU_STRIDE 0x01000 | |
71 | ||
72 | #define MPIC_CPU_IPI_DISPATCH_0 0x00040 | |
73 | #define MPIC_CPU_IPI_DISPATCH_1 0x00050 | |
74 | #define MPIC_CPU_IPI_DISPATCH_2 0x00060 | |
75 | #define MPIC_CPU_IPI_DISPATCH_3 0x00070 | |
7233593b | 76 | #define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010 |
14cf11af PM |
77 | #define MPIC_CPU_CURRENT_TASK_PRI 0x00080 |
78 | #define MPIC_CPU_TASKPRI_MASK 0x0000000f | |
79 | #define MPIC_CPU_WHOAMI 0x00090 | |
80 | #define MPIC_CPU_WHOAMI_MASK 0x0000001f | |
81 | #define MPIC_CPU_INTACK 0x000a0 | |
82 | #define MPIC_CPU_EOI 0x000b0 | |
f365355e | 83 | #define MPIC_CPU_MCACK 0x000c0 |
14cf11af PM |
84 | |
85 | /* | |
86 | * Per-source registers | |
87 | */ | |
88 | ||
89 | #define MPIC_IRQ_BASE 0x10000 | |
90 | #define MPIC_IRQ_STRIDE 0x00020 | |
91 | #define MPIC_IRQ_VECTOR_PRI 0x00000 | |
92 | #define MPIC_VECPRI_MASK 0x80000000 | |
93 | #define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */ | |
94 | #define MPIC_VECPRI_PRIORITY_MASK 0x000f0000 | |
95 | #define MPIC_VECPRI_PRIORITY_SHIFT 16 | |
96 | #define MPIC_VECPRI_VECTOR_MASK 0x000007ff | |
97 | #define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000 | |
98 | #define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000 | |
99 | #define MPIC_VECPRI_POLARITY_MASK 0x00800000 | |
100 | #define MPIC_VECPRI_SENSE_LEVEL 0x00400000 | |
101 | #define MPIC_VECPRI_SENSE_EDGE 0x00000000 | |
102 | #define MPIC_VECPRI_SENSE_MASK 0x00400000 | |
103 | #define MPIC_IRQ_DESTINATION 0x00010 | |
104 | ||
105 | #define MPIC_MAX_IRQ_SOURCES 2048 | |
106 | #define MPIC_MAX_CPUS 32 | |
107 | #define MPIC_MAX_ISU 32 | |
108 | ||
7233593b ZR |
109 | /* |
110 | * Tsi108 implementation of MPIC has many differences from the original one | |
111 | */ | |
112 | ||
113 | /* | |
114 | * Global registers | |
115 | */ | |
116 | ||
117 | #define TSI108_GREG_BASE 0x00000 | |
118 | #define TSI108_GREG_FEATURE_0 0x00000 | |
119 | #define TSI108_GREG_GLOBAL_CONF_0 0x00004 | |
120 | #define TSI108_GREG_VENDOR_ID 0x0000c | |
121 | #define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */ | |
122 | #define TSI108_GREG_IPI_STRIDE 0x0c | |
123 | #define TSI108_GREG_SPURIOUS 0x00010 | |
124 | #define TSI108_GREG_TIMER_FREQ 0x00014 | |
125 | ||
126 | /* | |
127 | * Timer registers | |
128 | */ | |
129 | #define TSI108_TIMER_BASE 0x0030 | |
130 | #define TSI108_TIMER_STRIDE 0x10 | |
131 | #define TSI108_TIMER_CURRENT_CNT 0x00000 | |
132 | #define TSI108_TIMER_BASE_CNT 0x00004 | |
133 | #define TSI108_TIMER_VECTOR_PRI 0x00008 | |
134 | #define TSI108_TIMER_DESTINATION 0x0000c | |
135 | ||
136 | /* | |
137 | * Per-Processor registers | |
138 | */ | |
139 | #define TSI108_CPU_BASE 0x00300 | |
140 | #define TSI108_CPU_STRIDE 0x00040 | |
141 | #define TSI108_CPU_IPI_DISPATCH_0 0x00200 | |
142 | #define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000 | |
143 | #define TSI108_CPU_CURRENT_TASK_PRI 0x00000 | |
144 | #define TSI108_CPU_WHOAMI 0xffffffff | |
145 | #define TSI108_CPU_INTACK 0x00004 | |
146 | #define TSI108_CPU_EOI 0x00008 | |
f365355e | 147 | #define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */ |
7233593b ZR |
148 | |
149 | /* | |
150 | * Per-source registers | |
151 | */ | |
152 | #define TSI108_IRQ_BASE 0x00100 | |
153 | #define TSI108_IRQ_STRIDE 0x00008 | |
154 | #define TSI108_IRQ_VECTOR_PRI 0x00000 | |
155 | #define TSI108_VECPRI_VECTOR_MASK 0x000000ff | |
156 | #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000 | |
157 | #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000 | |
158 | #define TSI108_VECPRI_SENSE_LEVEL 0x02000000 | |
159 | #define TSI108_VECPRI_SENSE_EDGE 0x00000000 | |
160 | #define TSI108_VECPRI_POLARITY_MASK 0x01000000 | |
161 | #define TSI108_VECPRI_SENSE_MASK 0x02000000 | |
162 | #define TSI108_IRQ_DESTINATION 0x00004 | |
163 | ||
164 | /* weird mpic register indices and mask bits in the HW info array */ | |
165 | enum { | |
166 | MPIC_IDX_GREG_BASE = 0, | |
167 | MPIC_IDX_GREG_FEATURE_0, | |
168 | MPIC_IDX_GREG_GLOBAL_CONF_0, | |
169 | MPIC_IDX_GREG_VENDOR_ID, | |
170 | MPIC_IDX_GREG_IPI_VECTOR_PRI_0, | |
171 | MPIC_IDX_GREG_IPI_STRIDE, | |
172 | MPIC_IDX_GREG_SPURIOUS, | |
173 | MPIC_IDX_GREG_TIMER_FREQ, | |
174 | ||
175 | MPIC_IDX_TIMER_BASE, | |
176 | MPIC_IDX_TIMER_STRIDE, | |
177 | MPIC_IDX_TIMER_CURRENT_CNT, | |
178 | MPIC_IDX_TIMER_BASE_CNT, | |
179 | MPIC_IDX_TIMER_VECTOR_PRI, | |
180 | MPIC_IDX_TIMER_DESTINATION, | |
181 | ||
182 | MPIC_IDX_CPU_BASE, | |
183 | MPIC_IDX_CPU_STRIDE, | |
184 | MPIC_IDX_CPU_IPI_DISPATCH_0, | |
185 | MPIC_IDX_CPU_IPI_DISPATCH_STRIDE, | |
186 | MPIC_IDX_CPU_CURRENT_TASK_PRI, | |
187 | MPIC_IDX_CPU_WHOAMI, | |
188 | MPIC_IDX_CPU_INTACK, | |
189 | MPIC_IDX_CPU_EOI, | |
f365355e | 190 | MPIC_IDX_CPU_MCACK, |
7233593b ZR |
191 | |
192 | MPIC_IDX_IRQ_BASE, | |
193 | MPIC_IDX_IRQ_STRIDE, | |
194 | MPIC_IDX_IRQ_VECTOR_PRI, | |
195 | ||
196 | MPIC_IDX_VECPRI_VECTOR_MASK, | |
197 | MPIC_IDX_VECPRI_POLARITY_POSITIVE, | |
198 | MPIC_IDX_VECPRI_POLARITY_NEGATIVE, | |
199 | MPIC_IDX_VECPRI_SENSE_LEVEL, | |
200 | MPIC_IDX_VECPRI_SENSE_EDGE, | |
201 | MPIC_IDX_VECPRI_POLARITY_MASK, | |
202 | MPIC_IDX_VECPRI_SENSE_MASK, | |
203 | MPIC_IDX_IRQ_DESTINATION, | |
204 | MPIC_IDX_END | |
205 | }; | |
206 | ||
207 | ||
6cfef5b2 | 208 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
209 | /* Fixup table entry */ |
210 | struct mpic_irq_fixup | |
211 | { | |
212 | u8 __iomem *base; | |
1beb6a7d | 213 | u8 __iomem *applebase; |
c4b22f26 | 214 | u32 data; |
1beb6a7d | 215 | unsigned int index; |
14cf11af | 216 | }; |
6cfef5b2 | 217 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af PM |
218 | |
219 | ||
fbf0274e BH |
220 | enum mpic_reg_type { |
221 | mpic_access_mmio_le, | |
222 | mpic_access_mmio_be, | |
223 | #ifdef CONFIG_PPC_DCR | |
224 | mpic_access_dcr | |
225 | #endif | |
226 | }; | |
227 | ||
228 | struct mpic_reg_bank { | |
229 | u32 __iomem *base; | |
230 | #ifdef CONFIG_PPC_DCR | |
231 | dcr_host_t dhost; | |
fbf0274e BH |
232 | #endif /* CONFIG_PPC_DCR */ |
233 | }; | |
234 | ||
3669e930 JB |
235 | struct mpic_irq_save { |
236 | u32 vecprio, | |
237 | dest; | |
238 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
239 | u32 fixup_data; | |
240 | #endif | |
241 | }; | |
242 | ||
14cf11af PM |
243 | /* The instance data of a given MPIC */ |
244 | struct mpic | |
245 | { | |
0ebfff14 BH |
246 | /* The remapper for this MPIC */ |
247 | struct irq_host *irqhost; | |
248 | ||
14cf11af | 249 | /* The "linux" controller struct */ |
b9e5b4e6 | 250 | struct irq_chip hc_irq; |
6cfef5b2 | 251 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 BH |
252 | struct irq_chip hc_ht_irq; |
253 | #endif | |
14cf11af | 254 | #ifdef CONFIG_SMP |
b9e5b4e6 | 255 | struct irq_chip hc_ipi; |
14cf11af PM |
256 | #endif |
257 | const char *name; | |
258 | /* Flags */ | |
259 | unsigned int flags; | |
260 | /* How many irq sources in a given ISU */ | |
261 | unsigned int isu_size; | |
262 | unsigned int isu_shift; | |
263 | unsigned int isu_mask; | |
14cf11af | 264 | unsigned int irq_count; |
14cf11af PM |
265 | /* Number of sources */ |
266 | unsigned int num_sources; | |
267 | /* Number of CPUs */ | |
268 | unsigned int num_cpus; | |
0ebfff14 | 269 | /* default senses array */ |
14cf11af PM |
270 | unsigned char *senses; |
271 | unsigned int senses_count; | |
272 | ||
7df2457d OJ |
273 | /* vector numbers used for internal sources (ipi/timers) */ |
274 | unsigned int ipi_vecs[4]; | |
275 | unsigned int timer_vecs[4]; | |
276 | ||
277 | /* Spurious vector to program into unused sources */ | |
278 | unsigned int spurious_vec; | |
279 | ||
6cfef5b2 | 280 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
281 | /* The fixup table */ |
282 | struct mpic_irq_fixup *fixups; | |
283 | spinlock_t fixup_lock; | |
284 | #endif | |
285 | ||
fbf0274e BH |
286 | /* Register access method */ |
287 | enum mpic_reg_type reg_type; | |
288 | ||
14cf11af | 289 | /* The various ioremap'ed bases */ |
fbf0274e BH |
290 | struct mpic_reg_bank gregs; |
291 | struct mpic_reg_bank tmregs; | |
292 | struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS]; | |
293 | struct mpic_reg_bank isus[MPIC_MAX_ISU]; | |
294 | ||
7fd72186 BH |
295 | /* Protected sources */ |
296 | unsigned long *protected; | |
297 | ||
7233593b ZR |
298 | #ifdef CONFIG_MPIC_WEIRD |
299 | /* Pointer to HW info array */ | |
300 | u32 *hw_set; | |
301 | #endif | |
302 | ||
a7de7c74 ME |
303 | #ifdef CONFIG_PCI_MSI |
304 | spinlock_t bitmap_lock; | |
305 | unsigned long *hwirq_bitmap; | |
306 | #endif | |
307 | ||
0d72ba93 OJ |
308 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
309 | u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES]; | |
310 | #endif | |
311 | ||
14cf11af PM |
312 | /* link */ |
313 | struct mpic *next; | |
3669e930 JB |
314 | |
315 | struct sys_device sysdev; | |
316 | ||
317 | #ifdef CONFIG_PM | |
318 | struct mpic_irq_save *save_data; | |
319 | #endif | |
14cf11af PM |
320 | }; |
321 | ||
7233593b ZR |
322 | /* |
323 | * MPIC flags (passed to mpic_alloc) | |
324 | * | |
325 | * The top 4 bits contain an MPIC bhw id that is used to index the | |
326 | * register offsets and some masks when CONFIG_MPIC_WEIRD is set. | |
327 | * Note setting any ID (leaving those bits to 0) means standard MPIC | |
328 | */ | |
329 | ||
14cf11af PM |
330 | /* This is the primary controller, only that one has IPIs and |
331 | * has afinity control. A non-primary MPIC always uses CPU0 | |
332 | * registers only | |
333 | */ | |
334 | #define MPIC_PRIMARY 0x00000001 | |
7233593b | 335 | |
14cf11af PM |
336 | /* Set this for a big-endian MPIC */ |
337 | #define MPIC_BIG_ENDIAN 0x00000002 | |
338 | /* Broken U3 MPIC */ | |
6cfef5b2 | 339 | #define MPIC_U3_HT_IRQS 0x00000004 |
14cf11af PM |
340 | /* Broken IPI registers (autodetected) */ |
341 | #define MPIC_BROKEN_IPI 0x00000008 | |
342 | /* MPIC wants a reset */ | |
343 | #define MPIC_WANTS_RESET 0x00000010 | |
7233593b ZR |
344 | /* Spurious vector requires EOI */ |
345 | #define MPIC_SPV_EOI 0x00000020 | |
346 | /* No passthrough disable */ | |
347 | #define MPIC_NO_PTHROU_DIS 0x00000040 | |
fbf0274e BH |
348 | /* DCR based MPIC */ |
349 | #define MPIC_USES_DCR 0x00000080 | |
7df2457d OJ |
350 | /* MPIC has 11-bit vector fields (or larger) */ |
351 | #define MPIC_LARGE_VECTORS 0x00000100 | |
f365355e OJ |
352 | /* Enable delivery of prio 15 interrupts as MCK instead of EE */ |
353 | #define MPIC_ENABLE_MCK 0x00000200 | |
d87bf3be OJ |
354 | /* Disable bias among target selection, spread interrupts evenly */ |
355 | #define MPIC_NO_BIAS 0x00000400 | |
7233593b ZR |
356 | |
357 | /* MPIC HW modification ID */ | |
358 | #define MPIC_REGSET_MASK 0xf0000000 | |
359 | #define MPIC_REGSET(val) (((val) & 0xf ) << 28) | |
360 | #define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf) | |
361 | ||
362 | #define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */ | |
363 | #define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */ | |
14cf11af PM |
364 | |
365 | /* Allocate the controller structure and setup the linux irq descs | |
366 | * for the range if interrupts passed in. No HW initialization is | |
367 | * actually performed. | |
368 | * | |
369 | * @phys_addr: physial base address of the MPIC | |
370 | * @flags: flags, see constants above | |
371 | * @isu_size: number of interrupts in an ISU. Use 0 to use a | |
372 | * standard ISU-less setup (aka powermac) | |
373 | * @irq_offset: first irq number to assign to this mpic | |
374 | * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0 | |
375 | * to match the number of sources | |
376 | * @ipi_offset: first irq number to assign to this mpic IPI sources, | |
377 | * used only on primary mpic | |
378 | * @senses: array of sense values | |
379 | * @senses_num: number of entries in the array | |
380 | * | |
381 | * Note about the sense array. If none is passed, all interrupts are | |
6cfef5b2 | 382 | * setup to be level negative unless MPIC_U3_HT_IRQS is set in which |
14cf11af PM |
383 | * case they are edge positive (and the array is ignored anyway). |
384 | * The values in the array start at the first source of the MPIC, | |
385 | * that is senses[0] correspond to linux irq "irq_offset". | |
386 | */ | |
0ebfff14 | 387 | extern struct mpic *mpic_alloc(struct device_node *node, |
a959ff56 | 388 | phys_addr_t phys_addr, |
14cf11af PM |
389 | unsigned int flags, |
390 | unsigned int isu_size, | |
14cf11af | 391 | unsigned int irq_count, |
14cf11af PM |
392 | const char *name); |
393 | ||
394 | /* Assign ISUs, to call before mpic_init() | |
395 | * | |
396 | * @mpic: controller structure as returned by mpic_alloc() | |
397 | * @isu_num: ISU number | |
398 | * @phys_addr: physical address of the ISU | |
399 | */ | |
400 | extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 401 | phys_addr_t phys_addr); |
14cf11af | 402 | |
0ebfff14 BH |
403 | /* Set default sense codes |
404 | * | |
405 | * @mpic: controller | |
406 | * @senses: array of sense codes | |
407 | * @count: size of above array | |
408 | * | |
409 | * Optionally provide an array (indexed on hardware interrupt numbers | |
410 | * for this MPIC) of default sense codes for the chip. Those are linux | |
411 | * sense codes IRQ_TYPE_* | |
412 | * | |
413 | * The driver gets ownership of the pointer, don't dispose of it or | |
414 | * anything like that. __init only. | |
415 | */ | |
416 | extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count); | |
417 | ||
418 | ||
14cf11af PM |
419 | /* Initialize the controller. After this has been called, none of the above |
420 | * should be called again for this mpic | |
421 | */ | |
422 | extern void mpic_init(struct mpic *mpic); | |
423 | ||
14cf11af PM |
424 | /* |
425 | * All of the following functions must only be used after the | |
426 | * ISUs have been assigned and the controller fully initialized | |
427 | * with mpic_init() | |
428 | */ | |
429 | ||
430 | ||
431 | /* Change/Read the priority of an interrupt. Default is 8 for irqs and | |
432 | * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the | |
433 | * IPI number is then the offset'ed (linux irq number mapped to the IPI) | |
434 | */ | |
435 | extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri); | |
436 | extern unsigned int mpic_irq_get_priority(unsigned int irq); | |
437 | ||
438 | /* Setup a non-boot CPU */ | |
439 | extern void mpic_setup_this_cpu(void); | |
440 | ||
441 | /* Clean up for kexec (or cpu offline or ...) */ | |
442 | extern void mpic_teardown_this_cpu(int secondary); | |
443 | ||
444 | /* Get the current cpu priority for this cpu (0..15) */ | |
445 | extern int mpic_cpu_get_priority(void); | |
446 | ||
447 | /* Set the current cpu priority for this cpu */ | |
448 | extern void mpic_cpu_set_priority(int prio); | |
449 | ||
450 | /* Request IPIs on primary mpic */ | |
451 | extern void mpic_request_ipis(void); | |
452 | ||
453 | /* Send an IPI (non offseted number 0..3) */ | |
454 | extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask); | |
455 | ||
a9c59264 PM |
456 | /* Send a message (IPI) to a given target (cpu number or MSG_*) */ |
457 | void smp_mpic_message_pass(int target, int msg); | |
458 | ||
f365355e OJ |
459 | /* Unmask a specific virq */ |
460 | extern void mpic_unmask_irq(unsigned int irq); | |
461 | /* Mask a specific virq */ | |
462 | extern void mpic_mask_irq(unsigned int irq); | |
463 | /* EOI a specific virq */ | |
464 | extern void mpic_end_irq(unsigned int irq); | |
465 | ||
14cf11af | 466 | /* Fetch interrupt from a given mpic */ |
35a84c2f | 467 | extern unsigned int mpic_get_one_irq(struct mpic *mpic); |
f365355e | 468 | /* This one gets from the primary mpic */ |
35a84c2f | 469 | extern unsigned int mpic_get_irq(void); |
f365355e OJ |
470 | /* Fetch Machine Check interrupt from primary mpic */ |
471 | extern unsigned int mpic_get_mcirq(void); | |
14cf11af | 472 | |
868ea0c9 MG |
473 | /* Set the EPIC clock ratio */ |
474 | void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); | |
475 | ||
476 | /* Enable/Disable EPIC serial interrupt mode */ | |
477 | void mpic_set_serial_int(struct mpic *mpic, int enable); | |
478 | ||
88ced031 | 479 | #endif /* __KERNEL__ */ |
bbeb3f4c | 480 | #endif /* _ASM_POWERPC_MPIC_H */ |