[deliverable/linux.git] / include / asm-powerpc / mpic.h

#ifndef _ASM_POWERPC_MPIC_H
#define _ASM_POWERPC_MPIC_H
#ifdef __KERNEL__

#include <linux/irq.h>
#include <asm/dcr.h>

/*
 * Global registers
 */

#define MPIC_GREG_BASE			0x01000

#define MPIC_GREG_FEATURE_0		0x00000
#define		MPIC_GREG_FEATURE_LAST_SRC_MASK		0x07ff0000
#define		MPIC_GREG_FEATURE_LAST_SRC_SHIFT	16
#define		MPIC_GREG_FEATURE_LAST_CPU_MASK		0x00001f00
#define		MPIC_GREG_FEATURE_LAST_CPU_SHIFT	8
#define		MPIC_GREG_FEATURE_VERSION_MASK		0xff
#define MPIC_GREG_FEATURE_1		0x00010
#define MPIC_GREG_GLOBAL_CONF_0		0x00020
#define		MPIC_GREG_GCONF_RESET			0x80000000
#define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
#define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff
#define MPIC_GREG_GLOBAL_CONF_1		0x00030
#define		MPIC_GREG_GLOBAL_CONF_1_SIE		0x08000000
#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK	0x70000000
#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)	\
			(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
#define MPIC_GREG_VENDOR_0		0x00040
#define MPIC_GREG_VENDOR_1		0x00050
#define MPIC_GREG_VENDOR_2		0x00060
#define MPIC_GREG_VENDOR_3		0x00070
#define MPIC_GREG_VENDOR_ID		0x00080
#define 	MPIC_GREG_VENDOR_ID_STEPPING_MASK	0x00ff0000
#define 	MPIC_GREG_VENDOR_ID_STEPPING_SHIFT	16
#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK	0x0000ff00
#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT	8
#define 	MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK	0x000000ff
#define MPIC_GREG_PROCESSOR_INIT	0x00090
#define MPIC_GREG_IPI_VECTOR_PRI_0	0x000a0
#define MPIC_GREG_IPI_VECTOR_PRI_1	0x000b0
#define MPIC_GREG_IPI_VECTOR_PRI_2	0x000c0
#define MPIC_GREG_IPI_VECTOR_PRI_3	0x000d0
#define MPIC_GREG_IPI_STRIDE		0x10
#define MPIC_GREG_SPURIOUS		0x000e0
#define MPIC_GREG_TIMER_FREQ		0x000f0

/*
 *
 * Timer registers
 */
#define MPIC_TIMER_BASE			0x01100
#define MPIC_TIMER_STRIDE		0x40

#define MPIC_TIMER_CURRENT_CNT		0x00000
#define MPIC_TIMER_BASE_CNT		0x00010
#define MPIC_TIMER_VECTOR_PRI		0x00020
#define MPIC_TIMER_DESTINATION		0x00030

/*
 * Per-Processor registers
 */

#define MPIC_CPU_THISBASE		0x00000
#define MPIC_CPU_BASE			0x20000
#define MPIC_CPU_STRIDE			0x01000

#define MPIC_CPU_IPI_DISPATCH_0		0x00040
#define MPIC_CPU_IPI_DISPATCH_1		0x00050
#define MPIC_CPU_IPI_DISPATCH_2		0x00060
#define MPIC_CPU_IPI_DISPATCH_3		0x00070
#define MPIC_CPU_IPI_DISPATCH_STRIDE	0x00010
#define MPIC_CPU_CURRENT_TASK_PRI	0x00080
#define 	MPIC_CPU_TASKPRI_MASK			0x0000000f
#define MPIC_CPU_WHOAMI			0x00090
#define 	MPIC_CPU_WHOAMI_MASK			0x0000001f
#define MPIC_CPU_INTACK			0x000a0
#define MPIC_CPU_EOI			0x000b0

/*
 * Per-source registers
 */

#define MPIC_IRQ_BASE			0x10000
#define MPIC_IRQ_STRIDE			0x00020
#define MPIC_IRQ_VECTOR_PRI		0x00000
#define 	MPIC_VECPRI_MASK			0x80000000
#define 	MPIC_VECPRI_ACTIVITY			0x40000000	/* Read Only */
#define 	MPIC_VECPRI_PRIORITY_MASK		0x000f0000
#define 	MPIC_VECPRI_PRIORITY_SHIFT		16
#define 	MPIC_VECPRI_VECTOR_MASK			0x000007ff
#define 	MPIC_VECPRI_POLARITY_POSITIVE		0x00800000
#define 	MPIC_VECPRI_POLARITY_NEGATIVE		0x00000000
#define 	MPIC_VECPRI_POLARITY_MASK		0x00800000
#define 	MPIC_VECPRI_SENSE_LEVEL			0x00400000
#define 	MPIC_VECPRI_SENSE_EDGE			0x00000000
#define 	MPIC_VECPRI_SENSE_MASK			0x00400000
#define MPIC_IRQ_DESTINATION		0x00010

#define MPIC_MAX_IRQ_SOURCES	2048
#define MPIC_MAX_CPUS		32
#define MPIC_MAX_ISU		32

/*
 * Tsi108 implementation of MPIC has many differences from the original one
 */

/*
 * Global registers
 */

#define TSI108_GREG_BASE		0x00000
#define TSI108_GREG_FEATURE_0		0x00000
#define TSI108_GREG_GLOBAL_CONF_0	0x00004
#define TSI108_GREG_VENDOR_ID		0x0000c
#define TSI108_GREG_IPI_VECTOR_PRI_0	0x00204		/* Doorbell 0 */
#define TSI108_GREG_IPI_STRIDE		0x0c
#define TSI108_GREG_SPURIOUS		0x00010
#define TSI108_GREG_TIMER_FREQ		0x00014

/*
 * Timer registers
 */
#define TSI108_TIMER_BASE		0x0030
#define TSI108_TIMER_STRIDE		0x10
#define TSI108_TIMER_CURRENT_CNT	0x00000
#define TSI108_TIMER_BASE_CNT		0x00004
#define TSI108_TIMER_VECTOR_PRI		0x00008
#define TSI108_TIMER_DESTINATION	0x0000c

/*
 * Per-Processor registers
 */
#define TSI108_CPU_BASE			0x00300
#define TSI108_CPU_STRIDE		0x00040
#define TSI108_CPU_IPI_DISPATCH_0	0x00200
#define TSI108_CPU_IPI_DISPATCH_STRIDE	0x00000
#define TSI108_CPU_CURRENT_TASK_PRI	0x00000
#define TSI108_CPU_WHOAMI		0xffffffff
#define TSI108_CPU_INTACK		0x00004
#define TSI108_CPU_EOI			0x00008

/*
 * Per-source registers
 */
#define TSI108_IRQ_BASE			0x00100
#define TSI108_IRQ_STRIDE		0x00008
#define TSI108_IRQ_VECTOR_PRI		0x00000
#define TSI108_VECPRI_VECTOR_MASK	0x000000ff
#define TSI108_VECPRI_POLARITY_POSITIVE	0x01000000
#define TSI108_VECPRI_POLARITY_NEGATIVE	0x00000000
#define TSI108_VECPRI_SENSE_LEVEL	0x02000000
#define TSI108_VECPRI_SENSE_EDGE	0x00000000
#define TSI108_VECPRI_POLARITY_MASK	0x01000000
#define TSI108_VECPRI_SENSE_MASK	0x02000000
#define TSI108_IRQ_DESTINATION		0x00004

/* weird mpic register indices and mask bits in the HW info array */
enum {
	MPIC_IDX_GREG_BASE = 0,
	MPIC_IDX_GREG_FEATURE_0,
	MPIC_IDX_GREG_GLOBAL_CONF_0,
	MPIC_IDX_GREG_VENDOR_ID,
	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
	MPIC_IDX_GREG_IPI_STRIDE,
	MPIC_IDX_GREG_SPURIOUS,
	MPIC_IDX_GREG_TIMER_FREQ,

	MPIC_IDX_TIMER_BASE,
	MPIC_IDX_TIMER_STRIDE,
	MPIC_IDX_TIMER_CURRENT_CNT,
	MPIC_IDX_TIMER_BASE_CNT,
	MPIC_IDX_TIMER_VECTOR_PRI,
	MPIC_IDX_TIMER_DESTINATION,

	MPIC_IDX_CPU_BASE,
	MPIC_IDX_CPU_STRIDE,
	MPIC_IDX_CPU_IPI_DISPATCH_0,
	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
	MPIC_IDX_CPU_CURRENT_TASK_PRI,
	MPIC_IDX_CPU_WHOAMI,
	MPIC_IDX_CPU_INTACK,
	MPIC_IDX_CPU_EOI,

	MPIC_IDX_IRQ_BASE,
	MPIC_IDX_IRQ_STRIDE,
	MPIC_IDX_IRQ_VECTOR_PRI,

	MPIC_IDX_VECPRI_VECTOR_MASK,
	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
	MPIC_IDX_VECPRI_SENSE_LEVEL,
	MPIC_IDX_VECPRI_SENSE_EDGE,
	MPIC_IDX_VECPRI_POLARITY_MASK,
	MPIC_IDX_VECPRI_SENSE_MASK,
	MPIC_IDX_IRQ_DESTINATION,
	MPIC_IDX_END
};


#ifdef CONFIG_MPIC_U3_HT_IRQS
/* Fixup table entry */
struct mpic_irq_fixup
{
	u8 __iomem	*base;
	u8 __iomem	*applebase;
	u32		data;
	unsigned int	index;
};
#endif /* CONFIG_MPIC_U3_HT_IRQS */


enum mpic_reg_type {
	mpic_access_mmio_le,
	mpic_access_mmio_be,
#ifdef CONFIG_PPC_DCR
	mpic_access_dcr
#endif
};

struct mpic_reg_bank {
	u32 __iomem	*base;
#ifdef CONFIG_PPC_DCR
	dcr_host_t	dhost;
	unsigned int	dbase;
	unsigned int	doff;
#endif /* CONFIG_PPC_DCR */
};

/* The instance data of a given MPIC */
struct mpic
{
	/* The device node of the interrupt controller */
	struct device_node	*of_node;

	/* The remapper for this MPIC */
	struct irq_host		*irqhost;

	/* The "linux" controller struct */
	struct irq_chip		hc_irq;
#ifdef CONFIG_MPIC_U3_HT_IRQS
	struct irq_chip		hc_ht_irq;
#endif
#ifdef CONFIG_SMP
	struct irq_chip		hc_ipi;
#endif
	const char		*name;
	/* Flags */
	unsigned int		flags;
	/* How many irq sources in a given ISU */
	unsigned int		isu_size;
	unsigned int		isu_shift;
	unsigned int		isu_mask;
	unsigned int		irq_count;
	/* Number of sources */
	unsigned int		num_sources;
	/* Number of CPUs */
	unsigned int		num_cpus;
	/* default senses array */
	unsigned char		*senses;
	unsigned int		senses_count;

	/* vector numbers used for internal sources (ipi/timers) */
	unsigned int		ipi_vecs[4];
	unsigned int		timer_vecs[4];

	/* Spurious vector to program into unused sources */
	unsigned int		spurious_vec;

#ifdef CONFIG_MPIC_U3_HT_IRQS
	/* The fixup table */
	struct mpic_irq_fixup	*fixups;
	spinlock_t		fixup_lock;
#endif

	/* Register access method */
	enum mpic_reg_type	reg_type;

	/* The various ioremap'ed bases */
	struct mpic_reg_bank	gregs;
	struct mpic_reg_bank	tmregs;
	struct mpic_reg_bank	cpuregs[MPIC_MAX_CPUS];
	struct mpic_reg_bank	isus[MPIC_MAX_ISU];

#ifdef CONFIG_PPC_DCR
	unsigned int		dcr_base;
#endif

#ifdef CONFIG_MPIC_WEIRD
	/* Pointer to HW info array */
	u32			*hw_set;
#endif

	/* link */
	struct mpic		*next;
};

/*
 * MPIC flags (passed to mpic_alloc)
 *
 * The top 4 bits contain an MPIC bhw id that is used to index the
 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
 * Note setting any ID (leaving those bits to 0) means standard MPIC
 */

/* This is the primary controller, only that one has IPIs and
 * has afinity control. A non-primary MPIC always uses CPU0
 * registers only
 */
#define MPIC_PRIMARY			0x00000001

/* Set this for a big-endian MPIC */
#define MPIC_BIG_ENDIAN			0x00000002
/* Broken U3 MPIC */
#define MPIC_U3_HT_IRQS			0x00000004
/* Broken IPI registers (autodetected) */
#define MPIC_BROKEN_IPI			0x00000008
/* MPIC wants a reset */
#define MPIC_WANTS_RESET		0x00000010
/* Spurious vector requires EOI */
#define MPIC_SPV_EOI			0x00000020
/* No passthrough disable */
#define MPIC_NO_PTHROU_DIS		0x00000040
/* DCR based MPIC */
#define MPIC_USES_DCR			0x00000080
/* MPIC has 11-bit vector fields (or larger) */
#define MPIC_LARGE_VECTORS		0x00000100

/* MPIC HW modification ID */
#define MPIC_REGSET_MASK		0xf0000000
#define MPIC_REGSET(val)		(((val) & 0xf ) << 28)
#define MPIC_GET_REGSET(flags)		(((flags) >> 28) & 0xf)

#define	MPIC_REGSET_STANDARD		MPIC_REGSET(0)	/* Original MPIC */
#define	MPIC_REGSET_TSI108		MPIC_REGSET(1)	/* Tsi108/109 PIC */

/* Allocate the controller structure and setup the linux irq descs
 * for the range if interrupts passed in. No HW initialization is
 * actually performed.
 * 
 * @phys_addr:	physial base address of the MPIC
 * @flags:	flags, see constants above
 * @isu_size:	number of interrupts in an ISU. Use 0 to use a
 *              standard ISU-less setup (aka powermac)
 * @irq_offset: first irq number to assign to this mpic
 * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 *	        to match the number of sources
 * @ipi_offset: first irq number to assign to this mpic IPI sources,
 *		used only on primary mpic
 * @senses:	array of sense values
 * @senses_num: number of entries in the array
 *
 * Note about the sense array. If none is passed, all interrupts are
 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
 * case they are edge positive (and the array is ignored anyway).
 * The values in the array start at the first source of the MPIC,
 * that is senses[0] correspond to linux irq "irq_offset".
 */
extern struct mpic *mpic_alloc(struct device_node *node,
			       phys_addr_t phys_addr,
			       unsigned int flags,
			       unsigned int isu_size,
			       unsigned int irq_count,
			       const char *name);

/* Assign ISUs, to call before mpic_init()
 *
 * @mpic:	controller structure as returned by mpic_alloc()
 * @isu_num:	ISU number
 * @phys_addr:	physical address of the ISU
 */
extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
			    phys_addr_t phys_addr);

/* Set default sense codes
 *
 * @mpic:	controller
 * @senses:	array of sense codes
 * @count:	size of above array
 *
 * Optionally provide an array (indexed on hardware interrupt numbers
 * for this MPIC) of default sense codes for the chip. Those are linux
 * sense codes IRQ_TYPE_*
 *
 * The driver gets ownership of the pointer, don't dispose of it or
 * anything like that. __init only.
 */
extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);


/* Initialize the controller. After this has been called, none of the above
 * should be called again for this mpic
 */
extern void mpic_init(struct mpic *mpic);

/*
 * All of the following functions must only be used after the
 * ISUs have been assigned and the controller fully initialized
 * with mpic_init()
 */


/* Change/Read the priority of an interrupt. Default is 8 for irqs and
 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 */
extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
extern unsigned int mpic_irq_get_priority(unsigned int irq);

/* Setup a non-boot CPU */
extern void mpic_setup_this_cpu(void);

/* Clean up for kexec (or cpu offline or ...) */
extern void mpic_teardown_this_cpu(int secondary);

/* Get the current cpu priority for this cpu (0..15) */
extern int mpic_cpu_get_priority(void);

/* Set the current cpu priority for this cpu */
extern void mpic_cpu_set_priority(int prio);

/* Request IPIs on primary mpic */
extern void mpic_request_ipis(void);

/* Send an IPI (non offseted number 0..3) */
extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);

/* Send a message (IPI) to a given target (cpu number or MSG_*) */
void smp_mpic_message_pass(int target, int msg);

/* Fetch interrupt from a given mpic */
extern unsigned int mpic_get_one_irq(struct mpic *mpic);
/* This one gets to the primary mpic */
extern unsigned int mpic_get_irq(void);

/* Set the EPIC clock ratio */
void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);

/* Enable/Disable EPIC serial interrupt mode */
void mpic_set_serial_int(struct mpic *mpic, int enable);

#endif /* __KERNEL__ */
#endif	/* _ASM_POWERPC_MPIC_H */
Commit	Line	Data
bbeb3f4c SR	1	#ifndef _ASM_POWERPC_MPIC_H
bbeb3f4c SR	2	#define _ASM_POWERPC_MPIC_H
88ced031	3	#ifdef __KERNEL__
bbeb3f4c	4
14cf11af	5	#include <linux/irq.h>
fbf0274e	6	#include <asm/dcr.h>
14cf11af PM	7
	8	/*
	9	* Global registers
	10	*/
	11
	12	#define MPIC_GREG_BASE 0x01000
	13
	14	#define MPIC_GREG_FEATURE_0 0x00000
	15	#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
	16	#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
	17	#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
	18	#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
	19	#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
	20	#define MPIC_GREG_FEATURE_1 0x00010
	21	#define MPIC_GREG_GLOBAL_CONF_0 0x00020
	22	#define MPIC_GREG_GCONF_RESET 0x80000000
	23	#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
	24	#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
	25	#define MPIC_GREG_GLOBAL_CONF_1 0x00030
868ea0c9 MG	26	#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
	27	#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
	28	#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
	29	(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
14cf11af PM	30	#define MPIC_GREG_VENDOR_0 0x00040
	31	#define MPIC_GREG_VENDOR_1 0x00050
	32	#define MPIC_GREG_VENDOR_2 0x00060
	33	#define MPIC_GREG_VENDOR_3 0x00070
	34	#define MPIC_GREG_VENDOR_ID 0x00080
	35	#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
	36	#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
	37	#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
	38	#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
	39	#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
	40	#define MPIC_GREG_PROCESSOR_INIT 0x00090
	41	#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
	42	#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
	43	#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
	44	#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
7233593b	45	#define MPIC_GREG_IPI_STRIDE 0x10
14cf11af PM	46	#define MPIC_GREG_SPURIOUS 0x000e0
	47	#define MPIC_GREG_TIMER_FREQ 0x000f0
	48
	49	/*
	50	*
	51	* Timer registers
	52	*/
	53	#define MPIC_TIMER_BASE 0x01100
	54	#define MPIC_TIMER_STRIDE 0x40
	55
	56	#define MPIC_TIMER_CURRENT_CNT 0x00000
	57	#define MPIC_TIMER_BASE_CNT 0x00010
	58	#define MPIC_TIMER_VECTOR_PRI 0x00020
	59	#define MPIC_TIMER_DESTINATION 0x00030
	60
	61	/*
	62	* Per-Processor registers
	63	*/
	64
	65	#define MPIC_CPU_THISBASE 0x00000
	66	#define MPIC_CPU_BASE 0x20000
	67	#define MPIC_CPU_STRIDE 0x01000
	68
	69	#define MPIC_CPU_IPI_DISPATCH_0 0x00040
	70	#define MPIC_CPU_IPI_DISPATCH_1 0x00050
	71	#define MPIC_CPU_IPI_DISPATCH_2 0x00060
	72	#define MPIC_CPU_IPI_DISPATCH_3 0x00070
7233593b	73	#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
14cf11af PM	74	#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
	75	#define MPIC_CPU_TASKPRI_MASK 0x0000000f
	76	#define MPIC_CPU_WHOAMI 0x00090
	77	#define MPIC_CPU_WHOAMI_MASK 0x0000001f
	78	#define MPIC_CPU_INTACK 0x000a0
	79	#define MPIC_CPU_EOI 0x000b0
	80
	81	/*
	82	* Per-source registers
	83	*/
	84
	85	#define MPIC_IRQ_BASE 0x10000
	86	#define MPIC_IRQ_STRIDE 0x00020
	87	#define MPIC_IRQ_VECTOR_PRI 0x00000
	88	#define MPIC_VECPRI_MASK 0x80000000
	89	#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
	90	#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
	91	#define MPIC_VECPRI_PRIORITY_SHIFT 16
	92	#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
	93	#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
	94	#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
	95	#define MPIC_VECPRI_POLARITY_MASK 0x00800000
	96	#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
	97	#define MPIC_VECPRI_SENSE_EDGE 0x00000000
	98	#define MPIC_VECPRI_SENSE_MASK 0x00400000
	99	#define MPIC_IRQ_DESTINATION 0x00010
	100
	101	#define MPIC_MAX_IRQ_SOURCES 2048
	102	#define MPIC_MAX_CPUS 32
	103	#define MPIC_MAX_ISU 32
	104
7233593b ZR	105	/*
	106	* Tsi108 implementation of MPIC has many differences from the original one
	107	*/
	108
	109	/*
	110	* Global registers
	111	*/
	112
	113	#define TSI108_GREG_BASE 0x00000
	114	#define TSI108_GREG_FEATURE_0 0x00000
	115	#define TSI108_GREG_GLOBAL_CONF_0 0x00004
	116	#define TSI108_GREG_VENDOR_ID 0x0000c
	117	#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
	118	#define TSI108_GREG_IPI_STRIDE 0x0c
	119	#define TSI108_GREG_SPURIOUS 0x00010
	120	#define TSI108_GREG_TIMER_FREQ 0x00014
	121
	122	/*
	123	* Timer registers
	124	*/
	125	#define TSI108_TIMER_BASE 0x0030
	126	#define TSI108_TIMER_STRIDE 0x10
	127	#define TSI108_TIMER_CURRENT_CNT 0x00000
	128	#define TSI108_TIMER_BASE_CNT 0x00004
	129	#define TSI108_TIMER_VECTOR_PRI 0x00008
	130	#define TSI108_TIMER_DESTINATION 0x0000c
	131
	132	/*
	133	* Per-Processor registers
	134	*/
	135	#define TSI108_CPU_BASE 0x00300
	136	#define TSI108_CPU_STRIDE 0x00040
	137	#define TSI108_CPU_IPI_DISPATCH_0 0x00200
	138	#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
	139	#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
	140	#define TSI108_CPU_WHOAMI 0xffffffff
	141	#define TSI108_CPU_INTACK 0x00004
	142	#define TSI108_CPU_EOI 0x00008
	143
	144	/*
	145	* Per-source registers
	146	*/
	147	#define TSI108_IRQ_BASE 0x00100
	148	#define TSI108_IRQ_STRIDE 0x00008
	149	#define TSI108_IRQ_VECTOR_PRI 0x00000
	150	#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
	151	#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
	152	#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
	153	#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
	154	#define TSI108_VECPRI_SENSE_EDGE 0x00000000
	155	#define TSI108_VECPRI_POLARITY_MASK 0x01000000
	156	#define TSI108_VECPRI_SENSE_MASK 0x02000000
	157	#define TSI108_IRQ_DESTINATION 0x00004
	158
	159	/* weird mpic register indices and mask bits in the HW info array */
	160	enum {
	161	MPIC_IDX_GREG_BASE = 0,
	162	MPIC_IDX_GREG_FEATURE_0,
	163	MPIC_IDX_GREG_GLOBAL_CONF_0,
	164	MPIC_IDX_GREG_VENDOR_ID,
	165	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
	166	MPIC_IDX_GREG_IPI_STRIDE,
	167	MPIC_IDX_GREG_SPURIOUS,
	168	MPIC_IDX_GREG_TIMER_FREQ,
169
170	MPIC_IDX_TIMER_BASE,
171	MPIC_IDX_TIMER_STRIDE,
172	MPIC_IDX_TIMER_CURRENT_CNT,
173	MPIC_IDX_TIMER_BASE_CNT,
174	MPIC_IDX_TIMER_VECTOR_PRI,
175	MPIC_IDX_TIMER_DESTINATION,
176
177	MPIC_IDX_CPU_BASE,
178	MPIC_IDX_CPU_STRIDE,
179	MPIC_IDX_CPU_IPI_DISPATCH_0,
180	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
181	MPIC_IDX_CPU_CURRENT_TASK_PRI,
182	MPIC_IDX_CPU_WHOAMI,
183	MPIC_IDX_CPU_INTACK,
184	MPIC_IDX_CPU_EOI,
185
186	MPIC_IDX_IRQ_BASE,
187	MPIC_IDX_IRQ_STRIDE,
188	MPIC_IDX_IRQ_VECTOR_PRI,
189
190	MPIC_IDX_VECPRI_VECTOR_MASK,
191	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
192	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
193	MPIC_IDX_VECPRI_SENSE_LEVEL,
194	MPIC_IDX_VECPRI_SENSE_EDGE,
195	MPIC_IDX_VECPRI_POLARITY_MASK,
196	MPIC_IDX_VECPRI_SENSE_MASK,
197	MPIC_IDX_IRQ_DESTINATION,
198	MPIC_IDX_END
199	};
200
201
6cfef5b2	202	#ifdef CONFIG_MPIC_U3_HT_IRQS
14cf11af PM	203	/* Fixup table entry */
	204	struct mpic_irq_fixup
	205	{
	206	u8 __iomem *base;
1beb6a7d	207	u8 __iomem *applebase;
c4b22f26	208	u32 data;
1beb6a7d	209	unsigned int index;
14cf11af	210	};
6cfef5b2	211	#endif /* CONFIG_MPIC_U3_HT_IRQS */
14cf11af PM	212
14cf11af PM	213
fbf0274e BH	214	enum mpic_reg_type {
	215	mpic_access_mmio_le,
	216	mpic_access_mmio_be,
	217	#ifdef CONFIG_PPC_DCR
	218	mpic_access_dcr
	219	#endif
	220	};
	221
	222	struct mpic_reg_bank {
	223	u32 __iomem *base;
	224	#ifdef CONFIG_PPC_DCR
	225	dcr_host_t dhost;
	226	unsigned int dbase;
	227	unsigned int doff;
	228	#endif /* CONFIG_PPC_DCR */
	229	};
	230
14cf11af PM	231	/* The instance data of a given MPIC */
	232	struct mpic
	233	{
0ebfff14 BH	234	/* The device node of the interrupt controller */
	235	struct device_node *of_node;
	236
	237	/* The remapper for this MPIC */
	238	struct irq_host *irqhost;
	239
14cf11af	240	/* The "linux" controller struct */
b9e5b4e6	241	struct irq_chip hc_irq;
6cfef5b2	242	#ifdef CONFIG_MPIC_U3_HT_IRQS
b9e5b4e6 BH	243	struct irq_chip hc_ht_irq;
b9e5b4e6 BH	244	#endif
14cf11af	245	#ifdef CONFIG_SMP
b9e5b4e6	246	struct irq_chip hc_ipi;
14cf11af PM	247	#endif
	248	const char *name;
	249	/* Flags */
	250	unsigned int flags;
	251	/* How many irq sources in a given ISU */
	252	unsigned int isu_size;
	253	unsigned int isu_shift;
	254	unsigned int isu_mask;
14cf11af	255	unsigned int irq_count;
14cf11af PM	256	/* Number of sources */
	257	unsigned int num_sources;
	258	/* Number of CPUs */
	259	unsigned int num_cpus;
0ebfff14	260	/* default senses array */
14cf11af PM	261	unsigned char *senses;
	262	unsigned int senses_count;
	263
7df2457d OJ	264	/* vector numbers used for internal sources (ipi/timers) */
	265	unsigned int ipi_vecs[4];
	266	unsigned int timer_vecs[4];
	267
	268	/* Spurious vector to program into unused sources */
	269	unsigned int spurious_vec;
	270
6cfef5b2	271	#ifdef CONFIG_MPIC_U3_HT_IRQS
14cf11af PM	272	/* The fixup table */
	273	struct mpic_irq_fixup *fixups;
	274	spinlock_t fixup_lock;
	275	#endif
	276
fbf0274e BH	277	/* Register access method */
	278	enum mpic_reg_type reg_type;
	279
14cf11af	280	/* The various ioremap'ed bases */
fbf0274e BH	281	struct mpic_reg_bank gregs;
	282	struct mpic_reg_bank tmregs;
	283	struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
	284	struct mpic_reg_bank isus[MPIC_MAX_ISU];
	285
	286	#ifdef CONFIG_PPC_DCR
	287	unsigned int dcr_base;
	288	#endif
14cf11af	289
7233593b ZR	290	#ifdef CONFIG_MPIC_WEIRD
	291	/* Pointer to HW info array */
	292	u32 *hw_set;
	293	#endif
	294
14cf11af PM	295	/* link */
	296	struct mpic *next;
	297	};
	298
7233593b ZR	299	/*
	300	* MPIC flags (passed to mpic_alloc)
	301	*
	302	* The top 4 bits contain an MPIC bhw id that is used to index the
	303	* register offsets and some masks when CONFIG_MPIC_WEIRD is set.
	304	* Note setting any ID (leaving those bits to 0) means standard MPIC
	305	*/
	306
14cf11af PM	307	/* This is the primary controller, only that one has IPIs and
	308	* has afinity control. A non-primary MPIC always uses CPU0
	309	* registers only
	310	*/
	311	#define MPIC_PRIMARY 0x00000001
7233593b	312
14cf11af PM	313	/* Set this for a big-endian MPIC */
	314	#define MPIC_BIG_ENDIAN 0x00000002
	315	/* Broken U3 MPIC */
6cfef5b2	316	#define MPIC_U3_HT_IRQS 0x00000004
14cf11af PM	317	/* Broken IPI registers (autodetected) */
	318	#define MPIC_BROKEN_IPI 0x00000008
	319	/* MPIC wants a reset */
	320	#define MPIC_WANTS_RESET 0x00000010
7233593b ZR	321	/* Spurious vector requires EOI */
	322	#define MPIC_SPV_EOI 0x00000020
	323	/* No passthrough disable */
	324	#define MPIC_NO_PTHROU_DIS 0x00000040
fbf0274e BH	325	/* DCR based MPIC */
fbf0274e BH	326	#define MPIC_USES_DCR 0x00000080
7df2457d OJ	327	/* MPIC has 11-bit vector fields (or larger) */
7df2457d OJ	328	#define MPIC_LARGE_VECTORS 0x00000100
7233593b ZR	329
	330	/* MPIC HW modification ID */
	331	#define MPIC_REGSET_MASK 0xf0000000
	332	#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
	333	#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
	334
	335	#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
	336	#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
14cf11af PM	337
	338	/* Allocate the controller structure and setup the linux irq descs
	339	* for the range if interrupts passed in. No HW initialization is
	340	* actually performed.
	341	*
	342	* @phys_addr: physial base address of the MPIC
	343	* @flags: flags, see constants above
	344	* @isu_size: number of interrupts in an ISU. Use 0 to use a
	345	* standard ISU-less setup (aka powermac)
	346	* @irq_offset: first irq number to assign to this mpic
	347	* @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
	348	* to match the number of sources
	349	* @ipi_offset: first irq number to assign to this mpic IPI sources,
	350	* used only on primary mpic
	351	* @senses: array of sense values
	352	* @senses_num: number of entries in the array
	353	*
	354	* Note about the sense array. If none is passed, all interrupts are
6cfef5b2	355	* setup to be level negative unless MPIC_U3_HT_IRQS is set in which
14cf11af PM	356	* case they are edge positive (and the array is ignored anyway).
	357	* The values in the array start at the first source of the MPIC,
	358	* that is senses[0] correspond to linux irq "irq_offset".
	359	*/
0ebfff14	360	extern struct mpic mpic_alloc(struct device_node node,
a959ff56	361	phys_addr_t phys_addr,
14cf11af PM	362	unsigned int flags,
14cf11af PM	363	unsigned int isu_size,
14cf11af	364	unsigned int irq_count,
14cf11af PM	365	const char *name);
	366
	367	/* Assign ISUs, to call before mpic_init()
	368	*
	369	* @mpic: controller structure as returned by mpic_alloc()
	370	* @isu_num: ISU number
	371	* @phys_addr: physical address of the ISU
	372	*/
	373	extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
a959ff56	374	phys_addr_t phys_addr);
14cf11af	375
0ebfff14 BH	376	/* Set default sense codes
	377	*
	378	* @mpic: controller
	379	* @senses: array of sense codes
	380	* @count: size of above array
	381	*
	382	* Optionally provide an array (indexed on hardware interrupt numbers
	383	* for this MPIC) of default sense codes for the chip. Those are linux
	384	* sense codes IRQ_TYPE_*
	385	*
	386	* The driver gets ownership of the pointer, don't dispose of it or
	387	* anything like that. __init only.
	388	*/
	389	extern void mpic_set_default_senses(struct mpic mpic, u8 senses, int count);
	390
	391
14cf11af PM	392	/* Initialize the controller. After this has been called, none of the above
	393	* should be called again for this mpic
	394	*/
	395	extern void mpic_init(struct mpic *mpic);
	396
14cf11af PM	397	/*
	398	* All of the following functions must only be used after the
	399	* ISUs have been assigned and the controller fully initialized
	400	* with mpic_init()
	401	*/
	402
	403
	404	/* Change/Read the priority of an interrupt. Default is 8 for irqs and
	405	* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
	406	* IPI number is then the offset'ed (linux irq number mapped to the IPI)
	407	*/
	408	extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
	409	extern unsigned int mpic_irq_get_priority(unsigned int irq);
	410
	411	/* Setup a non-boot CPU */
	412	extern void mpic_setup_this_cpu(void);
	413
	414	/* Clean up for kexec (or cpu offline or ...) */
	415	extern void mpic_teardown_this_cpu(int secondary);
	416
	417	/* Get the current cpu priority for this cpu (0..15) */
	418	extern int mpic_cpu_get_priority(void);
	419
	420	/* Set the current cpu priority for this cpu */
	421	extern void mpic_cpu_set_priority(int prio);
	422
	423	/* Request IPIs on primary mpic */
	424	extern void mpic_request_ipis(void);
	425
	426	/* Send an IPI (non offseted number 0..3) */
	427	extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
	428
a9c59264 PM	429	/* Send a message (IPI) to a given target (cpu number or MSG_) /
	430	void smp_mpic_message_pass(int target, int msg);
	431
14cf11af	432	/* Fetch interrupt from a given mpic */
35a84c2f	433	extern unsigned int mpic_get_one_irq(struct mpic *mpic);
14cf11af	434	/* This one gets to the primary mpic */
35a84c2f	435	extern unsigned int mpic_get_irq(void);
14cf11af	436
868ea0c9 MG	437	/* Set the EPIC clock ratio */
	438	void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
	439
	440	/* Enable/Disable EPIC serial interrupt mode */
	441	void mpic_set_serial_int(struct mpic *mpic, int enable);
	442
88ced031	443	#endif /* __KERNEL__ */
bbeb3f4c	444	#endif /* _ASM_POWERPC_MPIC_H */