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f8ef2705 PM |
1 | #ifndef __ASM_POWERPC_PCI_H |
2 | #define __ASM_POWERPC_PCI_H | |
1da177e4 LT |
3 | #ifdef __KERNEL__ |
4 | ||
5 | /* | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/types.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <asm/machdep.h> | |
18 | #include <asm/scatterlist.h> | |
19 | #include <asm/io.h> | |
20 | #include <asm/prom.h> | |
f8ef2705 | 21 | #include <asm/pci-bridge.h> |
1da177e4 LT |
22 | |
23 | #include <asm-generic/pci-dma-compat.h> | |
24 | ||
25 | #define PCIBIOS_MIN_IO 0x1000 | |
26 | #define PCIBIOS_MIN_MEM 0x10000000 | |
27 | ||
28 | struct pci_dev; | |
29 | ||
f8ef2705 PM |
30 | /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ |
31 | #define IOBASE_BRIDGE_NUMBER 0 | |
32 | #define IOBASE_MEMORY 1 | |
33 | #define IOBASE_IO 2 | |
34 | #define IOBASE_ISA_IO 3 | |
35 | #define IOBASE_ISA_MEM 4 | |
36 | ||
37 | /* | |
38 | * Set this to 1 if you want the kernel to re-assign all PCI | |
39 | * bus numbers | |
40 | */ | |
41 | extern int pci_assign_all_buses; | |
42 | #define pcibios_assign_all_busses() (pci_assign_all_buses) | |
43 | ||
1da177e4 | 44 | #define pcibios_scan_all_fns(a, b) 0 |
1da177e4 LT |
45 | |
46 | static inline void pcibios_set_master(struct pci_dev *dev) | |
47 | { | |
48 | /* No special bus mastering setup handling */ | |
49 | } | |
50 | ||
c9c3e457 | 51 | static inline void pcibios_penalize_isa_irq(int irq, int active) |
1da177e4 LT |
52 | { |
53 | /* We don't do dynamic PCI IRQ allocation */ | |
54 | } | |
55 | ||
56 | #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ | |
57 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) | |
58 | { | |
59 | if (ppc_md.pci_get_legacy_ide_irq) | |
60 | return ppc_md.pci_get_legacy_ide_irq(dev, channel); | |
61 | return channel ? 15 : 14; | |
62 | } | |
63 | ||
f8ef2705 | 64 | #ifdef CONFIG_PPC64 |
edb2d97e MW |
65 | |
66 | /* | |
67 | * We want to avoid touching the cacheline size or MWI bit. | |
68 | * pSeries firmware sets the cacheline size (which is not the cpu cacheline | |
69 | * size in all cases) and hardware treats MWI the same as memory write. | |
70 | */ | |
71 | #define PCI_DISABLE_MWI | |
1da177e4 | 72 | |
98747770 | 73 | #ifdef CONFIG_PCI |
98747770 | 74 | extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops); |
57190708 | 75 | extern struct dma_mapping_ops *get_pci_dma_ops(void); |
98747770 | 76 | |
e24c2d96 DM |
77 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, |
78 | enum pci_dma_burst_strategy *strat, | |
79 | unsigned long *strategy_parameter) | |
80 | { | |
81 | unsigned long cacheline_size; | |
82 | u8 byte; | |
83 | ||
84 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); | |
85 | if (byte == 0) | |
86 | cacheline_size = 1024; | |
87 | else | |
88 | cacheline_size = (int) byte * 4; | |
89 | ||
90 | *strat = PCI_DMA_BURST_MULTIPLE; | |
91 | *strategy_parameter = cacheline_size; | |
92 | } | |
98747770 SR |
93 | #else /* CONFIG_PCI */ |
94 | #define set_pci_dma_ops(d) | |
57190708 | 95 | #define get_pci_dma_ops() NULL |
bb4a61b6 | 96 | #endif |
e24c2d96 | 97 | |
1da177e4 LT |
98 | extern int pci_domain_nr(struct pci_bus *bus); |
99 | ||
100 | /* Decide whether to display the domain number in /proc */ | |
101 | extern int pci_proc_domain(struct pci_bus *bus); | |
102 | ||
f8ef2705 PM |
103 | #else /* 32-bit */ |
104 | ||
105 | #ifdef CONFIG_PCI | |
106 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, | |
107 | enum pci_dma_burst_strategy *strat, | |
108 | unsigned long *strategy_parameter) | |
109 | { | |
110 | *strat = PCI_DMA_BURST_INFINITY; | |
111 | *strategy_parameter = ~0UL; | |
112 | } | |
113 | #endif | |
114 | ||
f8ef2705 PM |
115 | /* Return the index of the PCI controller for device PDEV. */ |
116 | #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index | |
117 | ||
118 | /* Set the name of the bus as it appears in /proc/bus/pci */ | |
119 | static inline int pci_proc_domain(struct pci_bus *bus) | |
120 | { | |
121 | return 0; | |
122 | } | |
123 | ||
124 | #endif /* CONFIG_PPC64 */ | |
125 | ||
1da177e4 LT |
126 | struct vm_area_struct; |
127 | /* Map a range of PCI memory or I/O space for a device into user space */ | |
128 | int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, | |
129 | enum pci_mmap_state mmap_state, int write_combine); | |
130 | ||
131 | /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ | |
132 | #define HAVE_PCI_MMAP 1 | |
133 | ||
1d4454e7 RD |
134 | #if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE) |
135 | /* | |
136 | * For 64-bit kernels, pci_unmap_{single,page} is not a nop. | |
137 | * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and | |
138 | * so on are not nops. | |
139 | * and thus... | |
140 | */ | |
1da177e4 LT |
141 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ |
142 | dma_addr_t ADDR_NAME; | |
143 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ | |
144 | __u32 LEN_NAME; | |
145 | #define pci_unmap_addr(PTR, ADDR_NAME) \ | |
146 | ((PTR)->ADDR_NAME) | |
147 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ | |
148 | (((PTR)->ADDR_NAME) = (VAL)) | |
149 | #define pci_unmap_len(PTR, LEN_NAME) \ | |
150 | ((PTR)->LEN_NAME) | |
151 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ | |
152 | (((PTR)->LEN_NAME) = (VAL)) | |
153 | ||
1d4454e7 RD |
154 | #else /* 32-bit && coherent */ |
155 | ||
156 | /* pci_unmap_{page,single} is a nop so... */ | |
157 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) | |
158 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) | |
159 | #define pci_unmap_addr(PTR, ADDR_NAME) (0) | |
160 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | |
161 | #define pci_unmap_len(PTR, LEN_NAME) (0) | |
162 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | |
163 | ||
164 | #endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */ | |
165 | ||
166 | #ifdef CONFIG_PPC64 | |
167 | ||
f8ef2705 PM |
168 | /* The PCI address space does not equal the physical memory address |
169 | * space (we have an IOMMU). The IDE and SCSI device layers use | |
1da177e4 LT |
170 | * this boolean for bounce buffer decisions. |
171 | */ | |
172 | #define PCI_DMA_BUS_IS_PHYS (0) | |
f8ef2705 PM |
173 | |
174 | #else /* 32-bit */ | |
175 | ||
176 | /* The PCI address space does equal the physical memory | |
177 | * address space (no IOMMU). The IDE and SCSI device layers use | |
178 | * this boolean for bounce buffer decisions. | |
179 | */ | |
180 | #define PCI_DMA_BUS_IS_PHYS (1) | |
181 | ||
f8ef2705 | 182 | #endif /* CONFIG_PPC64 */ |
1d4454e7 | 183 | |
f8ef2705 PM |
184 | extern void pcibios_resource_to_bus(struct pci_dev *dev, |
185 | struct pci_bus_region *region, | |
1da177e4 LT |
186 | struct resource *res); |
187 | ||
f8ef2705 PM |
188 | extern void pcibios_bus_to_resource(struct pci_dev *dev, |
189 | struct resource *res, | |
43c34735 DB |
190 | struct pci_bus_region *region); |
191 | ||
f8ef2705 PM |
192 | static inline struct resource *pcibios_select_root(struct pci_dev *pdev, |
193 | struct resource *res) | |
085ae41f DM |
194 | { |
195 | struct resource *root = NULL; | |
196 | ||
197 | if (res->flags & IORESOURCE_IO) | |
198 | root = &ioport_resource; | |
199 | if (res->flags & IORESOURCE_MEM) | |
200 | root = &iomem_resource; | |
201 | ||
202 | return root; | |
203 | } | |
204 | ||
f8ef2705 | 205 | extern int unmap_bus_range(struct pci_bus *bus); |
1da177e4 | 206 | |
f8ef2705 | 207 | extern int remap_bus_range(struct pci_bus *bus); |
1da177e4 | 208 | |
f8ef2705 PM |
209 | extern void pcibios_fixup_device_resources(struct pci_dev *dev, |
210 | struct pci_bus *bus); | |
1da177e4 | 211 | |
12d04eef BH |
212 | extern void pcibios_setup_new_device(struct pci_dev *dev); |
213 | ||
facf0787 LV |
214 | extern void pcibios_claim_one_bus(struct pci_bus *b); |
215 | ||
1da177e4 LT |
216 | extern struct pci_controller *init_phb_dynamic(struct device_node *dn); |
217 | ||
ead83717 JR |
218 | extern struct pci_dev *of_create_pci_dev(struct device_node *node, |
219 | struct pci_bus *bus, int devfn); | |
220 | ||
221 | extern void of_scan_pci_bridge(struct device_node *node, | |
222 | struct pci_dev *dev); | |
223 | ||
224 | extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); | |
225 | ||
1da177e4 LT |
226 | extern int pci_read_irq_line(struct pci_dev *dev); |
227 | ||
1da177e4 LT |
228 | struct file; |
229 | extern pgprot_t pci_phys_mem_access_prot(struct file *file, | |
8b150478 | 230 | unsigned long pfn, |
1da177e4 LT |
231 | unsigned long size, |
232 | pgprot_t prot); | |
233 | ||
2311b1f2 ME |
234 | #define HAVE_ARCH_PCI_RESOURCE_TO_USER |
235 | extern void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
236 | const struct resource *rsrc, | |
e31dd6e4 | 237 | resource_size_t *start, resource_size_t *end); |
1da177e4 LT |
238 | |
239 | #endif /* __KERNEL__ */ | |
f8ef2705 | 240 | #endif /* __ASM_POWERPC_PCI_H */ |