projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f88df14b DG |
1 | #ifndef _ASM_POWERPC_PGTABLE_4K_H |
| 2 | #define _ASM_POWERPC_PGTABLE_4K_H | |
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3 | /* |
| 4 | * Entries per page directory level. The PTE level must use a 64b record | |
| 5 | * for each page table entry. The PMD and PGD level use a 32b record for | |
| 6 | * each entry by assuming that each entry is page aligned. | |
| 7 | */ | |
| 8 | #define PTE_INDEX_SIZE 9 | |
| 9 | #define PMD_INDEX_SIZE 7 | |
| 10 | #define PUD_INDEX_SIZE 7 | |
| 11 | #define PGD_INDEX_SIZE 9 | |
| 12 | ||
| ee7a76da | 13 | #ifndef __ASSEMBLY__ |
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14 | #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) |
| 15 | #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) | |
| 16 | #define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) | |
| 17 | #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) | |
| ee7a76da | 18 | #endif /* __ASSEMBLY__ */ |
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19 | |
| 20 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | |
| 21 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
| 22 | #define PTRS_PER_PUD (1 << PMD_INDEX_SIZE) | |
| 23 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
| 24 | ||
| 25 | /* PMD_SHIFT determines what a second-level page table entry can map */ | |
| 26 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
| 27 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
| 28 | #define PMD_MASK (~(PMD_SIZE-1)) | |
| 29 | ||
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30 | /* With 4k base page size, hugepage PTEs go at the PMD level */ |
| 31 | #define MIN_HUGEPTE_SHIFT PMD_SHIFT | |
| 32 | ||
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33 | /* PUD_SHIFT determines what a third-level page table entry can map */ |
| 34 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
| 35 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
| 36 | #define PUD_MASK (~(PUD_SIZE-1)) | |
| 37 | ||
| 38 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
| 39 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
| 40 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
| 41 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
| 42 | ||
| 43 | /* PTE bits */ | |
| 41743a4e | 44 | #define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */ |
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45 | #define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */ |
| 46 | #define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */ | |
| 47 | #define _PAGE_F_SECOND _PAGE_SECONDARY | |
| 48 | #define _PAGE_F_GIX _PAGE_GROUP_IX | |
| 49 | ||
| 50 | /* PTE flags to conserve for HPTE identification */ | |
| 51 | #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \ | |
| 52 | _PAGE_SECONDARY | _PAGE_GROUP_IX) | |
| 53 | ||
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54 | /* There is no 4K PFN hack on 4K pages */ |
| 55 | #define _PAGE_4K_PFN 0 | |
| 56 | ||
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57 | /* PAGE_MASK gives the right answer below, but only by accident */ |
| 58 | /* It should be preserving the high 48 bits and then specifically */ | |
| 59 | /* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */ | |
| 60 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \ | |
| 61 | _PAGE_HPTEFLAGS) | |
| 62 | ||
| 63 | /* Bits to mask out from a PMD to get to the PTE page */ | |
| 64 | #define PMD_MASKED_BITS 0 | |
| 65 | /* Bits to mask out from a PUD to get to the PMD page */ | |
| 66 | #define PUD_MASKED_BITS 0 | |
| 67 | /* Bits to mask out from a PGD to get to the PUD page */ | |
| 68 | #define PGD_MASKED_BITS 0 | |
| 69 | ||
| 70 | /* shift to put page number into pte */ | |
| 71 | #define PTE_RPN_SHIFT (17) | |
| 72 | ||
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73 | #ifdef STRICT_MM_TYPECHECKS |
| 74 | #define __real_pte(e,p) ((real_pte_t){(e)}) | |
| 75 | #define __rpte_to_pte(r) ((r).pte) | |
| 76 | #else | |
| 77 | #define __real_pte(e,p) (e) | |
| 78 | #define __rpte_to_pte(r) (__pte(r)) | |
| 79 | #endif | |
| 80 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12) | |
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81 | |
| 82 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
| 83 | do { \ | |
| 84 | index = 0; \ | |
| 85 | shift = mmu_psize_defs[psize].shift; \ | |
| 86 | ||
| 87 | #define pte_iterate_hashed_end() } while(0) | |
| 88 | ||
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89 | #ifdef CONFIG_PPC_HAS_HASH_64K |
| 90 | #define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr) | |
| 91 | #else | |
| 92 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
| 93 | #endif | |
| bf72aeba | 94 | |
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95 | /* |
| 96 | * 4-level page tables related bits | |
| 97 | */ | |
| 98 | ||
| 99 | #define pgd_none(pgd) (!pgd_val(pgd)) | |
| 100 | #define pgd_bad(pgd) (pgd_val(pgd) == 0) | |
| 101 | #define pgd_present(pgd) (pgd_val(pgd) != 0) | |
| 102 | #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0) | |
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103 | #define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS) |
| 104 | #define pgd_page(pgd) virt_to_page(pgd_page_vaddr(pgd)) | |
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105 | |
| 106 | #define pud_offset(pgdp, addr) \ | |
| 46a82b2d | 107 | (((pud_t *) pgd_page_vaddr(*(pgdp))) + \ |
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108 | (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))) |
| 109 | ||
| 110 | #define pud_ERROR(e) \ | |
| 141aa59b | 111 | printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) |
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112 | |
| 113 | #define remap_4k_pfn(vma, addr, pfn, prot) \ | |
| 114 | remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot)) | |
| f88df14b | 115 | #endif /* _ASM_POWERPC_PGTABLE_4K_H */ |