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1 | #ifndef _ASM_POWERPC_PGTABLE_4K_H |
2 | #define _ASM_POWERPC_PGTABLE_4K_H | |
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3 | /* |
4 | * Entries per page directory level. The PTE level must use a 64b record | |
5 | * for each page table entry. The PMD and PGD level use a 32b record for | |
6 | * each entry by assuming that each entry is page aligned. | |
7 | */ | |
8 | #define PTE_INDEX_SIZE 9 | |
9 | #define PMD_INDEX_SIZE 7 | |
10 | #define PUD_INDEX_SIZE 7 | |
11 | #define PGD_INDEX_SIZE 9 | |
12 | ||
13 | #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) | |
14 | #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) | |
15 | #define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) | |
16 | #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) | |
17 | ||
18 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | |
19 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
20 | #define PTRS_PER_PUD (1 << PMD_INDEX_SIZE) | |
21 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
22 | ||
23 | /* PMD_SHIFT determines what a second-level page table entry can map */ | |
24 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
25 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
26 | #define PMD_MASK (~(PMD_SIZE-1)) | |
27 | ||
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28 | /* With 4k base page size, hugepage PTEs go at the PMD level */ |
29 | #define MIN_HUGEPTE_SHIFT PMD_SHIFT | |
30 | ||
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31 | /* PUD_SHIFT determines what a third-level page table entry can map */ |
32 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
33 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
34 | #define PUD_MASK (~(PUD_SIZE-1)) | |
35 | ||
36 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
37 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
38 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
39 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
40 | ||
41 | /* PTE bits */ | |
42 | #define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */ | |
43 | #define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */ | |
44 | #define _PAGE_F_SECOND _PAGE_SECONDARY | |
45 | #define _PAGE_F_GIX _PAGE_GROUP_IX | |
46 | ||
47 | /* PTE flags to conserve for HPTE identification */ | |
48 | #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \ | |
49 | _PAGE_SECONDARY | _PAGE_GROUP_IX) | |
50 | ||
51 | /* PAGE_MASK gives the right answer below, but only by accident */ | |
52 | /* It should be preserving the high 48 bits and then specifically */ | |
53 | /* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */ | |
54 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \ | |
55 | _PAGE_HPTEFLAGS) | |
56 | ||
57 | /* Bits to mask out from a PMD to get to the PTE page */ | |
58 | #define PMD_MASKED_BITS 0 | |
59 | /* Bits to mask out from a PUD to get to the PMD page */ | |
60 | #define PUD_MASKED_BITS 0 | |
61 | /* Bits to mask out from a PGD to get to the PUD page */ | |
62 | #define PGD_MASKED_BITS 0 | |
63 | ||
64 | /* shift to put page number into pte */ | |
65 | #define PTE_RPN_SHIFT (17) | |
66 | ||
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67 | #ifdef STRICT_MM_TYPECHECKS |
68 | #define __real_pte(e,p) ((real_pte_t){(e)}) | |
69 | #define __rpte_to_pte(r) ((r).pte) | |
70 | #else | |
71 | #define __real_pte(e,p) (e) | |
72 | #define __rpte_to_pte(r) (__pte(r)) | |
73 | #endif | |
74 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12) | |
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75 | |
76 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
77 | do { \ | |
78 | index = 0; \ | |
79 | shift = mmu_psize_defs[psize].shift; \ | |
80 | ||
81 | #define pte_iterate_hashed_end() } while(0) | |
82 | ||
bf72aeba PM |
83 | #define pte_pagesize_index(pte) MMU_PAGE_4K |
84 | ||
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85 | /* |
86 | * 4-level page tables related bits | |
87 | */ | |
88 | ||
89 | #define pgd_none(pgd) (!pgd_val(pgd)) | |
90 | #define pgd_bad(pgd) (pgd_val(pgd) == 0) | |
91 | #define pgd_present(pgd) (pgd_val(pgd) != 0) | |
92 | #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0) | |
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93 | #define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS) |
94 | #define pgd_page(pgd) virt_to_page(pgd_page_vaddr(pgd)) | |
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95 | |
96 | #define pud_offset(pgdp, addr) \ | |
46a82b2d | 97 | (((pud_t *) pgd_page_vaddr(*(pgdp))) + \ |
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98 | (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))) |
99 | ||
100 | #define pud_ERROR(e) \ | |
141aa59b | 101 | printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) |
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102 | |
103 | #define remap_4k_pfn(vma, addr, pfn, prot) \ | |
104 | remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot)) | |
f88df14b | 105 | #endif /* _ASM_POWERPC_PGTABLE_4K_H */ |